RT974A Dual Channel, Ultra-Low Resistance Load Switch General Description The RT974A is a small, ultra-low R ON, dual channel load switch with EN controlled pin. The product contains two N-MOSFETs that can operate between an input voltage range of.8v to 5.5V. Also, it supports a maximum continuous current of 6A each channel. Each switch is independently controlled by EN pins ( and ), which can directly interface with low-voltage control signals. The RT974A is available in the WDFN-14TL 3x2 package with exposed pad for high power and heat dissipation. Ordering Information RT974A Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-. Suitable for use in SnPb or Pb-free soldering processes. Marking Information M : Product Code MW Package Type QW : WDFN-14TL 3x2 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) W : Date Code Features Integrated Dual Channel Load Switch Input Voltage Range :.8V to 5.5V Ultra-Low R ON Resistance R ON = 18mΩ at V IN = 5V (V DD = 5V) R ON = 18mΩ at V IN = 3.6V (V DD = 5V) R ON = 18mΩ at V IN = 1.8V (V DD = 5V) 6A Maximum Continuous Switch Current Per Channel Low Quiescent Current 75μA (Both Channels) 55μA () Low Control Input Threshold Enables Use of 1.4V/ 1.8V/2.5V/3.3V Logics Configurable Rise Time Quick Output Discharge (QOD) Adaptive Discharge Current 14T-Lead WDFN Package with Thermal Pad RoHS Compliant and Halogen Free Applications Ultrabook TM Notebooks/Netbooks Tablet PC Consumer Electronics Set-Top Boxes/Residential Gateways Telecom Systems Solid State Drives (SSD) Simplified Application Circuit VIN1 V OUT1 C IN1 RT974A C OUT1 R L1 Dual Power Supply or Dual DC/DC Converter Enable Enable VDD VIN2 SS1 SS2 C SS1 C SS2 C IN2 V OUT2 GND C OUT2 R L2 1
Pin Configurations VIN1 VIN1 VDD VIN2 VIN2 (TOP VIEW) 1 2 3 4 5 6 7 GND 15 14 13 12 11 9 8 SS1 GND SS2 WDFN-14TL 3x2 Functional Pin Description Pin No. Pin Name Pin Function 1, 2 VIN1 Input Voltage for Switch 1. Bypass this input with a ceramic capacitor to GND. Recommended voltage range for this pin for optimal R ON performance is.8v to V DD. 3 Enable Control Input for Switch 1 (Active High). Do not leave floating. 4 VDD Charge Pump Voltage Input. Power supply to the device. Recommended voltage range for this pin is 2.5V to 5.5V. 5 Enable Control Input for Switch 2 (Active High). Do not leave floating. 6, 7 VIN2 Input Voltage for Switch 2. Bypass this input with a ceramic capacitor to GND. Recommended voltage range for this pin for optimal R ON performance is.8v to V DD. 8, 9 Switch 2 Output. SS2 Switch 2 Slew Rate Control. Can be left floating. 11, 15 (Exposed Pad) GND Ground. The Exposed pad should be soldered to a large PCB and connected to GND for maximum thermal dissipation. 12 SS1 Switch 1 Slew Rate Control. Can be left floating. 13, 14 Switch 1 Output. 2
Function Block Diagram VIN1 SS1 Control Logic VDD Charge Pump GND Control Logic SS2 VIN2 Operation The RT974A contains two N-MOSFETs which controlled by EN pin independently. Enable Control Asserting ENx pin high enables the switch. Switch will turn on as the EN signal is higher than V ENH, and turn off when the EN signal is lower than V ENL. Thus, it can operate under low voltage logic, please refer to the electrical characteristics. This pin cannot be left floating and must be tied either high or low voltage for proper functionality. Charge Pump Provides sufficient bias voltage to both N-MOSFETs. Adjustable Rise Time Connecting a capacitor to GND on the SSx pin sets the slew rate for each channel. It could also be used to prevent in-rush current. 3
Absolute Maximum Ratings (Note 1) VIN1, VIN2,,, VDD,,, SS1, SS2 -------------------------------------------------------.3V to 6V Maximum Continuous Switch Current Per Channel, IMAX ------------------------------------------------------- 6A Maximum Pulsed Switch Current, Pulse <μs, 2% Duty Cycle Per Channel, IPLS -------------------- 8A Power Dissipation, P D @ T A = WDFN-14TL 3x2 ------------------------------------------------------------------------------------------------------------ 3.11W Package Thermal Resistance (Note 2) WDFN-14TL 3x2, θ JA ------------------------------------------------------------------------------------------------------- 32.1 C/W WDFN-14TL 3x2, θ JC ------------------------------------------------------------------------------------------------------ 6.3 C/W Junction Temperature ------------------------------------------------------------------------------------------------------ 15 C Lead Temperature (Soldering, sec.) -------------------------------------------------------------------------------- 26 C Storage Temperature Range --------------------------------------------------------------------------------------------- 65 C to 15 C ESD Susceptibility (Note 3) HBM (Human Body Model) ----------------------------------------------------------------------------------------------- 2kV CDM (Charged-Device Model) ------------------------------------------------------------------------------------------- 1kV Recommended Operating Conditions (Note 4) V IN1,2, Input Voltage Range ----------------------------------------------------------------------------------------------.8V to V DD V DD, Charge Pump Voltage Input Range ------------------------------------------------------------------------------ 2.5V to 5.5V V,2, EN Voltage Range ------------------------------------------------------------------------------------------------ V to V DD Junction Temperature Range --------------------------------------------------------------------------------------------- to 1 Ambient Temperature Range --------------------------------------------------------------------------------------------- to Electrical Characteristics (V IN =.8V to 5.5V, T A =, unless otherwise specified) EN Input Supply Input Voltage Parameter Symbol Test Conditions Min Typ Max Unit High-Level V ENH 1.4 -- 5.5 Low-Level V ENL --.5 ENx Pin Input Leakage Current I EN V EN = 5.5V -- -- 1 A V (V DD = 5V, V IN =.8V to V DD, T A =, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Power Supplies and Currents V DD Quiescent Current (Both Channels) V DD Quiescent Current () I IN(VDD, ON) I OUT1 = I OUT2 = A V IN1,2 = V,2 = V DD = 5V I OUT1 = I OUT2 = A I IN(VDD, ON) V IN1,2 = V = V DD = 5V, V = GND -- 75 115 A -- 55 -- A V DD Shutdown Current I IN(VDD, OFF) V,2 = GND, V OUT1,2 = V -- -- 2 A 4
Parameter Symbol Test Conditions Min Typ Max Unit VIN1,2 Off-State Supply Current (Per Channel) Resistance Characteristics ON-State Resistance IIN(VIN, OFF) RON V,2 = GND,,2 = V IOUT = ma, VDD = 5V VIN1,2 = 5V -- -- 8 VIN1,2 = 3.3V -- -- 3 VIN1,2 = 1.8V -- -- 2 VIN1,2 =.8V -- -- 1 VIN = 5V -- 18 25 VIN = 3.3V -- 18 25 VIN = 1.8V -- 18 25 VIN = 1.5V -- 18 25 VIN = 1.2V -- 18 25 VIN =.8V -- 18 25 Output Pull-down Resistance RPD VEN = V, VIN = 5V, IOUT = 15mA -- 2 A m (V DD = 3.3V, V IN =.8V to V DD, T A =, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Power Supplies and Currents VDD Quiescent Current (Both Channels) VDD Quiescent Current () IIN(VDD, ON) IIN(VDD, ON) IOUT1 = IOUT2 = A VIN1,2 = V,2 = VDD = 3.3V IOUT1 = IOUT2 = A VIN1,2 = V = VDD = 3.3V V = GND -- 4 -- A -- -- -- A VDD Shutdown Current IIN(VDD, OFF) V,2 = GND,,2 = V -- -- 2 A VIN1,2 Off-State Supply Current (Per Channel) Resistance Characteristics On-State Resistance IIN(VIN, OFF) RON V,2 = GND,,2 = V IOUT = ma, VDD = 3.3V VIN1,2 = 3.3V -- -- 3 VIN1,2 = 1.8V -- -- 2 VIN1,2 = 1.2V -- -- 2 VIN1,2 =.8V -- -- 1 VIN = 3.3V -- 22 -- VIN = 2.5V -- -- VIN = 1.8V -- 19 -- VIN = 1.5V -- 18 -- VIN = 1.2V -- 18 -- VIN =.8V -- 18 -- Output Pull-down Resistance RPD VEN = V, VIN = 3.3V, IOUT = 1mA -- 26 Note 1. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured at T A = on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θjc is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. A m 5
Typical Application Circuit V IN1.8V to 5.5V C IN1 1, 2 VIN1 13, 14 C IN2 RT974A C OUT1 R L1 V OUT1 Enable V DD 2.5V to 5.5V 3 4 VDD 12 SS1 C SS1 Enable 5 SS2 V IN2.8V to 5.5V C IN3 6, 7 VIN2 C IN4 8, 9 C SS2 V OUT2 11, 15 (Exposed Pad) GND C OUT2 R L2 Timing Diagram VIN VOUT V OUT + - C IN RT974A C OUT R L Enable EN VDD GND Shown for Clarity TEST CIRCUIT V EN 5% 5% t ON t OFF t r t f V OUT 5% 5% V OUT 9% 9% % % t D Figure 1. Test Circuit and t ON /t OFF Waveforms 6
Timing Characteristics Parameter Test Conditions Min Typ Max Unit VIN = EN = VDD = 5V, T A = 25 C T ON Turn-On Time R L =, C OUT =.1 F, C SS = pf -- 12 -- T OFF Turn-Off Time R L =, C OUT =.1 F, C SS = pf -- 4 -- T R VOUT Rise Time R L =, C OUT =.1 F, C SS = pf -- 135 -- s T F VOUT Fall Time R L =, C OUT =.1 F, C SS = pf -- 3 -- T D ON Delay Time R L =, C OUT =.1 F, C SS = pf -- 4 -- VIN =.8V, EN = VDD = 5V, T A = 25 C T ON Turn-On Time R L =, C OUT =.1 F, C SS = pf -- 58 -- T OFF Turn-Off Time R L =, C OUT =.1 F, C SS = pf -- 8 -- T R VOUT Rise Time R L =, C OUT =.1 F, C SS = pf -- 28 -- s T F VOUT Fall Time R L =, C OUT =.1 F, C SS = pf -- -- T D ON Delay Time R L =, C OUT =.1 F, C SS = pf -- 4 -- VIN = EN = VDD = 3.3V, T A = 25 C T ON Turn-On Time R L =, C OUT =.1 F, C SS = pf -- 96 -- T OFF Turn-Off Time R L =, C OUT =.1 F, C SS = pf -- 6 -- T R VOUT Rise Time R L =, C OUT =.1 F, C SS = pf -- 94 -- s T F VOUT Fall Time R L =, C OUT =.1 F, C SS = pf -- 3 -- T D ON Delay Time R L =, C OUT =.1 F, C SS = pf -- 4 -- VIN =.8V, EN = VDD = 3.3V, T A = 25 C T ON Turn-On Time R L =, C OUT =.1 F, C SS = pf -- 56 -- T OFF Turn-Off Time R L =, C OUT =.1 F, C SS = pf -- 175 -- T R VOUT Rise Time R L =, C OUT =.1 F, C SS = pf -- 28 -- s T F VOUT Fall Time R L =, C OUT =.1 F, C SS = pf -- 4 -- T D ON Delay Time R L =, C OUT =.1 F, C SS = pf -- 4 -- 7
Typical Operating Characteristics Quiescent Current vs. VDD Quiescent Curren vs. VDD 5 Both Channels 5 Quiescent Current (µa) 4 Quiescent Current (µa) 4 VIN1 = VIN2 = VDD, V = V = 5V, VOUT = Open, VUT1 = On, VUT2 = On VIN1 = VIN2 = VDD, V = V, V = 5V, VOUT = Open, VUT1 = Off, VUT2 = On 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VDD (V) 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VDD (V) Shut-Down Current vs. VDD Off-State Supply Current vs. Input Voltage Shut-Down Current (µa) 1..8.6.4.2. Both Channels VIN1 = VIN2 = VDD, V = V = V, VOUT = V Off-State Supply Current (µa).5.4.3.2.1. -.1 -.2 -.3 -.4 -.5 VDD = 5.5V, VEN = V, VOUT = V 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VDD (V) On-Resistance vs. Temperature On-Resistance vs. Temperature 4 On-Resistance (mω) 35 25 VIN = 2.5V VIN = 1.8V VIN = 1.5V VIN = 1.2V VIN = 1.5V VIN =.8V On-Resistance (mω) 25 15 VIN =.8V VIN = 1.5V VIN = 1.2V VIN = 1.5V VIN = 1.8V VIN = 2.5V VIN = 3.3V VIN = 3.6V VIN = 4.2V VIN = 5V VIN = 5.5V 15 VDD = 2.5V, IOUT = ma -4-15 35 6 85 Temperature ( C) VDD = 5.5V, IOUT = ma -4-15 35 6 85 Temperature ( C) 8
On-Resistance vs. Input Voltage On-Resistance vs. Input Voltage 4 35 On-Resistance (mω) 25 15 On-Resistance (mω) 25 15 VDD = 2.5V, IOUT = ma VDD = 5.5V, IOUT = ma.8 1.14 1.48 1.82 2.16 2.5 On-Resistance vs. Input Voltage Discharge Resistance vs. Input Voltage On-Resistance (mω) 28 26 24 22 18 16 VDD = 2.5V VDD = 3.3V VDD = 3.6V VDD = 4.2V VDD = 5V VDD = 5.5V TA =, IOUT = ma Discharge Resistance (Ω) 4 36 3 28 24 16 1 8 4 VDD = 5.5V, VEN = V Output Voltage vs. Enable Voltage On Delay Time vs. Input Voltage 2.6 2.4 2.2 55 Output Voltage (V) 2. 1.8 1.6 1.4 1.2 1..8.6 VDD = 2.5V VDD = 3.3V VDD = 3.6V VDD = 4.2V VDD = 5V VDD = 5.5V On Delay Time (ms) 5 45 4 35.4.2. VIN = 2.5V, TA = 25 VDD = 2.5V, CSS = 1nF.5 1 1.5 2 2.5 Enable Voltage (V).8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 9
On Delay Time vs. Input Voltage On Delay Time vs. VDD VDD = 5.5V, CSS = 1nF VIN1 = VIN2 = 2.5V, CSS = 1nF On Delay Time (ms) 55 5 45 4 35 On Delay Time (µs) 5 4 25 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VDD (V) Off Fall Time vs. Input Voltage Off Fall Time vs. Input Voltage 8 VDD = 2.5V, CSS = 1nF 4 VDD = 5.5V, CSS = 1nF 7 35 Off Fall Time (µs) 6 5 4 Off Fall Time (µs) 25 15 5.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 Off Fall Time vs. VDD Off Time vs. Input Voltage 5 VIN = 2.5V, CSS = 1nF VDD = 2.5V, CSS = 1nF Off Fall Time (µs) 4 3 2 Off Time (µs) 25 15 1 5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VDD (V).8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6
Off Time vs. Input Voltage Off Time vs. VDD 15 1 15 Off Time (µs) 9 6 Off Time (µs) VDD = 5.5V, CSS = 1nF 5 VIN = 2.5V, CSS = 1nF 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VDD (V) On Time vs. Input Voltage On Time vs. Input Voltage 1 On Time (ms) 9 8 7 On Time (ms) 14 1 8 5 4 VDD = 2.5V, CSS = 1nF.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 4 VDD = 5.5V, CSS = 1nF On Time vs. VDD On Rising Time vs. Input Voltage On Time (ms) 9 8 7 On Rising Time (µs) 8 4 VIN = 2.5V, CSS = 1nF 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VDD (V) VDD = 2.5V, CSS = 1nF.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 11
On Rising Time vs. Input Voltage On Rising Time vs. VDD 18 On Rising Time (µs) 1 14 1 8 4 On Rising Time (µs) 9 8 7 VDD = 5.5V, CSS = 1nF 5 VIN = 2.5V, CSS = 1nF 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VDD (V) Turn-On Response Time Turn-On Response Time (5mV/Div) (5mV/Div) (5mV/Div) (5mV/Div) VIN =.8V, VDD = 2.5V, CIN = 1μF, COUT =.1μF, RL = Ω VIN =.8V, VDD = 5V, CIN = 1μF, COUT =.1μF, RL = Ω Time (5μs/Div) Time (5μs/Div) Turn-On Response Time Turn-On Response Time (2V/Div) (2V/Div) VIN = 2.5V, VDD = 2.5V, CIN = 1μF, COUT =.1μF, RL = Ω VIN = 5V, VDD = 5V, CIN = 1μF, COUT =.1μF, RL = Ω Time (5μs/Div) Time (5μs/Div) 12
Turn-Off Response Time Turn-Off Response Time (5mV/Div) (5mV/Div) (5mV/Div) VIN =.8V, VDD = 2.5V, CIN = 1μF, COUT =.1μF, RL = Ω (5mV/Div) VIN =.8V, VDD = 5V, CIN = 1μF, COUT =.1μF, RL = Ω Time (5μs/Div) Time (5μs/Div) Turn-Off Response Time Turn-Off Response Time (2V/Div) (2V/Div) VIN = 2.5V, VDD = 2.5V, CIN = 1μF, COUT =.1μF, RL = Ω VIN = 5V, VDD = 5V, CIN = 1μF, COUT =.1μF, RL = Ω Time (5μs/Div) Time (5μs/Div) 13
Application Information The RT974A is a small, ultra-low R ON, dual channel load switch with EN controlled pins, and is equipped with a charge pump circuitry to drive the internal N-MOSFET switch. The product contains two N-channel MOSFETs that can operate between input voltage range of.8v to 5.5V. It also supports a maximum continuous current of 6A each channel and a maximum pulsed switch current of 8A (pulse <μs). Each switch is independently controlled by EN pins ( and ), which can directly interface with low-voltage control signals. Input and Output VINx (input) is the power source connection to the internal circuitry and the Drain of the MOSFET. VOUTx (output) is the Source of the MOSFET. In a typical application, current flows through the switch from VINx to VOUTx toward the load. If VOUTx is greater than VINx, current will flow from VOUTx to VINx since the MOSFET is bidirectional when on. Chip Enable Input The switch will be disabled when the ENx pin is in a logic low condition. During this condition, the internal circuitry and MOSFET will be turned off, reducing the supply current to.1μa typical. Floating the ENx may cause unpredictable operation. ENx should not be allowed to go negative with respect to GND. Supply Filter/Bypass Capacitor A 1μF or greater low-esr ceramic capacitor from VIN to GND, located at the device is strongly recommended to prevent the input voltage drooping during high current application. However, higher capacitor values will further reduce the voltage droop on the input. Furthermore, without the bypass capacitor, an output short may cause sufficient ringing on the input (from source lead inductance) to destroy the internal control circuitry. The input transient must not exceed 6V of the absolute maximum supply voltage even for a short duration. Output Filter Capacitor A to 1 ratio of supply capacitor to output capacitor from VOUTx to GND is recommended to prevent the in-rush currents during low supply voltage start-up. Because the integrated body diode in the load switch, higher output capacitor can cause output voltage to exceed supply voltage when the system supply is removed. A output capacitor smaller then supply capacitor is recommended to prevent the current flow through the integrated body diode from output to system supply. Charge Pump The switch has an internal charge pump circuit that is supplied from VDD pin to afford sufficient bias voltage to both N-channel MOSFETs. The recommended VDD voltage range is 2.5V to 5.5V, and must above VIN for optimal ultra-low R ON performance, or the value of R ON will be greater than the value listed in the ELECTRICAL CHARACTERISTICS table. On-Resistance vs. Input Voltage (VIN > VDD, ) On-Resistance (mω) 9 8 7 6 5 4 TA =, IOUT = ma VDD = 2.5V VDD = 3.3V VDD = 3.6V VDD = 4.2V VDD = 5V VDD = 5.5V Adjustable Rise Time The RT974A provides an external adjustable rise time function. The adjustable rise time is used to prevent large inrush current and output voltage overshoot while the switch is being powered-up. The external capacitor connected from SS pins to GND is charged by a 1μA current source to set each rise time. 14
Discharge Operation When ENx is low, the RT974A will discharge the system residual voltage using internal MOSFET connected between the VOUTx and GND. The discharge current depends on the voltage at the VOUTx pin. When the voltage at the VOUTx is lower than.8v, the RT974A will fully turn the internal MOSFET on to pull the VOUTx low. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : Maximum Power Dissipation (W) 1 3.5 Four-Layer PCB 3. 2.5 2. 1.5 1..5. 25 5 75 125 Ambient Temperature ( C) Figure 2. Derating Curve of Maximum Power Dissipation P D(MAX) = (T J(MAX) T A ) / θ JA where T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and θ JA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 1. The junction to ambient thermal resistance, θ JA, is layout dependent. For WDFN-14TL 3x2 package, the thermal resistance, θ JA, is 32.1 C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at T A = can be calculated by the following formula : P D(MAX) = (1 ) / (32.1 C/W) = 3.11W for WDFN-14TL 3x2 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θ JA. The derating curve in Figure 2 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 15
Outline Dimension 2 1 2 1 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min. Max. Min. Max. A.7.8.28.31 A1..5..2 A3.175.25.7. b.15.25.6. b1.55.65.22.26 D 2.9 3..114.122 D2 2.45 2.55.96. E 1.9 2..75.83 E2.85.95.33.37 e K K1.4.16..8.1.5 L..4.12.16 W-Type 14TL DFN 3x2 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1 st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. 16