High-speed low-power 2D DCT Accelerator. EECS 6321 Yuxiang Chen, Xinyi Chang, Song Wang Electrical Engineering, Columbia University Prof.

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High-speed low-power 2D DCT Accelerator EECS 6321 Yuxiang Chen, Xinyi Chang, Song Wang Electrical Engineering, Columbia University Prof. Mingoo Seok

Project Goal Project Goal Execute a full VLSI design flow from RTL design to place and route with custom standard cell. Demonstrate a low power design methodology using standard tool flows Steps Matlab implementation of DCT algorithm utilizing RTL Implementation of DCT and Approximate Adder, tested using matlab generated random inputs. Approximate Adder Physical Layout with standard cell dimensions Synthesize/post-synthesize RTL to gate level netlist. Measured delay and power APR with IBM 130nm standard cell and APPROX_ADDER cell. Fixed DRC errors. LVS Free.

Methodology Overview Synopsys Design Compile Matlab Model RTL Design Synthesis & Timing Analysis Encounter Auto Place & Route Function Verification ModelSim Prime Time Analysis

DCT with Loeffler Algorithm Loeffler Algorithm Number of multiplications reach the theoretical low limit. 4 Stages MultAddSub Blocks [1]M. Jridi and A. Alfalou,

Canonical signed digit (CSD) representation CSD Signed representation containing the fewest number of nonzero bits Effective way to carry out constant multiplier for DCT. Number of additions and subtractions will be minimized. Identified common elements in CSD constant coefficients and shared required resource X = 2^a ± 2^b ± 2^c ±.. [1]M. Jridi and A. Alfalou,

RTL Block Diagram for DCT-1 Stage 1 Stage 2 Stage 3 Stage 4

RTL Block Diagram for DCT-2 21 Cycles from first sets of input to last sets of output. Data feeds every 19 cycles

Semi-custom Approximate Adder conventional MA approximate adder Removal of some series connected transistors will facilitate faster charging/discharging of node capacitances. Complexity reduction by removal of transistors also aids in reducing dynamic power. Use approximate FA cells only in LSBs, thus ensuring that the final output quality does not degrade too much Measure the output quality using MSE (mean square error) [3] V. Gupta, D. Mohapatra, A. Raghunathan and K. Roy

Design Compiler Combine scx3_cmos8rf_lpvt_tt_1p2v_25c.db and cmrf8sf_custom.db to synthesize the whole design Set_don t_touch our customized cell approximate adder Use the smallest driven cell INVXLTS for all the inputs to get the maximum optimization

Netlist Simulation Simulate the function and timing in modelsim

Semi-custom Approximate Adder

Abstract View Detailed Blockage abstract Draw blockage manually to mitigate defects of APR tool

Floorplan - final Implementation Size: 710.2 (W) x 730.2 (H) Challenges: Match custom cell boundary to power grid. Antenna Issue. APR routing challenge.

Approximate Adder Accuracy Comparison Number of Approximate Adder MSE PSNR 1 3.53 42.68 db 2 13.46 36.87 db 3 41.95 31.94 db

Result With Adder Total Power (mw) Area (um^2) Frequency (ns) A B C 70.753 66.254 63.899 191558.88 182021.76 174057.11 225.7 225.7 225.7 State of the Art Power (mw) Area (mm^2) DCT Core 29.92 0.569 Adder A: RCA with full adders. Adder B: RCA with LSB 3 bits synthesized approximate adder. Adder C: RCA with LSB 3 bits customized approximate adder.

Reference [1] M. Jridi, A. Alfalou, "A low-power, high-speed DCT architecture for image compression: Principle and implementation," 18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC), 2010, pp. 304-309. [2] Y. H. Chen, T. Y. Chang and C. Y. Li, "Highthroughput DA-based DCT with high accuracy error-compensated adder tree", IEEE Trans. VeryLarge Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp.709-714, 2011 [3] V. Gupta, D. Mohapatra, A. Raghunathan and K. Roy, "Low-power digital signal processing using approximate adders", IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 1, pp.124-137, 2013 [4] P. Kulkarni, P. Gupta, and M. D. Ercegovac, Trading accuracy for power in a multiplier architecture, J. Low Power Electron., vol. 7, no. 4, pp.490 501, 2011. [5] Y. V. Ivanov and C. J. Bleakley, Real-time h.264 video encoding in software with fast mode decision and dynamic complexity control, ACM Trans. Multimedia Comput. Commun. Applicat., vol. 6, pp. 5:1 5:21, Feb. 2010.

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