, and Reverse Suppy Protection Controer FEATURES n Wide Operating Votage Range: 2.5V to 34V n Overvotage Protection to 6V n Reverse Suppy Protection to 4V n Bocks 5Hz and 6Hz AC Power n No Input Capacitor or TVS Required for Most Appications n Adjustabe Undervotage and Overvotage Protection Range n Charge Pump Enhances Externa N-Channe MOSFET n Low Operating Current: 125µA n Low Shutdown Current: 1µA n Faut Status Output n Compact 8-Lead, 3mm 2mm DFN and TSOT-23 (ThinSOT ) Packages APPLICATIONS n Portabe Instrumentation n Industria Automation n Laptops n Automotive DESCRIPTION The LTC 4365 protects appications where power suppy input votages may be too high, too ow or even negative. It does this by controing the gate votages of a pair of externa N-channe MOSFETs to ensure that the output stays within a safe operating range. The can withstand votages between 4V and 6V and has an operating range of 2.5V to 34V, whie consuming ony 125µA in norma operation. Two comparator inputs aow configuration of the overvotage () and undervotage () set points using an externa resistive divider. A shutdown pin provides externa contro for enabing and disabing the MOSFETs as we as pacing the device in a ow current shutdown state. A faut output provides status of the gate pin puing ow. A faut is indicated when the part is in shutdown or the input votage is outside the and set points. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks and ThinSOT, No R SENSE and Hot Swap are trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. TYPICAL APPLICATION 12V Automotive Appication Load Protected from Reverse and Overvotage at 12V Si4946 3A 3V = 3.5V = 18V 51k VALID WINDOW 182k 1V/DIV 243k 3V 59k = 18V = 3.5V 1s/DIV 4365 TA1b 4365 TA1a 1
ABSOLUTE MAXIMUM RATINGS Suppy Votage (Note 1)... 4V to 6V Input Votages (Note 3),....3V to 6V....3V to 6V....3V to 4V Output Votages (Note 4)....3V to 6V... 4V to 45V Operating Ambient Temperature Range C... C to 7 C I... 4 C to 85 C H... 4 C to 125 C Storage Temperature Range... 65 C to 15 C Lead Temperature (Sodering, 1 sec) for TSOT Ony...3 C PIN CONFIGURATION TOP VIEW 1 2 3 4 9 8 7 6 5 1 2 3 4 TOP VIEW 8 7 6 5 DDB PACKAGE 8-LEAD (3mm 2mm) PLASTIC DFN T JMAX = 15 C, θ JA = 76 C/W EXPOSED PAD (PIN 9) PCB GROUND CONNECTION OPTIONAL TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 T JMAX = 15 C, θ JA = 195 C/W ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE CDDB#TRMPBF CDDB#TRPBF LFKS 8-Lead (3mm 2mm) Pastic DFN C to 7 C IDDB#TRMPBF IDDB#TRPBF LFKS 8-Lead (3mm 2mm) Pastic DFN 4 C to 85 C HDDB#TRMPBF HDDB#TRPBF LFKS 8-Lead (3mm 2mm) Pastic DFN 4 C to 125 C CTS8#TRMPBF CTS8#TRPBF LTFKT 8-Lead Pastic TSOT-23 C to 7 C ITS8#TRMPBF ITS8#TRPBF LTFKT 8-Lead Pastic TSOT-23 4 C to 85 C HTS8#TRMPBF HTS8#TRPBF LTFKT 8-Lead Pastic TSOT-23 4 C to 125 C TRM = 5 pieces. *Temperature grades are identified by a abe on the shipping container. Consut LTC Marketing for parts specified with wider operating temperature ranges. Consut LTC Marketing for information on ead based finish parts. For more information on ead free part marking, go to: http://www.inear.com/eadfree/ For more information on tape and ree specifications, go to: http://www.inear.com/tapeandree/ 2
ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. = 2.5V to 34V, uness otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS, Input Votage Range Operating Range Protection Range I VIN Input Suppy Current = V, =, 4 C to 85 C = V, =, 4 C to 125 C = 2.5V I VIN(R) Reverse Input Suppy Current = 4V, = V 1.2 1.8 ma (LO) Input Suppy Undervotage Lockout Rising 1.8 2.2 2.4 V I VOUT Input Current = V, = = 2.5V, = = 4V, = V ΔV N-Channe Gate Drive (- ) = = 5.V, I = 1µA = = 12V to 34V, I = 1µA I (UP) N-Channe Gate Pu Up Current = = = 12V 12 2 3 µa I (FAST) N-Channe Gate Fast Pu Down Current Fast Shutdown, = 2V, = = 12V 31 5 72 ma I (SLOW) N-Channe Gate Gente Pu Down Current Gente Shutdown, = 2V, = = 12V 5 9 15 µa t (FAST) N-Channe Gate Fast Turn Off Deay C = 2.2nF, or Faut 2 4 µs t (SLOW) N-Channe Gente Turn Off Deay C = 2.2nF, Faing, = = 12V 15 25 35 µs t RECERY Recovery Deay Time = 12V, Power Good to DV > V 26 36 49 ms, V Input Threshod Votage Faing ΔV = V 492.5 5 57.5 mv V Input Threshod Votage Rising ΔV = V 492.5 5 57.5 mv V HYST Input Hysteresis 2 25 32 mv V HYST Input Hysteresis 2 25 32 mv I LEAK, Leakage Current V =.5V, = 34V ±1 na t, Faut Propagation Deay Overdrive = 5mV = = 12V 2.5 4 3 7.4 1 1 25 6 1 2 3.6 8.4 34 6 5 1 15 3 25 5 4.2 9.8 V V µa µa µa µa µa µa 1 2 µs V Input Threshod Faing to ΔV = V.4.75 1.2 V I Input Current =.75V, = 34V ±1 na t START Deay Coming Out of Shutdown Mode Rising to ΔV > V, = = 12V 4 8 12 µs t (F) to Asserted = = 12V 1.5 3 µs t LOWPWR Deay from Turn Off to Low Power Operation = = 12V 26 36 55 ms V OL Output Votage Low I = 5µA.15.4 V I Leakage Current = 5V, = 34V ±2 na Note 1. Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2. A currents into pins are positive; a votages are referenced to uness otherwise noted. Note 3. These pins can be tied to votages beow.3v through a resistor that imits the current beow 1mA. Note 4. The pin is referenced to and does not exceed 44V for the entire operating range. V V 3
TYPICAL PERFORMANCE CHARACTERISTICS I VIN (µa) 1 8 6 4 2 Operating Current vs Temperature Shutdown Current vs Current vs ( 4 to 6V) = 2.5V = = 2.5V = 34V = 12V I VIN (µa) 3 25 2 15 1 5 = = V 125 C 45 C 7 C 25 C I VIN (µa) 4 4 8 12 = = V 25 C 45 C 125 C 25 C 5 25 25 5 75 1 125 TEMPERATURE ( C) 5 1 15 2 25 3 35 (V) 16 5 25 25 5 75 (V) 4365 G1 4365 G2 4365 G3 2 16 Operating Current vs Temperature = 2.5V = = 34V 2 15 Shutdown Current vs Temperature = V = Current vs Reverse 25 = V 2 45 C I VOUT (µa) 12 8 4 = 12V = 2.5V I VOUT (µa) 1 5 = 34V = 12V I VOUT (µa) 15 1 5 25 C 125 C = 2.5V 5 25 25 5 75 1 125 TEMPERATURE (C ) 5 25 25 5 75 1 125 TEMPERATURE (C ) 1 2 3 4 5 (V) 4365 G4 4365 G5 4365 G6 V (V) 12 Drive vs = V 1 8 = 6 4 V (V) Drive vs Temperature 1 = = 34V 8 = = 12V I = 1µA 6 4 I (UP) (µa) Current vs Drive 25 = = 12V 125 C 2 15 25 C 1 45 C 2 T = 25 C I = 1µA 5 1 15 2 25 3 35 (V) 2 5 = = 2.5V 25 25 5 75 1 125 TEMPERATURE ( C) 5 2 4 6 8 1 V (V) 4365 G7 4365 G8 4365 G9 4
TYPICAL PERFORMANCE CHARACTERISTICS Threshod vs Temperature 57.5 = = 12V 55. 52.5 Threshod vs Temperature 57.5 = = 12V 55. 52.5 1..75 / Leakage vs Temperature V / =.5V = 12V V (mv) 5. V (mv) 5. I LEAK (na).5 497.5 495. 497.5 495..25 492.5 5 25 25 5 75 1 125 TEMPERATURE ( C) 492.5 5 25 25 5 75 1 125 TEMPERATURE ( C) 75 25 25 75 125 175 TEMPERATURE ( C) 4365 G1 4365 G11 4365 G12 2 16 / Propagation Deay vs Overdrive = = 12V T = 25 C 5 4 Recovery Deay Time vs Temperature = 34V Recovery Deay Time vs 5 45 C 125 C 4 t (µs) 12 8 t RECERY (ms) 3 2 = 12V t RECERY (ms) 3 2 25 C 4 1 = 2.5V 1 1 1 1 1 ERDRIVE (mv) 5 25 25 5 75 1 125 TEMPERATURE ( C) 5 1 15 2 25 3 35 (V) 4365 G13 4365 G14 4365 G15 AC Bocking Turn-On Timing Turn-Off Timing 1V/DIV 5V/DIV 1µF, 12Ω LOAD ON 6V SI9945 DUAL NCH MOSFET = 12V 5V/DIV 1µF, 12Ω LOAD ON 6V SI9945 DUAL NCH MOSFET 2V/DIV 1µF, 1k LOAD ON 6V DUAL NCH MOSFET 3V/DIV 3V/DIV 2.5ms/DIV 4365 G16 25µs/DIV 4365 G17 25µs/DIV 4365 G18 5
PIN FUNCTIONS Exposed Pad: Connect to device ground. : Faut Indication Output. This high votage open drain output is pued ow if is beow its monitor threshod, if is above its monitor threshod, if is ow, or if has not risen above (LO). : Gate Drive Output for Externa N-channe MOSFETs. An interna charge pump provides 2µA of pu-up current and up to 9.8V of enhancement to the gate of an externa N-channe MOSFET. When turned off, is pued just beow the ower of or. When goes negative, is automaticay connected to. : Device Ground. : Overvotage Comparator Input. Connect this pin to an externa resistive divider to set the desired overvotage faut threshod. Input to an accurate, fast (1µs) comparator with a.5v rising threshod and 25mV of hysteresis. When rises above its threshod, a 5mA current sink pus down on the output. When fas back beow.475v, and after a 36ms recovery deay waiting period, the charge pump is enabed. The ow eakage current of the input aows the use of arge vaued resistors for the externa resistive divider. Connect to if unused. : Shutdown Contro Input. high enabes the charge pump which in turn enhances the gate of an externa N-channe MOSFET. A ow on generates a pu down on the output with a 9µA current sink and paces the in ow current mode (1µA). If unused, connect to. If goes beow ground, or if rings to 6V, use a current imiting resistor of at east 1k. : Undervotage Comparator Input. Connect this pin to an externa resistive divider to set the desired undervotage faut threshod. Input to an accurate, fast (1µs) comparator with a.5v faing threshod and 25mV of hysteresis. When fas beow its threshod, a 5mA current sink pus down on the output. When rises back above.525v, and after a 36ms recovery deay waiting period, the charge pump is enabed. The ow eakage current of the input aows the use of arge vaued resistors for the externa resistive divider. If unused, connect to. Whie connected to, if goes beow ground, or if rings to 6V, use a current imiting resistor of at east 1k. : Power Suppy Input. Maximum protection range: 4V to 6V. Operating range: 2.5V to 34V. : Output Votage Sense Input. This pin senses the votage at the output side of the externa N-channe MOSFET. The charge pump votage is referenced to. It is used as the charge pump input when is greater than approximatey 6.5V. 6
BLOCK DIAGRAM 4V TO 6V REVERSE PROTECTION LDO 5TERNAL SUPPLY 6.5TERNAL SUPPLY CLOSES SWITCH WHEN IS NEGATIVE ENABLE CHARGE PUMP f = 4kHz I 2.2V LO DELAY TIMERS LOGIC OFF TURN OFF 5mA 9µA 25mV PULLDOWN HYSTERESIS.5V 4365 BD 7
OPERATION Many of today s eectronic systems get their power from externa sources such as a wa wart adapter, batteries and custom power suppies. These power sources are often unreiabe, wired incorrecty, out of spec, or just pain wrong. This can ead to suppy votages that are too high, too ow, or even negative. If these power sources are appied directy to the eectronic systems, the systems coud be subject to damage. The is an input votage faut protection N-channe MOSFET controer. The part isoates an input suppy from its oad to protect the oad from unexpected suppy votage conditions, whie providing a ow oss path for quaified power. To protect eectronic systems from impropery connected power suppies, system designers wi often add discrete diodes, transistors and high votage comparators. The high votage comparators enabe system power ony if the input suppy fas within a desired votage window. A Schottky diode or P-channe MOSFET typicay added in series with the suppy protects against reverse suppy connections. The provides accurate overvotage and undervotage comparators to ensure that power is appied to the system ony if the input suppy meets the user seectabe votage window. Reverse suppy protection circuits automaticay isoate the oad from negative input votages. During norma operation, a high votage charge pump enhances the gate of externa N-channe power MOSFETs. Power consumption is 1µA during shutdown and 125µA whie operating. The integrates a these functions in tiny TSOT-23 and 3mm 2mm DFN packages. APPLICATIONS INFORMATION The is an N-channe MOSFET controer that protects a oad from fauty suppy connections. A basic appication circuit using the is shown in Figure 1. The circuit provides a ow oss connection from to as ong as the votage at is between 3.5V and 12V NOMINAL R3 182k R2 243k R1 59k M1 R5 1k SI4946 6V DUAL 4365 F1 M2 = 18V = 3.5V C OUT 1µF 3.5V TO 18V 18V. Votages at outside of the 3.5V to 18V range are prevented from getting to the oad and can be as high as 6V and as ow as 4V. The circuit of Figure 1 protects against negative votages at as shown. No other externa components are needed. During norma operation, the provides up to 9.8V of gate enhancement to the externa back-to-back N-channe MOSFETs. This turns on the MOSFET, thus connecting the oad at to the suppy at. Drive The turns on the externa N-channe MOSFETs by driving the pin above. The votage difference between the and pins (gate drive) is a function of and. Figure 1. Protects Load from 4V to 6V Fauts 8
APPLICATIONS INFORMATION Figure 2 highights the dependence of the gate drive on and. When system power is first turned on ( ow to high, = V), gate drive is at a maximum for a vaues of. This heps prevent start-up probems into heavy oads by ensuring that there is enough gate drive to support the oad. As ramps up from V, the absoute vaue of the votage remains fixed unti is greater than the ower of ( 1V) or 6V. Once crosses this threshod, gate drive begins to increase up to a maximum of 9.8V (for 12V). The curves of Figure 2 were taken with a oad of 1µA. If there were no oad on, the gate drive for each woud be sighty higher. Note that when is at the ower end of the operating range, the externa N-channe MOSFET must be seected with a corresponding ower threshod votage. V (V) 12 1 8 6 4 2 = 5V = 3.3V = 2.5V = 12V T = 25 C I = 1µA = 3V 3 6 9 12 15 (V) 4365 F2 Figure 2. Gate Drive ( ) vs Tabe 1 ists some externa MOSFETs compatibe with different suppy votages. Tabe 1. Dua MOSFETs for Various Suppy Ranges MOSFET V TH(MAX) V GS(MAX) V DS(MAX) 2.5V SiB914.8V 5V 8V 3.3V Si592 1.V 5V 8V 5V Si794 1.5V 8V 12V 3V Si423 3.V 2V 3V 6V Si9945 3.V 2V 6V Overvotage and Undervotage Protection The provides two accurate comparators to monitor for overvotage () and undervotage () conditions at. If the input suppy rises above the user adjustabe threshod, the gate of the externa MOSFET is quicky turned off, thus disconnecting the oad from the input. Simiary, if the input suppy fas beow the user adjustabe threshod, the gate of the externa MOSFET aso is quicky turned off. Figure 3 shows a / appication for an input suppy of 12V. 12V TH = 3.5V TH = 18V R3 182k R2 243k.5V R1 59k.5V COMPARATOR COMPARATOR 25mV 25mV DISCHARGE WITH 5mA SINK Figure 3., Comparators Monitor 12V Suppy 4365 F3 The externa resistive divider aows the user to seect an input suppy range that is compatibe with the oad at. Furthermore, the and inputs have very ow eakage currents (typicay < 1nA at 1 C), aowing for arge vaues in the externa resistive divider. In the appication of Figure 3, the oad is connected to the suppy ony if ies between 3.5V and 18V. In the event that goes above 18V or beow 3.5V, the gate of the externa N-channe MOSFET is immediatey discharged with a 5mA current sink, thus isoating the oad from the suppy. 9
APPLICATIONS INFORMATION Figure 4 shows the timing associated with the pin. Once a faut propagates through the comparator (t ), the output is asserted ow and a 5mA current sink discharges the pin. As fas, the pin tracks. V t (FAST) t V V HYST t t RECERY EXTERNAL N-CHANNEL MOSFET TURNS OFF 4365 F4 Figure 4. Timing ( < (V V HYST ), > 1.2V) Figure 5 shows the timing associated with the pin. Once an faut propagates through the comparator (t ), the output is asserted ow and a 5mA current sink discharges the pin. As fas, the pin tracks. V t V V HYST t Procedure for Seecting / Externa Resistor Vaues The foowing 3-step procedure heps seect the resistor vaues for the resistive divider of Figure 3. This procedure minimizes and offset errors caused by eakage currents at the respective pins. 1. Choose maximum toerabe offset at the pin, V OS(). Divide by the worst case eakage current at the pin, I (1nA). Set the sum of R1 R2 equa to V OS() divided by 1nA. Note that due to the presence of R3, the actua offset at wi be sighty ower: R1R2 = V OS() I 2. Seect the desired trip threshod, TH. Find the vaue of R3: R3 = 2 V OS() TH.5V I ( ) 3. Seect the desired trip threshod, TH. Find the vaues of R1 and R2: R1= V OS() I R3 2 TH t (FAST) t RECERY EXTERNAL N-CHANNEL MOSFET TURNS OFF 4365 F5 R2 = V OS() I R1 Figure 5. Timing ( > (V V HYST ), > 1.2V) When both the and fauts are removed, the externa MOSFET is not immediatey turned on. The input suppy must remain within the user seected power good window for at east 36ms (t RECERY ) before the oad is again connected to the suppy. This recovery timeout period fiters noise (incuding ine noise) at the input suppy and prevents chattering of power at the oad. The exampe of Figure 3 uses standard 1% resistor vaues. The foowing parameters were seected: V OS() = 3mV I = 1nA TH = 3.5V TH = 18V 1
APPLICATIONS INFORMATION The resistor vaues can then be soved: 1. R1R2 = 3mV 1nA =3k 2. R3= 2 3mV (3.5V.5V) =1.8M 1nA The cosest 1% vaue: R3 = 1.82M: 3. R1= 3k1.82M = 58.9k 2 18V The cosest 1% vaue: R1 = 59k: R2 = 3k 59k = 241k The cosest 1% vaue: R2 = 243k Therefore: = 17.93V, = 3.51V. Reverse Protection The s rugged and hot-swappabe input heps protect the more sensitive circuits at the output oad. If the input suppy is pugged in backwards, or a negative suppy is inadvertenty connected, the prevents this negative votage from passing to the output oad. The empoys a nove, high speed reverse suppy votage monitor. When the negative votage is detected, an interna switch connects the gates of the externa back-to-back N-channe MOSFETs to the negative input suppy. As shown in Figure 6, externa back-to-back N-channe MOSFETs are required for reverse suppy protection. When goes negative, the reverse comparator coses the interna switch, which in turn connects the gates of the externa MOSFETs to the negative votage. The body diode (D1) of M1 turns on, but the body diode (D2) of M2 remains in reverse bocking mode. This means that the common source connection of M1 and M2 remains about a diode drop higher than. Since the gate votage of M2 is shorted to, M2 wi be turned off and no current can fow from to the oad at. Note that the votage rating of M2 must withstand the reverse votage excursion at. Figure 7 iustrates the waveforms that resut when is hot pugged to 2V., and start out at ground just before the connection is made. Due to the parasitic inductance of the and connections, the votage at the and pins ring significanty beow 2V. Therefore, a 4V N-channe MOSFET was seected to survive the overshoot. The speed of the reverse protection circuits is evident by how cosey the pin foows during the negative transients. The two waveforms are amost indistinguishabe on the scae shown. D1 D2 = 4V M1 M2 C OUT TO LOAD 5V/DIV REVERSE COMPARATOR CLOSES SWITCH WHEN IS NEGATIVE 4365 F6 Figure 6. Reverse Protection Circuits 2V 5ns/DIV 4365 F7 Figure 7. Hot Swapping to 2V 11
APPLICATIONS INFORMATION The trace at, on the other hand, does not respond to the negative votage at, demonstrating the desired reverse suppy protection. The waveforms of Figure 7 were captured using a 4V dua N-channe MOSFET, a 1µF ceramic output capacitor and no oad current on. Recovery Timer The has a recovery deay timer that fiters noise at and heps prevent chatter at. After either an or faut has occurred, the input suppy must return to the desired operating votage window for at east 36ms in order to turn the externa MOSFET back on as iustrated in Figures 4 and 5. Going out of and then back into faut in ess than 36ms wi keep the MOSFET off continuousy. Simiary, coming out of shutdown ( ow to high) triggers an 8µs start-up deay timer (see Figure 1). The recovery timer is aso active whie the is powering up. The 36ms timer starts once rises above (LO) and ies within the user seectabe / power good window. See Figure 8. (LO) MOSFET OFF t RECERY MOSFET ON to track, thus keeping the externa MOSFETs off as decays. Note that when < 4.5V, the pin is pued to within 4mV of ground. Gente gate turn off reduces oad current sew rates and mitigates votage spikes due to parasitic inductances. To further decrease pin sew rate, pace a capacitor across the gate and source terminas of the externa MOSFETs. The waveforms of Figure 9 were captured using the Si423 dua N-channe MOSFETs, and a 2A oad with 1µF output capacitor. 5V/DIV Status 1µs/DIV = 12V T = 25 C Figure 9. Gente Shutdown: Tracks as Decays The high votage open drain output is driven ow if is asserted ow, if is outside the desired / votage window, or if has not risen above (LO). Figures 4, 5 and 1 show the output timing. 4365 F9 4365 F8 Figure 8. Recovery Timing During Power-On ( =, = = ) t (SLOW) t START Gente Shutdown ΔV The input turns off the externa MOSFETs in a gente, controed manner. When is asserted ow, a 9µA current sink sowy begins to turn off the externa MOSFETs. Once the votage at the pin fas beow the votage at the pin, the current sink is throtted back and a feedback oop takes over. This oop forces the votage = t (F) Figure 1. Gente Shutdown Timing 4365 F1 12
APPLICATIONS INFORMATION Seect Between Two Input Suppies With the part in shutdown, the and pins can be driven by separate power suppies. The then automaticay drives the pin just beow the ower of the two suppies, thus turning off the externa back-to-back MOSFETs. The appication of Figure 11 uses two s to seect between two power suppies. Care shoud be taken to ensure that ony one of the two s is enabed at any given time. V1 V2 M1 M1 SEL 1 OUT V1 V2 M2 M2 OUT Limiting Inrush Current During Turn-On The turns on the externa N-channe MOSFET with a 2µA current source. The maximum sew rate at the pin can be reduced by adding a capacitor on the pin: Sew Rate = 2µA C Since the MOSFET acts ike a source foower, the sew rate at equas the sew rate at. Therefore, inrush current is given by: I INRUSH = C OUT C 2µA For exampe, a 1A inrush current to a 33µF output capacitance requires a capacitance of: C = 2µA C OUT I INRUSH SEL 4365 F11 Figure 11. Seecting One of Two Suppies Singe MOSFET Appication When reverse protection is not needed, ony a singe externa N-channe MOSFET is necessary. The appication circuit of Figure 12 connects the oad to when is ess than 3V, and uses the minima set of externa components. 24V R2 237k R1 4.2k SI712DN 6V 4365 F12 = 3V C OUT 1µF Figure 12. Sma Footprint Singe MOSFET Appication Protects Against 6V 2µA 33µF C = = 6.6nF 1A The 6.8nF C capacitor in the appication circuit of Figure 13 imits the inrush current to approximatey 1A. R makes sure that C does not affect the fast turn off characteristics during / fauts, or during reverse connection. R4A and R4B hep prevent high frequency osciations with the externa N-channe MOSFET and reated board parasitics. M1 R4A 1Ω R4B 1Ω M2 4365 F13 C OUT 33µF R 5.1k C 6.8nF Figure 13. Limiting Inrush Current with C 13
APPLICATIONS INFORMATION Transients During Faut The circuit of Figure 14 was used to dispay transients during an overvotage condition. The nomina input suppy is 24V and it has an overvotage threshod of 3V. The parasitic inductance is that of a 1 foot wire (roughy 3nH). Figure 15 shows the waveforms during an overvotage condition at. These transients depend on the parasitic inductance and resistance of the wire aong with the capacitance at the node. D1 is an optiona power camp (TVS, Tranzorb) recommended for appications where the DC input votage can exceed 24V and with arge parasitic inductance. No camp was used to capture the waveforms of Figure 15. In order to maintain reverse suppy protection, D1 must be a bi-directiona camp rated for at east 225W peak puse power dissipation. 24V 12 INCH WIRE LENGTH C IN 1µF D1 OPTIONAL R2 237k R1 4.2k R3 1k M1 SI9945 6V M2 4365 F14 = 3V Figure 14. Faut with Large Inductance 2V/DIV 2V/DIV C OUT 1µF 9Ω MOSFET Seection To protect against a negative votage at, the externa N-channe MOSFETs must be configured in a back-toback arrangement. Dua N-channe packages are thus the best choice. The MOSFET is seected based on its power handing capabiity, drain and gate breakdown votages, and threshod votage. The drain to source breakdown votage must be higher than the maximum votage expected between and. Note that if an appication generates high energy transients during norma operation or during Hot Swap, the externa MOSFET must be abe to withstand this transient votage. Due to the high impedance nature of the charge pump that drives the pin, the tota eakage on the pin must be kept ow. The gate drive curves of Figure 2 were measured with a 1µA oad on the pin. Therefore, the eakage on the pin must be no greater than 1µA in order to match the curves of Figure 2. Higher eakage currents wi resut in ower gate drive. The dua N-channe MOSFETs shown in Tabe 1 a have a maximum eakage current of 1nA. Additionay, Tabe 1 ists representative MOSFETs that woud work at different vaues of. Layout Considerations The trace ength between the pin and the drain of the externa MOSFET shoud be minimized, as we as the trace ength between the pin of the and the gates of the externa MOSFETs. Pace the bypass capacitors at as cose as possibe to the externa MOSFET. Use high frequency ceramic capacitors in addition to buk capacitors to mitigate Hot Swap ringing. Pace the high frequency capacitors cosest to the MOSFET. Note that buk capacitors mitigate ringing by virtue of their ESR. Ceramic capacitors have ow ESR and can thus ring near their resonant frequency. I IN 2A/DIV A 25ns/DIV 4365 F15 Figure 15. Transients During Faut When No Tranzorb (TVS) Is Used 14
PACKAGE DESCRIPTION TS8 Package 8-Lead Pastic TSOT-23 (Reference LTC DWG # 5-8-1637).52 MAX.65 REF 2.9 BSC (NOTE 4) 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.8 BSC 1.5 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR.65 BSC.22.36 8 PLCS (NOTE 3).8.9.2 BSC DATUM A 1. MAX.1.1.3.5 REF.9.2 1.95 BSC (NOTE 3) TS8 TSOT-23 82 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 DDB Package 8-Lead Pastic DFN (3mm 2mm) (Reference LTC DWG # 5-8-172 Rev B) 2.55 ±.5 1.15 ±.5.61 ±.5 (2 SIDES).25 ±.5.5 BSC 2.2 ±.5 (2 SIDES).7 ±.5 PACKAGE OUTLINE RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 BAR TOP MARK (SEE NOTE 6).2 REF 3. ±.1 (2 SIDES) 2. ±.1 (2 SIDES).75 ±.5.5 R =.5 TYP.56 ±.5 (2 SIDES) R =.115 TYP 5.4 ±.1 4 1.25 ±.5.5 BSC 2.15 ±.5 (2 SIDES) BOTTOM VIEW EXPOSED PAD 8 PIN 1 R =.2 OR.25 45 CHAMFER (DDB8) DFN 95 REV B NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 15
TYPICAL APPLICATION Protects Step Down Reguator from 3V to 3V Fauts CMDSH-3 12V NOMINAL PROTECTED FROM 3V TO 3V 51k SI423 3V DUAL N-CHANNEL 3.5V TO 18V INPUT RANGE 4.7µF CERAMIC BOOST LT1765-3.3 SYNC V SW FB V C 2.2nF.18µF 1.5µH UPS12 OUTPUT 3.3V 2.5A 4.7µF CERAMIC 182k 243k 59k = 18V = 3.5V 4365 TA2 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC4356 Surge Stopper Overvotage/Overcurrent Protection Reguator Wide Operating Range: 4V to 8V, Reverse Protection to 6V, Adjustabe Output Camp Votage LTC1696 Overvotage Protection Controer ThinSOT Package, 2.7V to 28V LTC1735 High Efficiency Synchronous Step-Down Switching Reguator Output Faut Protection, 16-Pin SSOP LTC1778 No R SENSE Wide Input Range Synchronous Step-Down Controer Up to 97% Efficiency, 4V 36V,.8V (.9)( ), I OUT Up to 2A LTC299 Tripe/Dua Inputs / Negative Monitor Pin Seectabe Input Poarity Aows Negative and Monitoring LTC2912/LTC2913 Singe/Dua / Votage Monitor Ads and Trip Vaues, ±1.5% Threshod Accuracy LTC2914 Quad / Monitor For Positive and Negative Suppies LTC3727/LTC3727-1 2-Phase, Dua, Synchronous Controer 4V 36V,.8V 14V LTC3827/LTC3827-1 Low I Q, Dua, Synchronous Controer 4V 36V,.8V 1V, 8µA Quiescent Current LTC3835/LTC3835-1 Low I Q, Synchronous Step-Down Controer Singe Channe LTC3827/LTC3827-1 LT3845 Low I Q, Synchronous Step-Down Controer 4V 6V, 1.23V 36V, 12µA Quiescent Current LT385 Dua, 55kHz, 2-Phase Synchronous Step-Down Controer Dua 18 Phased Controers, 4V to 24V, 97% Duty Cyce, 4mm 4mm QFN-28, SSOP-28 Packages LT4256 LTC426 Positive 48V Hot Swap Controer with Open-Circuit Detect Positive High Votage Hot Swap Controer with ADC and I 2 C Fodback Current Limiting, Open-Circuit and Overcurrent Faut Output, Up to 8V Suppy Wide Operating Range 8.5V to 8V LTC4352 Idea MOSFET ORing Diode Externa N-Channe MOSFETs Repace ORing Diodes, V to 18V LTC4354 Negative Votage Diode-OR Controer Contros Two N-Channe MOSFETs, 1µs Turn-Off, 8V Operation LTC4355 Positive Votage Diode-OR Controer Contros Two N-Channe MOSFETs,.5µs Turn-Off, 8V Operation 16 LT 91 PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA 9535-7417 (48) 432-19 FAX: (48) 434-57 www.inear.com LINEAR TECHNOLOGY CORPORATION 21