Features OBSOLETE. Output Third Order Intercept (IP3) [2] dbm Total Supply Current ma

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v.1111 Typical Applications Features The is ideal for: Point-to-Point Radios Point-to-Multi-Point Radios VSAT & SATCOM Military & Space Functional Diagram P1dB Output Power: + dbm Psat Output Power: + dbm High Gain: db Output IP3: +34 dbm Supply Voltage: Vdd = +6V @ 25 ma 5 Ohm Matched Input/Output Die Size:.9 x 2. x.1 mm General Description The is a four stage GaAs phemt MMIC Medium Power Amplifier die which operates between 34 and 46.5 GHz. The amplifier provides db of gain, + dbm of saturated output power, and 17% PAE from a +6V supply. With up to +37 dbm IP3 the is ideal for high linearity applications in miltary and space as well as point-to-point and point-to-multi-point radios. The amplifier I/Os are internally matched facilitating integration into mutli-chip-modules (MCMs). All data shown herein was measured with the chip connected via two.25mm (1 mil) wire bonds of minimal length.31 mm (12 mils). Electrical Specifications, T A = +25 C, Vdd = Vdd1 = Vdd2 = +6V, Idd = 25 ma [1] Parameter Min. Typ. Max. Min. Typ. Max. Units Frequency Range 34-4 4-46.5 GHz Gain 19 23 db Gain Variation Over Temperature..38 db/ C Input Return Loss 13 db Output Return Loss 11 12 db Output Power for 1 db Compression (P1dB) 21 21 dbm Saturated Output Power (Psat) dbm Output Third Order Intercept (IP3) [2] 34 34 dbm Total Supply Current 25 25 ma [1] Adjust Vgg between -2 to V to achieve Idd = 25 ma typical. [2] Measurement taken at Pout / tone = + dbm. 1 One Technology Way, P.O. Box 9, Norwood, MA 62-9

v_1111 Gain & Return Loss Gain vs. Temperature RESPONSE (db) 1 S21 S11 S -1 - - 49 Input Return Loss vs. Temperature Output Return Loss vs. Temperature RETURN LOSS (db) -5-1 -15 - -25-49 P1dB vs. Temperature P1dB (dbm) GAIN (db) RETURN LOSS (db) 1 49-5 -1-15 - -25 49 P1dB vs Supply Voltage P1dB (dbm) 5V 5.5V 6V One Technology Way, P.O. Box 9, Norwood, MA 62-9 2

v_1111 Psat vs. Temperature Psat vs. Supply Voltage Psat (dbm) P1dB vs. Supply Current P1dB (dbm) Output IP3 vs. Temperature, Pout/tone = + dbm IP3 (dbm) ma 5 ma 25 ma 4 35 Psat (dbm) Psat vs. Supply Current Psat (dbm) ma 5 ma 25 ma 5.V 5.5V 6.V Output IP3 vs. Supply Current, Pout/tone = + dbm IP3 (dbm) 4 35 25 25 ma 5 ma 25 ma 34 35 36 37 38 39 4 41 42 43 44 45 46 47 34 35 36 37 38 39 4 41 42 43 44 45 46 47 3 One Technology Way, P.O. Box 9, Norwood, MA 62-9

v_1111 Output IP3 vs. Supply Voltage, Pout/tone = + dbm 4 Output IM3 @ Vdd = +5V 6 IP3 (dbm) 35 5V 5.5V 6V 25 34 35 36 37 38 39 4 41 42 43 44 45 46 47 Output IM3 @ Vdd =+5.5V Output IM3 @ Vdd = +6V IM3 (dbc) 6 6 5 5 4 4 Power Compression @ 4 GHz Pout (dbm), GAIN (db), PAE (%) 34 GHz 36 GHz 38 GHz 4 GHz 42 GHz 1 45 GHz 6 8 1 12 35 25 15 1 5 Pout Gain PAE Pout/TONE (dbm) IM3 (dbc) IM3 (dbc) 5 4 34 GHz 36 GHz 38 GHz 4 GHz 42 GHz 1 45 GHz 6 8 1 12 1 Pout/TONE (dbm) 34 GHz 36 GHz 38 GHz 4 GHz 42 GHz 45 GHz 6 8 1 12 Pout/TONE (dbm) Reverse Isolation vs. Temperature ISOLATION (db) -1 - - -4-5 -1-7 -4-1 2 5 8 INPUT POWER (dbm) -6 49 One Technology Way, P.O. Box 9, Norwood, MA 62-9 4

v_1111 Gain & Power vs. Supply Current @ 4 GHz Gain & Power vs. Supply Voltage @ 4 GHz Gain (db), P1dB (dbm), Psat (dbm) 27 21 15 21 2 2 25 Idd (ma) Absolute Maximum Ratings Drain Bias Voltage (Vdd) Gate Bias Voltage (Vgg) RF Input Power (rfin) +7 Vdc -3 to Vdc +15 dbm Channel Temperature 15 C Continuous Pdiss (T= 85 C) (derate mw/ C above 85 C) GAIN (db) P1dB (dbm) Psat (dbm) 1.57 W Power Dissipation POWER DISSIPATION (W) 3 2.5 2 1.5 1.5 34 GHz 36 GHz 38 GHz 4 GHz 42 GHz 45 GHz Gain (db), P1dB (dbm), Psat (dbm) -1-8 -6-4 -2 2 4 6 8 27 21 15 INPUT POWER (dbm) 5 5.2 5.4 5.6 5.8 6 Vdd (V) Typical Supply Current vs. Vdd Vdd (V) GAIN (db) P1dB (dbm) Psat (dbm) Idd (ma) +5 25 +5.5 25 +6 25 Adjust Vgg1 to achieve Idd = 25 ma Thermal Resistance (channel to die bottom) 41.3 C/W Storage Temperature -65 to 15 C Operating Temperature -55 to 85 C ELECTROSTATIC sensitive DEVICE OBSERVE HANDLING PRECAUTIONS 5 One Technology Way, P.O. Box 9, Norwood, MA 62-9

v_1111 Outline Drawing Die Packaging Information [1] Standard Alternate GP-1 (Gel Pack) [2] [1] For more information refer to the Packaging Information Document in the Product Support Section of our website. [2] For alternate packaging information contact Hittite Microwave Corporation. NOTES: 1. ALL Dimensions ARE IN INCHES [MM] 2. DIE THICKness IS.4 3. TYPICAL BOND PAD IS.4 SQUARE 4. BOND PAD METALIZATION: GOLD 5. BACKSIDE METALIZATION: GOLD 6. BACKSIDE METAL IS GROUND 7. NO ConneCTION REQUIRED for UNLABELED BOND PADS 8. OVERALL DIE SIZE ±.2 One Technology Way, P.O. Box 9, Norwood, MA 62-9 6

v_1111 Pad Descriptions Pad Number Function Description Interface Schematic 1 RFIN 2 Vgg 3 RFOUT 4, 5 Vdd1, Vdd2 This pad is DC coupled and matched to 5 Ohms. Gate control for PA. Adjust Vgg to achieve recommendedbias current. External bypass capacitors 1 pf, 1 nf, and 4.7 μf are required. This pad is AC coupled and matched to 5 Ohms. Drain bias voltage. External bypass capacitors of 1pF, 1 nf, and 4.7uF are required for each pad. Die Bottom GND Die bottom must be connected to RF/DC ground. 7 One Technology Way, P.O. Box 9, Norwood, MA 62-9

v_1111 Assembly Diagram Application Circuit One Technology Way, P.O. Box 9, Norwood, MA 62-9 8

v_1111 Mounting & Bonding Techniques for Millimeterwave GaAs MMICs The die should be attached directly to the ground plane eutectically or with conductive epoxy (see HMC general Handling, Mounting, Bonding Note). 5 Ohm Microstrip transmission lines on.127mm (5 mil) thick alumina thin film substrates are recommended for bringing RF to and from the chip (Figure 1). If.254mm (1 mil) thick alumina thin film substrates must be used, the die should be raised.15mm (6 mils) so that the surface of the die is coplanar with the surface of the substrate. One way to accomplish this is to attach the.12mm (4 mil) thick die to a.15mm (6 mil) thick molybdenum heat spreader (moly-tab) which is then attached to the ground plane (Figure 2). Microstrip substrates should be located as close to the die as possible in order to minimize bond wire length. Typical die-to-substrate spacing is.76mm to.152 mm (3 to 6 mils). Handling Precautions Follow these precautions to avoid permanent damage. Storage: All bare die are placed in either Waffle or Gel based ESD protective containers, and then sealed in an ESD protective bag for shipment. Once the sealed ESD protective bag has been opened, all die should be stored in a dry nitrogen environment. Cleanliness: Handle the chips in a clean environment. DO NOT attempt to clean the chip using liquid cleaning systems. Static Sensitivity: Follow ESD precautions to protect against > ± 25V ESD strikes. Transients: Suppress instrument and bias supply transients while bias is applied. Use shielded signal and bias cables to minimize inductive pickup. General Handling: Handle the chip along the edges with a vacuum collet or with a sharp pair of bent tweezers. The surface of the chip may have fragile air bridges and should not be touched with vacuum collet, tweezers, or fingers. Mounting The chip is back-metallized and can be die mounted with AuSn eutectic preforms or with electrically conductive epoxy. The mounting surface should be clean and flat. Eutectic Die Attach: A 8/ gold tin preform is recommended with a work surface temperature of 255 C and a tool temperature of 5 C. When hot 9/1 nitrogen/hydrogen gas is applied, tool tip temperature should be 29 C. DO NOT expose the chip to a temperature greater than 3 C for more than seconds. No more than 3 seconds of scrubbing should be required for attachment. Epoxy Die Attach: Apply a minimum amount of epoxy to the mounting surface so that a thin epoxy fillet is observed around the perimeter of the chip once it is placed into position. Cure epoxy per the manufacturer s schedule. Wire Bonding Ball or wedge bond with.25mm (1 mil) diameter pure gold wire. Thermosonic wirebonding with a nominal stage temperature of 15 C and a ball bonding force of 4 to 5 grams or wedge bonding force of to grams is recommended. Use the minimum level of ultrasonic energy to achieve reliable wirebonds. Wirebonds should be started on the chip and terminated on the package or substrate. All bonds should be as short as possible <.31mm (12 mils). 9 One Technology Way, P.O. Box 9, Norwood, MA 62-9

v_1111 Notes: One Technology Way, P.O. Box 9, Norwood, MA 62-9 1