Prduct Descriptin Sirenza Micrdevices SDM- W pwer mdule is a rbust impedance matched, single-stage, push-pull Class AB amplifier mdule suitable fr use as a pwer amplifier driver r utput stage. The pwer transistrs are fabricated using Sirenza's latest, high perfrmance LDMOS prcess. It is a drp-in, n-tune slutin fr high pwer applicatins requiring high efficiency, excellent linearity, and unit-tunit repeatability. It is internally matched t hms. SDM- SDM-Y Pb - MHz Class AB W Pwer Amplifier Mdule RHS Cmpliant & Green Package Functinal Blck Diagram Vgs +V DC t + V DC +V DC Vds RF in Vgs +V DC t + V DC +V DC Vds Prduct Features Available in RHS cmpliant packaging W RF impedance W Output P db Single Supply Operatin : Nminally V High : db at MHz High : % at MHz Applicatins Case Flange = Grund Base Statin PA driver Repeater CDMA GSM / EDGE Key Specificatins Symbl Parameter Units Min. Typ. Max. RF ut Frequency Frequency f Operatin MHz - P db Output Pwer at db Cmpressin, MHz W - W PEP Output Pwer, MHz and MHz db - Flatness Peak-t-Peak Variatin, W PEP, - MHz db -.. Input Return Lss, W PEP Output Pwer, - MHz db - - - IMD rd Order Prduct. W PEP Output, MHz and MHz dbc - - - IMD Variatin W PEP Output, Change in Spacing KHz - MHz db -. - Drain, W PEP Output, MHz and MHz % - Drain, W CW Output, MHz % - - Delay Signal Delay frm Pin t Pin ns -. - Phase Linearity Deviatin frm Linear Phase (Peak-t-Peak) Deg -. - R TH Thermal Resistance (Junctin-t-Case) ºC/W. Test Cnditins Z in = Z ut = Ω, V DD =.V, I DQ = I DQ =ma TT Flange = ºC Quality Specificatins Parameter Descriptin Unit Typical ESD Rating Human Bdy Mdel Vlts MTTF C Channel Hurs. X The infrmatin prvided herein is believed t be reliable at press time. Sirenza Micrdevices assumes n respnsibility fr inaccuracies r mmisins. Sirenza Micrdevices assumes n respnsibility fr the use f this infrmatin, and all such infrmatin shall be entirely at the user s wn risk. Prices and specificatins are subject t change withut ntice. N patent rights r licenses t any f the circuits described herein are implied r granted t any third party. Sirenza Micrdevices des nt authrize r warrant any Sirenza Micrdevices prduct fr use in life-supprt devices and/r systems. Cpyright Sirenza Micrdevices, Inc. All wrldwide rights reserved. S. Technlgy Curt, Phne: () SMI-MMIC http://www.sirenza.cm Brmfield, CO EDS- Rev G
SDM- - MHz W Pwer Amp Mdule Pin Descriptin Pin # Functin Descriptin V GS LDMOS FET Q and Q gate bias. V GSTH. t. VDC. See Ntes, and,,, Grund Mdule Tpside grund. RF Input Internally DC blcked V GS LDMOS FET Q and Q gate bias. V GSTH. t. VDC. See Ntes, and V D LDMOS FET Q and Q drain bias. See Nte. RF Output Internally DC blcked V D LDMOS FET Q and Q drain bias. See Nte. Flange Grund Baseplate prvides electrical grund and a thermal transfer path fr the device. Prper munting assures ptimal perfrmance and the highest reliability. See Sirenza applicatins nte AN- Detailed Installatin Instructins fr Pwer Mdules. Simplified Device Schematic +V DC t + V DC Q Q +V DC Nte : Internal RF decupling is included n all bias leads. N additinal bypass elements are required, hwever sme applicatins may require energy strage n the V D leads t accmmdate mdulated signals. Q Nte : Gate vltage must be applied t V GS leads simultaneusly with r after applicatin f drain vltage t prevent ptentially destructive scillatins. Bias vltages shuld never be applied t a mdule unless it is prperly terminated n bth input and utput. +V DC t + V DC Abslute Maximum Ratings Parameters Value Unit Drain Vltage (V DD ) V RF Input Pwer + dbm Lad Impedance fr Cntinuus Operatin Withut Damage : VSWR Cntrl (Gate) Vltage, VDD = VDC V Output Device Channel Temperature + ºC Operating Temperature Range Strage Temperature Range Q +V DC - t + - t + Operatin f this device beynd any ne f these limits may cause permanent damage. Fr reliable cntinuus peratin see typical setup values specified in the table n page ne. ºC ºC Nte : The required V GS crrespnding t a specific I DQ will vary frm mdule t mdule and may differ between V GS and V GS n the same mdule by as much as ±. vlts due t the nrmal die-t-die variatin in threshld vltage fr LDMOS transistrs. Nte : The threshld vltage (V GSTH ) f LDMOS transistrs varies with device temperature. External temperature cmpensatin may be required. See Sirenza applicatin ntes AN- LDMOS Bias Temperature Cmpensatin. Nte : This mdule was designed t have it's leads hand sldered t an adjacent PCB. The maximum sldering irn tip temperature shuld nt exceed F, and the sldering irn tip shuld nt be in direct cntact with the lead fr lnger than secnds. Refer t app nte AN (www.sirenza.cm) fr further installatin instructins. Cautin: ESD Sensitive Apprpriate precautin in handling, packaging and testing devices must be bserved. S. Technlgy Curt Phne: () SMI-MMIC http://www.sirenza.cm Brmfield, CO EDS- Rev G
SDM- - MHz W Pwer Amp Mdule Typical Perfrmance Curves (db), (%) Tne,, Linearity and vs Frequency Vdd=V, Idq=.A, Put=W PEP, Delta F= MHz IM IM IM - Frequency (MHz) - - - - - - - - IMD(dBc), (db) (db), (%) Tne,, Linearity vs Put Vdd=V, Idq=.A, Freq= MHz, Delta F= MHz - IM IM - IM - Put (W PEP) - - - - - - IMD (dbc) CW,, vs Frequency Vdd=V, Idq=.A, Put=W CW, vs Put Vdd=V, Idq=.A, Freq= MHz - (db), (%) - - - Input Return Lss (db) (db) (%) - Frequency (MHz) Put (W) S. Technlgy Curt Phne: () SMI-MMIC http://www.sirenza.cm Brmfield, CO EDS- Rev G
SDM- - MHz W Pwer Amp Mdule Typical Perfrmance Curves (cnt d) CW,, vs Supply Vltage Put=W, Idq=.A, Freq= MHz - Tw Tne,,, IMD vs Supply Vltage Put=W PEP, Idq=.A, Freq= MHz, Delta F= MHz (db), (%) - - - - Input Return Lss (db) (db), (%) IM IM IM - - - - - - - - - Input Return Lss (db), IMD (dbc). - Vds (Vlts) - - Vds (Vlts). CW vs Put fr varius Idq Vds=V, Freq= MHz IM vs Put fr varius Idq Vds=V, Freq= MHz, Delta F= MHz Idq=.A Idq=.A - Idq=.A Idq=.A Idq=.A (db). Idq=.A Idq=.A (db) - - Idq=.A Idq=.A. Idq=.A - Put (W) - Put (W PEP) Nte: Evaluatin test fixture infrmatin available n Sirenza Website, referred t as SDM-EVAL S. Technlgy Curt Phne: () SMI-MMIC http://www.sirenza.cm Brmfield, CO EDS- Rev G
SDM- - MHz W Pwer Amp Mdule Package Outline Drawing... [. ] (X). [.]. [.].. [ (X).. ] (X). [.] LABEL LOCATION. [.]. [.].... [. ] [.]. [.]. (X) [.]. [.] LOT NUMBER LOGO MODULE NUMBER BAR CODE. [.]. [.] (X). [.]. [.]. [.]. [.] LEAD IDENTIFICATION Lead N. Grund Input Grund VGS VD Grund Output Grund V Grund D BASE PLATE Functin V GS.. [. [.]. [.].. ]. [.]. [.] (X). [.]. [.]. [.] MAX. INTERPRET DRAWING PER ANSI Y... MEASURE FROM THE BOTTOM OF THE LEADS.. DIMENSIONS ARE INCHES[MM].. LEAD IDENTIFICATION IS FOR REFERENCE ONLY.. ORIENTATION OF LABEL IS TO BE AS SHOWN. MODULE WEIGHT = gm NOMINAL Nte: Refer t Applicatin nte AN, Detailed Installatin Instructins fr Pwer Mdules fr detailed munting infrmatin. S. Technlgy Curt Phne: () SMI-MMIC http://www.sirenza.cm Brmfield, CO EDS- Rev G