Features. Description. Table 1: Device summary. Order code Marking Package Packing STW75N60M6 75N60M6 TO-247 Tube

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Transcription:

N-channel 600 V, 32 mω typ., 72 A MDmesh M6 Power MOSFET in TO-247 package Datasheet - production data Features Order code VDS RDS(on) max. ID STW75N60M6 600 V 36 mω 72 A 3 2 1 TO-247 Figure 1: Internal schematic diagram Reduced switching losses Lower RDS(on) per area vs previous generation Low gate input resistance 100% avalanche tested Zener-protected Applications Switching applications LLC converters Boost PFC converters Table 1: Device summary Description The new MDmesh M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent RDS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. Order code Marking Package Packing STW75N60M6 75N60M6 TO-247 Tube December 2017 DocID031350 Rev 1 1/12 This is information on a product in full production. www.st.com

Contents STW75N60M6 Contents 1 Electrical ratings... 3 2 Electrical characteristics... 4 2.1 Electrical characteristics (curves)... 6 3 Test circuits... 8 4 Package information... 9 4.1 TO-247 package information... 9 5 Revision history... 11 2/12 DocID031350 Rev 1

Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ±25 V Drain current (continuous) at TC = 25 C 72 A ID Drain current (continuous) at TC = 100 C 45 A IDM (1) Drain current (pulsed) 288 A PTOT Total dissipation at TC = 25 C 446 W dv/dt (2) Peak diode recovery voltage slope 15 dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns Tstg Tj Storage temperature range -55 to 150 C Operating junction temperature range Notes: (1) Pulse width is limited by safe operating area. (2) ISD 72 A, di/dt = 400 A/µs, VDS(peak) < V(BR)DSS, VDD = 400 V (3) VDS 480 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 0.28 C/W Rthj-amb Thermal resistance junction-ambient 50 C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR EAS Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) Single pulse avalanche energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) 11 A 1.4 J DocID031350 Rev 1 3/12

Electrical characteristics STW75N60M6 2 Electrical characteristics (TC = 25 C unless otherwise specified) Table 5: On /off-states Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS IDSS Drain-source breakdown voltage Zero-gate voltage drain current VGS = 0 V, ID = 1 ma 600 V VGS = 0 V, VDS= 600 V 1 VGS = 0 V, VDS = 600 V, TC = 125 C (1) IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±5 µa VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µa 3.25 4 4.75 V RDS(on) Notes: Static drain-source on-resistance (1) Defined by design, not subject to production test. 100 VGS = 10 V, ID = 36 A 32 36 mω µa Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance - 4850 - pf Coss Output capacitance VGS = 0 V, VDS = 100 V, - 380 - pf f = 1 MHz Reverse transfer Crss - 3.5 - pf capacitance Coss eq. (1) Equivalent output capacitance VGS = 0 V, VDS = 0 to 480 V - 851 - pf RG Intrinsic gate resistance f = 1 MHz open drain - 1.5 - Ω Qg Total gate charge VDD = 480 V, ID = 72 A, - 106 - nc Qgs Gate-source charge VGS = 0 to 10 V - 22 - nc Qgd Gate-drain charge (see Figure 15: "Test circuit for gate charge behavior") - 55 - nc Notes: (1) Coss eq. is defined as the constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 4/12 DocID031350 Rev 1

Electrical characteristics Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 300 V, ID = 36 A, - 35 - ns tr Rise time RG = 4.7 Ω, VGS = 10 V - 38 - ns td(off) Turn-off delay time (see Figure 14: "Test circuit for resistive load switching times" - 90 - ns tf Fall time and Figure 19: "Switching time waveform") - 12 - ns Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 72 A ISDM (1) Source-drain current (pulsed) - 288 A VSD (2) Forward on voltage VGS = 0 V, ISD = 72 A - 1.6 V trr Reverse recovery time ISD = 72 A, di/dt = 100 A/µs, - 367 ns Qrr Reverse recovery charge VDD = 60 V - 6.4 µc IRRM Reverse recovery current (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 35 A trr Reverse recovery time ISD = 72 A, di/dt = 100 A/µs, - 552 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 C - 13.7 µc IRRM Reverse recovery current (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 49.6 A Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID031350 Rev 1 5/12

Electrical characteristics STW75N60M6 2.1 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance d d t Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/12 DocID031350 Rev 1

Figure 8: Normalized on-resistance vs temperature Electrical characteristics Figure 9: Normalized V(BR)DSS vs temperature Figure 10: Capacitance variations Figure 11: Normalized gate threshold voltage vs temperature Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics DocID031350 Rev 1 7/12

Test circuits STW75N60M6 3 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform 8/12 DocID031350 Rev 1

Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 TO-247 package information Figure 20: TO-247 package outline DocID031350 Rev 1 9/12

Package information STW75N60M6 Table 9: TO-247 package mechanical data mm Dim. Min. Typ. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 5.45 5.60 L 14.20 14.80 L1 3.70 4.30 L2 18.50 ØP 3.55 3.65 ØR 4.50 5.50 S 5.30 5.50 5.70 10/12 DocID031350 Rev 1

Revision history 5 Revision history Table 10: Document revision history Date Revision Changes 11-Dec-2017 1 Initial version DocID031350 Rev 1 11/12

IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 2017 STMicroelectronics All rights reserved 12/12 DocID031350 Rev 1