TLC7701-Q1, TLC7705-Q1, TLC7733-Q1 MICROPOWER SUPPLY VOLTAGE SUPERVISORS

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Qualified for Automotive Applications Power-On Reset Generator Automatic Reset Generation After Voltage Drop Precision Voltage Sensor Temperature-Compensated Voltage Reference Programmable Delay Time by External Capacitor Supply Voltage Range...2 V to 6 V Defined Output from V DD V Power-Down Control Support for Static RAM With Battery Backup Maximum Supply Current of 6 μa Power Saving Totem-Pole Outputs TLC770-Q, TLC770-Q, TLC77-Q SGLS208A OCTOBER 200 REVISED MAY 2008 CONTROL RESIN CT GND PW PACKAGE (TOP VIEW) 2 8 7 6 V DD SENSE description The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputer and microprocessor systems. During power-on, is asserted when V DD reaches V. After minimum V DD ( 2 V) is established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (V I(SENSE) ) remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time, t d, is determined by an external capacitor: t d = 2. 0 C T Where C T is in farads t d is in seconds Except for the TLC770, which can be customized with two external resistors, each supervisor has a fixed SENSE threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time, t d, has expired. In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By driving the chip select (CS) of the memory circuit with the output of the TLC77xx and with the CONTROL driven by the memory bank select signal (CSH) of the microprocessor (see Figure 0), the memory circuit is automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the battery.) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2008, Texas Instruments Incorporated POST OFFICE BOX 60 DALLAS, TEXAS 726

TLC770-Q, TLC770-Q, TLC77-Q SGLS208A OCTOBER 200 REVISED MAY 2008 ORDERING INFORMATION T A PACKAGE ORDERABLE PART NUMBER TSSOP PW Tape and reel TLC770QPWRQ 770Q 0 C to 2 C TSSOP PW Tape and reel TLC770QPWRQ 770Q TSSOP PW Tape and reel TLC77QPWRQ 77Q TOP-SIDE MARKING For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. The PW package is only available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TLC770QPWREP). FUNCTION TABLE CONTROL RESIN V I(SENSE) >V IT+ L L False H L L L True H L L H False H L L H True L H H L False H L H L True H L H H False H L H H True H H and states shown are valid for t > t d. logic symbol SENSE 7 RESIN 2 CT CONTROL COMP S S<V IT V IT CX 2 Z Z2 Z 6 This symbol is in accordance with ANSI/IEEE Std 9 98 and IEC Publication 67-2. 2 POST OFFICE BOX 60 DALLAS, TEXAS 726

TLC770-Q, TLC770-Q, TLC77-Q SGLS208A OCTOBER 200 REVISED MAY 2008 functional block diagram CONTROL 0 μa 8 6 V DD RESIN 2 SENSE 7 R R2 MΩ. V Outputs are totem-pole configuration. External pullup or pulldown resistors are not required. Nominal values: TLC770 R (Typ) R2 (Typ) 0 TLC770 90 kω 290 kω TLC77 70 kω 0 kω CT GND POST OFFICE BOX 60 DALLAS, TEXAS 726

TLC770-Q, TLC770-Q, TLC77-Q SGLS208A OCTOBER 200 REVISED MAY 2008 timing diagram Threshold Voltages V DD and V I(SENSE) V IT+ V IT V IT+ V res t Output t d t d Output Undefined t absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, V DD (see Note )............................................................. 7 V Input voltage range, CONTROL, RESIN, SENSE (see Note )........................... 0. V to 7 V Maximum low output current, I OL........................................................... 0 ma Maximum high output current, I OH......................................................... 0 ma Input clamp current, I IK (V I < 0 or V I > V DD )............................................... ±0 ma Output clamp current, I OK (V O < 0 or V O > V DD )............................................ ±0 ma Continuous total power dissipation.................................... See Dissipation Rating Table Operating free-air temperature range, T A : TL77xxQ.................................. 0 C to 2 C Storage temperature range, T stg.................................................. 6 C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : All voltage values are with respect to GND. PACKAGE T A 2 C POWER RATING DISSIPATION RATING TABLE DERATING FACTOR ABOVE T A = 2 C T A = 8 C POWER RATING T A = 2 C POWER RATING PW 2 mw.2 mw/ C 27 mw 0 mw recommended operating conditions at specified temperature range MIN MAX UNIT Supply voltage, V DD 2 6 V Input voltage, V I 0 V DD V High-level input voltage at RESIN and CONTROL, V IH 0.7 V DD V Low-level input voltage at RESIN and CONTROL, V IL 0.2 V DD V High-level output current, I OH V DD 2.7 27V Low-level output current, I OL 2 ma 2 ma Input transition rise and fall rate at RESIN and CONTROL, Δt/ΔV 00 ns/v Operating free-air temperature range, T A 0 2 C To ensure a low supply current, V IL should be kept < 0. V and V IH > V DD 0. V. POST OFFICE BOX 60 DALLAS, TEXAS 726

TLC770-Q, TLC770-Q, TLC77-Q SGLS208A OCTOBER 200 REVISED MAY 2008 electrical characteristics over recommended operating conditions (see Note 2) (unless otherwise noted) V OH V OL PARAMETER High-level output voltage Low-level output voltage TEST CONDITIONS V DD = 2 V.8 I OH = 20 μa V DD = 2.7 V 2. V DD =. V. I OH = 2 ma V DD =. V.7 TLC77xx MIN TYP MAX V DD = 2 V 0.2 I OL = 20 μa V DD = 2.7 V 0.2 V DD =. V 0.2 I OL = 2 ma V DD =. V 0. TLC770.0..6 V IT Negative-going i input threshold h voltage, TLC770 V DD = 2 V to 6 V...6 V TLC77 2.8 2.9.0 V hys Hysteresis voltage, SENSE TLC770 V DD = 2 V to 6 V TLC77 TLC770 0 V res Power-up reset voltage I OL = 20 μa V I I Input current RESIN V I = 0 V to V DD 2 CONTROL V I = V DD 7 SENSE V I = V 0 SENSE, TLC770 only V I = V 2 I DD(d) Supply current during t d RESIN = V DD, I DD Supply current SENSE = V DD V IT max + 0.2 V 9 6 μa CONTROL = 0 V, Outputs open RESIN = V DD, SENSE = V DD, 20 0 μa V DD = V, V CT = 0, CONTROL = 0 V, Outputs open C I Input capacitance, SENSE V I = 0 V to V DD 0 pf Typical values apply at T A = 2 C. The lowest supply voltage at which becomes active. The symbol V res is not currently listed within EIA or JEDEC standards for semiconductor symbology. Rise time of V DD μs/v. NOTES: 2. All characteristics are measured with C T = 0. μf.. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0. μf) should be connected near the supply terminals. 70 UNIT V V mv μa POST OFFICE BOX 60 DALLAS, TEXAS 726

TLC770-Q, TLC770-Q, TLC77-Q SGLS208A OCTOBER 200 REVISED MAY 2008 switching characteristics at V DD = V, R L = 2 kω, C L = 0 pf, T A = Full Range (unless otherwise noted) PARAMETER MEASURED FROM TO (INPUT) (OUTPUT) t d Delay time V I(SENSE) V IT+ and t PLH t PHL t PLH t PHL t PLH t PHL t PLH t PHL t PLH t PHL low-to-high-level output high-to-low-level output low-to-high-level output high-to-low-level output low-to-high-level output high-to-low-level output low-to-high-level output high-to-low-level output low-to-high-level output high-to-low-level output Low-level minimum pulse duration to switch and SENSE RESIN TEST CONDITIONS RESIN = 0.7 V DD, CONTROL = 0.2 V DD, C T = 00 nf, T A = Full range, See timing diagram TLC77xx MIN TYP MAX UNIT. 2..2 ms 20 V IH = V IT+ max + 0.2 V, V IL = V IT min 0.2 V, RESIN = 0.7 07 V DD, CONTROL = 0.2 V DD, CT = NC 20 20 μs V IH = 0.7 07 V DD, V IL = 0.2 V DD, 60 SENSE = V IT+ max+02v 0.2 V, ns CONTROL = 0.2 V DD, 6 CT = NC 20 μs V IH = 0.7 V DD, V IL = 0.2 V DD, 8 ns CONTROL SENSE = V IT+ max+02v 0.2 V, RESIN = 0.7 V DD, CT = NC SENSE RESIN t r Rise time and t f Fall time NC = No capacitor, and includes up to 00-pF probe and jig capacitance. V IH = V IT+ max + 0.2 V, V IL = V IT min 0.2 V, V IL = 0.2 V DD, V IH = 0.7 V DD 0% to 90% 8 90% to 0% μss μss ns/v 6 POST OFFICE BOX 60 DALLAS, TEXAS 726

TLC770-Q, TLC770-Q, TLC77-Q SGLS208A OCTOBER 200 REVISED MAY 2008 PARAMETER MEASUREMENT INFORMATION DUT V R L (see Note A) C L (see Note B) NOTES: A. For switching characteristics, R L = 2 kω. B. C L = 0 pf includes jig and probe capacitance. Figure. AND Output Configurations I, Q, and Y suffixed devices t w(l) 0.7 VDD 0. V DD 0.2 V DD M suffixed devices VIT+max + 200 mv 2.7 V t w(l) t w(l). V 0. V V IT V IT+ V IT min 200 mv (a) RESIN (b) SENSE Figure 2. Input Pulse Definition Waveforms POST OFFICE BOX 60 DALLAS, TEXAS 726 7

TLC770-Q, TLC770-Q, TLC77-Q SGLS208A OCTOBER 200 REVISED MAY 2008 TYPICAL CHARACTERISTICS VIT (TA)/VIT (2 C) Normalized Input Threshold Voltage.00.00.00.002.00 0.999 0.998 0.997 0 NORMALIZED INPUT THRESHOLD VOLTAGE vs TEMPERATURE 20 0 20 0 60 80 00 20 T A Temperature C Supply Current μ A I DD 0 9 8 7 6 2 0 0. SUPPLY CURRENT vs SUPPLY VOLTAGE RESIN = V DD = V to 6. V SENSE = GND CONTROL = GND CT = Open = 00 pf T A = 2 C 0.. 2.... 6. V DD Supply Voltage V Figure Figure V OH High-Level Output Voltage V.. 2. 2. 0. 0 0. HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 2 C 8 C 2 C 0 C V DD =. V RESIN =. V SENSE = 0. V CONTROL = 0 V CT = Open = 00 pf 0 C C 0 0 20 2 0 0 I OH High-Level Output Current ma V OL Low-Level Output Voltage V 6 2 0 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT V DD =. V RESIN =. V SENSE = V CONTROL = 0 V CT = Open = 00 pf 2 C 8 C 2 C 0 C C 0 C 0 0 20 2 0 I OL Low-Level Output Current ma Figure Figure 6 8 POST OFFICE BOX 60 DALLAS, TEXAS 726

Input Current μ A I I 8 6 2 0 2 6 8 0 TLC770-Q, TLC770-Q, TLC77-Q SGLS208A OCTOBER 200 REVISED MAY 2008 TYPICAL CHARACTERISTICS INPUT CURRENT vs INPUT VOLTAGE AT SENSE V DD =. V CT = Open = 00 pf 2 C C 0 2 6 V I Input Voltage at SENSE V Figure 7 2 C C Minimum Pulse Duration at SENSE μ s t w 7 6 2 0 0 MINIMUM PULSE DURATION AT SENSE vs SENSE THRESHOLD OVERDRIVE 0 00 0 200 20 00 0 00 Sense Threshold Overdrive mv Figure 8 V DD = 2 V Control = 0. V RESIN =. V CT = Open = 00 pf POST OFFICE BOX 60 DALLAS, TEXAS 726 9

TLC770-Q, TLC770-Q, TLC77-Q SGLS208A OCTOBER 200 REVISED MAY 2008 APPLICATION INFORMATION V DD 00 kω 0. μf 0. μf V DD TLC77xx RESIN V DD SENSE NC TMS70C20 CT CONTROL GND GND Figure 9. Reset Controller in a Microcomputer System V DD 0. μf V DD TLC77xx 0. μf RESIN SENSE CONTROL CT CS V DD 0. μf TMS70 CSH GND 2K 8 CMOS RAM ADD0 DATA0 7 6 8 A0 A D0 D7 GND R/W R/W GND Figure 0. Data Retention During Power Down Using Static CMOS RAMs 0 POST OFFICE BOX 60 DALLAS, TEXAS 726

PACKAGE OPTION ADDENDUM www.ti.com 2-Nov-207 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan TLC770QPWRGQ ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) TLC770QPWRQ ACTIVE TSSOP PW 8 200 Green (RoHS & no Sb/Br) TLC770QPWRGQ ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) TLC77QPWRGQ ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) TLC77QPWRQ ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) (2) Lead/Ball Finish (6) MSL Peak Temp () Op Temp ( C) Device Marking (/) CU NIPDAU Level--260C-UNLIM -0 to 2 770Q CU NIPDAU Level--260C-UNLIM -0 to 2 770Q CU NIPDAU Level--260C-UNLIM -0 to 2 770Q CU NIPDAU Level--260C-UNLIM -0 to 2 77Q CU NIPDAU Level--260C-UNLIM -0 to 2 77Q Samples () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 0 RoHS substances, including the requirement that RoHS substance do not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=000ppm threshold. Antimony trioxide based flame retardants must also meet the <=000ppm threshold requirement. () MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. () There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. () Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page

PACKAGE OPTION ADDENDUM www.ti.com 2-Nov-207 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLC77-Q : Catalog: TLC77 Enhanced Product: TLC77-EP NOTE: Qualified Version Definitions: Catalog - TI's standard catalog product Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com -Nov-207 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A0 (mm) B0 (mm) K0 (mm) P (mm) W (mm) Pin Quadrant TLC770QPWRGQ TSSOP PW 8 2000 0.0 2. 7.0.6.6 8.0 2.0 Q TLC770QPWRQ TSSOP PW 8 200 0.0 2. 7.0.6.6 8.0 2.0 Q TLC770QPWRGQ TSSOP PW 8 2000 0.0 2. 7.0.6.6 8.0 2.0 Q TLC77QPWRGQ TSSOP PW 8 2000 0.0 2. 7.0.6.6 8.0 2.0 Q TLC77QPWRQ TSSOP PW 8 2000 0.0 2. 7.0.6.6 8.0 2.0 Q Pack Materials-Page

PACKAGE MATERIALS INFORMATION www.ti.com -Nov-207 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC770QPWRGQ TSSOP PW 8 2000 67.0 67.0.0 TLC770QPWRQ TSSOP PW 8 200 67.0 67.0.0 TLC770QPWRGQ TSSOP PW 8 2000 67.0 67.0.0 TLC77QPWRGQ TSSOP PW 8 2000 67.0 67.0.0 TLC77QPWRQ TSSOP PW 8 2000 67.0 67.0.0 Pack Materials-Page 2

SCALE 2.800 PW0008A PACKAGE OUTLINE TSSOP -.2 mm max height SMALL OUTLINE PACKAGE 6.6 TYP 6.2 SEATING PLANE C A PIN ID AREA 0. C 8 6X 0.6. 2.9 NOTE 2X.9 B.. NOTE 8X 0.0 0.9 0. C A B.2 MAX SEE DETAIL A (0.) TYP 0.2 GAGE PLANE 0-8 0.7 0.0 DETAIL A TYPICAL 0. 0.0 2288/A 02/20 NOTES:. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y.M. 2. This drawing is subject to change without notice.. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0. mm per side.. This dimension does not include interlead flash. Interlead flash shall not exceed 0.2 mm per side.. Reference JEDEC registration MO-, variation AA. www.ti.com

PW0008A EXAMPLE BOARD LAYOUT TSSOP -.2 mm max height SMALL OUTLINE PACKAGE 8X (0.) 8X (.) SYMM 8 (R 0.0) TYP SYMM 6X (0.6) (.8) LAND PATTERN EXAMPLE SCALE:0X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.0 MAX ALL AROUND 0.0 MIN ALL AROUND NON SOLDER MASK DEFINED SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 2288/A 02/20 NOTES: (continued) 6. Publication IPC-7 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

PW0008A EXAMPLE STENCIL DESIGN TSSOP -.2 mm max height SMALL OUTLINE PACKAGE 8X (0.) 8X (.) SYMM 8 (R 0.0) TYP SYMM 6X (0.6) (.8) SOLDER PASTE EXAMPLE BASED ON 0.2 mm THICK STENCIL SCALE:0X 2288/A 02/20 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-72 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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