HOME ASSIGNMENT 1. For the differential amplifier circuit shown below in figure.q1, let I=1 ma, V CC =5V, v CM = -2V, R C =3kΩ and β=100. Assume that the BJTs have v BE =0.7 V at i C =1 ma. Find the voltage at the emitters and at the outputs. 2. For the differential amplifier circuit shown below in figure.q2 with an input of +1V and with I=1 ma, V CC = 5V, R C =3kΩ and β=100, find the voltages at the emitters and the collector voltages. Assume that the BJTs have v BE =0.7 V at i C =1 ma. Figure.Q1 Figure.Q2 3. For the BJT differential amplifier shown below in figure.q3, find the value of the input differential signal, v id = v B1 v B2, that causes i E1 = 0.80I. Figure.Q3 4. When the output of a BJT differential amplifier is taken differentially, its CMRR is found to be 40 db higher than when the output is taken single-endedly. If the only source of common-mode gain when the output is taken differentially is the mismatch in collector resistances, what must this mismatch be in percent?
5. The differential amplifier shown below uses transistors with β=100. Evaluate the following: a) The input differential resistance R id. b) The overall differential voltage gain v o /v sig (neglect the effect of r o ) c) The CMRR in db. Figure.Q5 6. For the circuit below determine an optimum value for R offset to minimize offset and drift. Determine the output offset voltage if V os = 3mV and I os = 100nA. R i = 2kΩ, R f = 40kΩ, R load = 20kΩ. 7. Find the voltage gain, input impedance, and output voltage. Figure.Q6 Figure.Q7 8. For the circuit below, find the voltage gain, input impedance, and output voltage. If slew rate is 2 volts per microsecond, find f max (power bandwidth) for a 10 volt peak output.
9. A 5 khz square wave with 10 V pp is applied to a practical integrator. Show the output waveform voltages. Figure.Q8 Figure.Q9 10. A 1.0 khz, 10 V pp triangular wave is applied to a practical differentiator as shown in figure.q10. Show the output in relationship to the input. 11. A Miller integrator whose input and output voltages are initially zero and whose time constant is 1ms is driven by the signal shown below. Sketch and label the output waveform that results. Also sketch and label the output waveform, when fed with a string of pulses of 10 µs duration and 1 V amplitude rising from 0. Figure.Q10 Figure.Q11 12. Design a circuit, using one ideal op-amp, whose output is v o = v I1 + 3v I2 2(v I3 + 3v I4 ). 13. Use two ideal op-amps and resistors to implement the summation function. v o = v 1 + 2v 2 3v 3 4v 4 14. Determine the frequency of oscillation of the circuit below. R i =10kΩ, R f =15kΩ, R d =8kΩ, R=20kΩ, C=0.1uF Figure.Q14
15. The figure below shows the loop gain of a feedback amplifier of an op amp. (a) How much must the loop gain be reduced to just make the amplifier stable? (b) Estimate the reduction in loop gain to make the amplifier stable with a 45 o phase margin. 16. For the class-a amplifier shown, show that the maximum efficiency for a sinusoidal input signal 25%. Clearly state assumptions you make. For example, ignore saturation 17. A class A emitter follower, biased using the circuit shown in figure.q17 uses V CC = 5V, R = R L = 1kΩ, with all transistors (including Q 3 ) identical. Assume V BE = 0.7 V, V CEsat = 0.3 V, and β to be very large. For linear operation, what are the upper and lower limits of output voltage, and the corresponding inputs? Figure.Q16 Figure.Q17 18. The output voltage of a three-terminal voltage regulator is 5 V @ 5 ma load, and 4.96 V @ 1.5 A load. What is the regulator s output resistance and load regulation?
19. What is v o in the following circuit if V REF = 2 V, R 1 = 500Ω, and R 2 =200Ω? 20. What is the output voltage of the series regulator?