2017 IEEE 67th Electronic Components and Technology Conference Embedded Si Fan Out: A Low Cost Wafer Level Packaging Technology Without Molding and De-bonding Processes Daquan Yu*, Zhenrui Huang, Zhiyi Xiao, Li Yang, Min Xiang Huatian Technology (Kunshan) Electronics Co., Ltd. 112 LongTeng RD, Economic & Technical Development Zone Kunshan, Jiangsu, China Daquan.yu@htkjks.com Abstract Advanced packaging technology plays more and more important role for device miniaturization, system integration, and performance enhancement. Among many new packaging technologies, fan-out wafer level packaging (FOWLP) aroused more interests and showed the advantages of higher number of I/Os, integration flexibilities, low cost, and small form factor due to the elimination of substrate. However, FOWLP using epoxy mold compound (EMC) material faces a number of technical challenges such as warpage wafer handling, difficult to fabricate fine-pitch redistribution layer (RDL), and reliability issues for large package due to the CTE mismatch between chip and EMC. In addition, for high performance SiP, advanced FOWLP with multilayer fine-pitch RDLs, excellent alignment accuracy, shortest interconnect routing between dies, and ultra small form factor was required. In this paper, the development of a wafer level embedded silicon fan-out, named esifo technology was reported. For esifo package, the known good dies are embedded in the cavities formed on silicon wafer and the micro-scale gap between the dies and cavities is filled by epoxy material. An almost entire silicon surface was constructed as the fan-out area for RDL and BGA. The process is simple comparing with standard FOWLP since there is no molding, temporary bonding and de-bonding process. The key advantage is that the CTE for dies and silicon wafer is same and there is no warpage issue during manufacturing which results in good packaging yield. An esifo package with size of 3.3 3.3mm, one layer RDL and 50 BGAs was successfully demonstrated. The results proved that the process of esifo was simple and suitable for high density system integration with ultra low profile. Various reliability tests were carried out to study the package reliability and no failure was found. The simulation results show that for the same package, esifo has lower thermal stress than FOWLP using EMC. Keywords-WLP; Fan-out; Dry etch; Die attach; RDL I. INTRODUCTION The growing and diversifying system requirements have continued to drive the development of a variety of new package styles and configurations: small form factor and lightweight technology, low profile technology, high pin count technology, high speed technology, lower cost. With the development of bumping, RDL, TSV, wafer bonding, debonding and wafer molding techniques, various wafer level packaging technologies such as WLCSP, 2.5D, 3D- WLCSP, and fan-out wafer-level packaging (FOWLP) were developed [1]. FOWLP in which tested known good dies are reconstructed and surrounded by epoxy mold compound (EMC) material which spreads the package footprint outside the die surface showed more advantages comparing with fanin WLCSP. The package size has no limit to the die size and suitable for multi-die integration. Therefore, FOWLP has been used in various products such as baseband, RF (radio frequency) transceiver, and PMICs (power management ICs) [2]. 3D ewlb-pop and ewlb-sip were also developed for highly integrated, miniaturized, low profile and cost effective system integration [3]. Recently, TSMC developed INFO technology and realized the mass production for integration of A10 processor and memory [4], which inspires the packaging houses and foundries to develop their own FOWLP for the forecasted explosive growth of the market in the next few years [1]. In order to reduce overall cost, panel from fan-out technology was proposed to provide high volume manufacturing with more effective process. However, there are many challenges such as warpage, die shift, low yield and lack of production tools [5]. Although FOWLP has been used for mass production, there are still a number of challenges need to be resolved. Typically, there are five major steps for FOWLP including KGD reconstruction, molding, de-bonding, wafer level RDL and backend process. For process point of view, it is very troublesome to handle EMC wafer, which usually has a large warpage since the EMC has big difference CTE with silicon chip. In addition, the manufacturing of fine pitch RDL on EMC surface is also difficult. Therefore, engineers and researchers are working hard to develop new fan-out technology with simple process, low cost and high yield. II. PROCESS DEVELOPMENT OF ESIFO Fig. 1 shows the structure of an embedded Si Fan-Out (esifo) package, which is filed in 2015 [6]. In the package, known good die was embedded in silicon carrier and the micro gap between the die and silicon was filled by polymer. The die and silicon carrier reconstruct a surface for RDL routing and solder bump formation. The big difference with normal FOWLP is that there is no EMC in esifo package. The process flow of esifo package manufacturing is illustrated in Fig. 2. Firstly, a silicon wafer was used to form cavities with certain depth. Dry etch by Bosch process is ideal for cavity formation. Secondly, thin dies with designed 2377-5726/17 $31.00 2017 IEEE DOI 10.1109/ECTC.2017.166 28
thickness were attached into the cavities by the attached film on the bottom of the dies. After die attachment, a reconstructed device wafer was fabricated. Thirdly, the micro gap between the die and sidewall of the cavity as well as the surface of the reconstructed wafer were filled and laminated at the same time by dry film using vacuum process. Fourthly, the pads on dies were opened by lithography and development. Fifthly, RDL was fabricated by standard process including seed layer deposition, PR formation, plating, PR strip and seed layer etching. For single RDL design, the next step was repassivation. Then followed BGA formation, wafer thinning and final dicing. Finally, an esifo package was fabricated. Multilayer RDL can be formed according to package requirement. film (DAF) which is used for adhesive bonding of the die on the bottom of the silicon cavity. The thicknss of the DAF is about 15 m. Finally, the wafer was diced and the dies were ready for pick place process. Figure 1. Schematic view of silicon fan-out structure. There are a number of advantages for esifo package. There is nearly no warpage since silicon wafer was used as reconstruct substrate. The process is quite simple since there is no molding, temporary bonding and de-bonding requirement. Fine-pitch RDL manufacturing is easier on Si comparing with molding compounds and can achieve high density routing. Furthermore, it can get mall form factor since the thinning of wafer is the last step. Figure 3. Cross-section view of the cavity after process optimization: profile; bottom. Figure 2. Process flow of esifo package manufacturing. To prove the concept of esifo, a 3.3 3.3mm package with minimum 400 m pitch of BGA was fabricated. In the package, there is one layer Cu RDL with thickness of 3 m, minimum line width of 14 m. The die size is 1.96 2.36mm with a pad pitch of 90 m. The device wafer was thinned to 100 m. Wafer thinning process was quiate mature and the thickness variation of ±5 m can be easily achieved. Then backside of the thinned wafer was laminated with die attach In present study, 8 in. blank silicon wafer is used for esifo process development. At first, the cavities with vertical sidewall for die embedding was formed by Bosch process. Althogh the total thickness of die and DAF was 115 m, the overflow of DAF during die attach process would reduce the thickness. After preliminary test, the depth of the cavities on the wafer was set as 107 m. The length and width of cavities is ~30 m larger than die size on each side. An inductive coupled plasma (ICP) source reactor is used and the gases used in the Bosch process are SF6 and (C4F8). For TSVs formation, silicon etch is quite mature since the etching area is small [7]. However, the etching of large silicon cavities with good TTV is challenging. In addition, smooth bottom surface without any grass and bumps was required to prevent die tilt and carcks during die attach process. After process optimization, the average depth of the cavities is 106.7 m with TTV of ± 4 m. To achieve the stringent requirement of the cavity profile, etching rate of 29
7.2 m/min is developed which is slow comparing with small vias or trench etching. Fig. 3 shows the cross-section view of a cavity for die embedding. The sidewall and bottom of the cavity is quire smooth. There is no grass or bumps, which should be eliminated for successful die attachment. The footing variation in a single cavity is less than 5 m without counting the region of 15 m away from the sidewall. The flat bottom with ~1 m rougness is achieved which is suitable for die attachment. A dedicated die attach tool for FOWLP from ASM, NUCLEUS, was used for C2W attachment with an accuracy of ±4 m. According to measurement results, the maximum die shift of 3.1 m was achieved. Fig. 4 shows the image of a die after attachment. The gap of ~30 m was process for one die and all dies on one wafer. As shown in Fig. 4, after die attachment, a re-constructed silicon wafer was formed and the gap between die and cavity is too small to be found. The filling of the trench between the die and silicon carrier was a key process for esifo. A vaccum dry film lamination process was developed. The trench was filled without voids and carcks. Further, a passivation layer on the reconstructed wafer surface was formed at the same time. The filling results were showed in Fig. 5 after RDL fabrication. It can be found that the filling is successful. The die thickness of ~96 m, and the thickness of DAF in the two samples were 11.6 and 7.6 m respectively. The difference in hight of the surface of embedded die and silicon was about about 4 m. Based on the measuremnt of 15 samles from differen region of the wafer, the maximum difference is 6.3 m. The passivaton layer thickness variation on silicon carrier is less than 3 m and that on die surface is less than 8 m. Comparing with Fig. 5 and, it can be found that when RDL pass the trench, a small protrusion of ~2 m was formed. Figure 5. Cross-section view of the trench where without RDL, with RDL routing Figure 4. Images after die attach process: one die, whole wafer. To simplify the process, in present study, the film is patternable. A mimimum opening size of 15 m can be achieved based on process development. In present package, pad opening of 30 m is required. Based on calculation, the shift of the pad opening after lithography is less than 7 m. After process, the average value of opening shift was 2.8 m 30
with the maximum shift of 6.5 m. Fig. 6 shows the opening shift after lithography and photoresist develop. The Cu RDL with mimimum width of 15 m and thickness of 3 m was designed. As shown in Fig. 7, after manufacturing, the width of the Cu RDL is about 16.8 m. It can be found that after seed layer etch of Cu and Ti, there is no metal residue on the passivation. Then eletroless plaing of Ni/Au was performed for as protection layer and UBM for BGA. After RDL formation, final passivation was performed followed pad openning for BGA formation. uiniformly and the wafer is still flat with samll warpage. The shear strength of the BGA meets the criteria. Figure 8. The fan-out wafer after backside thinning to 300 m. Figure 6. Opening shift after lithography and photoresist develop. Figure 7. Image of RDL and UBM after Cu plating. Before BGA formation, the wafer was then thinned from backside to 300 m. As shown in Fig. 8, the wafer afer thinning is quite flat and the warpage value of 2mm was achieved. The small warpage is due to the similar CTE between silicon wafer and embedded dies. In process development, some wafer was further thinned to 250 m without issue. Siince thinning of esifo package at the final step, ultra low package profile can be easier achieved. Solder paste printing on the front side of the wafer for BGA formation is doable for the small warpage. BGAs with diameter of 280 m, height of ~120 m were formed using SnAgCu solder paste. The minimum pitch of the BGAs is 400 m. Fig. 9 shows the top and side view of the wafer after BGA formation. It can be seen that the BGAs were formed Figure 9. The fan-out wafer after BGA formation: top view, side view. After dicing, a final esifo package was shown in Fig. 10. The die was embedded in the center of the package and the trench filling with polymer between die and silicon carrier is hardly to be found. It can be found that some BGAs happened to sit on the trench. The cross-section microstructure of the BGA, die and trench was shown in Fig. 11. It can be seen that the filling of the trench is perfect without any voids or seam. The difference in height of the die and silicon wafer surface is about several microns. The thickness of first passivation layer on the reconstructed wafer is about 10 m and the thickness of final passivation is 31
around 20 m. Such a package should be robust based on the microstructure since the die was well fixed by the thin polymer and adhesive into the silicon cavity. conducted for reliability evaluation. 100 samples were used for each reliability test. After reliability tests, the selected samples were cross-sectioned and characterized by scanning electron microscopy(sem). After precondition and reliability tests, no failure was found. According to the SEM observation, there is no abnormal at the interface of die, silicon carrier and RDL. After TC 1000 cycles and HAST for 264 h, there were no voids, cracks or delamination for the filled polymer between die and cavity sidewall, and the adhesive layer between die and cavity bottom. Mechanical simulation was used to analyze the stress distribution during TC test. Fig. 12 showed the 3D model used for simulation and the mises stress contours on the RDLs. Comparing to the stress distribution above the trench filling with polymer, the RDL had a higher stress level near the UBM of the BGAs. It meant the trench filling with large polymer volume was not a main factor to lead the fracture of the RDLs which passed the trench. Figure 10. Outlook of an esifo package. Figure 11.The cross-section microstructure of the esifo package. III. RELIABILITY EVALUATION Prior to the reliability tests, preconditioning was performed to simulate the effects of board assembly on moisturized packaging. The samples were first baked at 125 C for 24 hours to remove the moisture inside the package, and then soaked at 85 C under 60 % relative humidity (RH) for 168 hours. At last, the samples were reflowed at 260 C for 3 times. Thermal cycling (TC) test (-55~125 C) up to 1000 cycles, high temperature storage (HTS) test at 125 C for 1008h, thermal humidity storage (THS) test at 85 C under 85% RH for 264 h, and highly accelerated stress test temperature storage (HAST) test at 110 C for 264 h were Figure 12.The finite element analysis of the fan-out package: the finite element model, the mises stress contours of the RDLs. To evaluate board level reliabilities of the esifo package, a simulation for the SMT process was conducted. 32
As shown in Fig.13, a chip after packaging was mounted on 3 layer printed circuit board (PCB) with a size of 14 14 0.6mm. Both esifo and standard FOWLP using EMC were simulated for comparion. The die was embedded by two type materials, Si and the EMC respectively. Thematerial properties used for evaluation are listed in Table I. embedded chip BGA PCB Figure 13.The finite element analysis of the board level reliability: the model, the mesh. Fig. 14 showed the BGA peeling stress distribution at the fan-out package surface. The maximum peeling stresses for esifo and FOWLP are 55.19 and 194.4MPa, respectively. The stress for esifo package was only one third of FOWLP. As shown in Tabel I, the CTE of EMC is 7 times larger than that of chip for fanout. The reliability of FOWLP is always a challenge for large package due to the CTE mismatch. Therefore, esifo package has a dramatic advantage on thermal stress because of a good CTE match between the silicon carrier and the embedded chip. Table I. Material properties Material Elastic Poisson s CTE, ppm Tg modulus, GPa ratio Si 131 0.278 2.8 -- EMC 8 0.3 20@below Tg 175 65@above Tg Chip 131 0.278 2.8 -- BGA 50 0.4 22 -- PCB 2.45 0.19 14 -- Fig.14.The BGA peeling stress contours for: esifo, FOWLP using EMC. d IV. CONCLUSION In summary, a low cost wafer level fan-out technology esifo was developed in which the die was embedded in silicon for spreading of the package footprint. The esifo process is simple due to the elemination of molding, temporary bonding and de-bonding and at the same time, there is no warapge issue since the silicon carrie has the same CTE with embedded dies. An esifo package with size of 3.3 3.3mm was demonstrated. The die size is 1.96 2.36mm with pad pitch of 90 m. The device wafer was thinned to 100 m and the depth of the cavities on silicon wafer was 107 m. In the package, there is one layer Cu RDL with thickness of 3 m, minimum line width of 15 m. BGAs with diameter of 280 m and 400 m pitch were formed by solder past printing. All the processes were developed and the results showed esifo package was easier to be produced. Reliability tests including THS, T/C, HTS and HAST were carried out and no failure was found. The simulation results indicated the stress distribution on the trench between die and silion carrier was not the lead the RDL fracture. Because the silicon carrier has a good CTE match of the embedded chip, the esifo package could reduce the thermal stress on BGAs dramatically. Present study indicates that the esifo technology is promising for both single die and multidie integration requiring small form factor, high density integration with high yield and low cost. 33
ACKNOWLEDGMENT The authors appreciate the support by ASM Pacific Technology, AMEC, and NMC Ltd for process development. REFERENCES [1] John H. Lau, patent issues of fan-out wafer/panel-level packaging, Chip Scale Review, Nov/Dec 2015, pp. 42-46 [2] John H. Lau, Nelson Fan, Li Ming, Design, material, process, and equipment of embedded fan-out wafer/panel-level packaging, Chip Scale Review, May/June, 2016, pp. 38-44 [3] Yaojian Lin, Chen Kang, Linda Chua, Won Kyung Choi and Seung Wook Yoon, Advanced 3D ewlb-pop(embedded Wafer Level Ball Grid Array-Package on Package) Technology, Proc. 66th Electronic Components and Technology Conference (ECTC), IEEE Press, Jun. 2016, pp. 1772-1777 [4] Chien-Fu Tseng, Chung-Shi Liu, Chi-Hsi Wu, and Douglas Yu, InFO (Wafer Level Integrated Fan-Out) Technology, Proc. 66th Electronic Components and Technology Conference (ECTC), IEEE Press, Jun. 2016, pp. 1-6 [5] Hong-Da Chang, David Chang, Kenny Liu, H. S. Hsu, Rui-Feng Tai, Hsiao-Chun Huang, Yi-Che Lai, Chang-Lun Lu, Chun-Tang Lin, Steve Chiu, Development and Characterization of New Generation Panel Fan-Out (P-FO)Packaging Technology, Proc. 64th Electronic Components and Technology Conference (ECTC), IEEE Press, Jun. 2014, pp. 947-951. [6] Daquan Yu, embedded silicon fan-out package and the method of forming the same, Chinese Patent 201510486674.1, filed on Aug. 11, 2015. [7] Zhiyi Xiao, Jun Fan, Yulong Ren, Yang Li, Xiaohua Huang, Daquan Yu, Wei Zhang, Development of 3D Thin WLCSP Using Vertical Via Last TSV Technology with Various Temporary Bonding Materials and Low Temperature PECVD Process, Proc. 66th Electronic Components and Technology Conference (ECTC), IEEE Press, Jun. 2016, pp. 302-309.. 34