Chapter 1.I.I. Versatile Low Voltaige, Low. Power Op-amp Design. Frode Larsen

Chapter 1.I.I Versatile Low Voltaige, Low Power Op-amp Design Frode Larsen AT&T Microelectronics/Bell Laboratories Abstract In this chapter we will look at low voltage operational amplifier design from a system level approach. Based on the system and application, the most suitable amplifier structure will change, and we will introduce <an architecture that is modular in nature, and thus can easily be modified for a given application. The trade-off between performance and cost will be illustrated with a basic architecture which will be modified to meet various amplifier requirements. All designs were done in a standard CMOS process without low threshold or depletion mode devices. First, a single ended audio driver capable of driving an AC coupled 16Os1, 1OOpF load to within 0.15V of the rails with less than O.O2%THID at 3kHz will be presented. This amplifier operates at a supply range from 2.3 to 5.5V with a quiescent current of 350pA. Next we will look at a low noise fully balanced amplifier optimized to drive large capacitive loads at high speeds with a minimum quiescent current, suitable for sampled data systems. This amplifier could drive a 50pF load at about 35V/,u-sec f3v in a V environment with a quiescent current of 450,uA. Finally, an input/output rail-to-rail fully balanced amplifier will be presented suitable for low noise, audio applications, such as pre-amplifiers, single ended to fully balanced converters, and continuous time filters. Less then O.OOS%THD was achieved in the audio range driving a 10ks1, 15pF load to within O.1V of the rails with a quiescent current of 300pA. 1.1.1.1 Introduction A typical single ended V amplifier designed iin a standard CMOS process without depletion mode or low voltage devices contains a rail-to-rail input stage, one or more gain stages, and a rail-to-rail output stage which might be combined with the last gain stage. We will first cover some of the design criteria for each stage and then present some complete amplifiers suitable for various applications. The intent is to illustrate how a single architecture can be modified to meet a variety of design goals with minimum redesign. 3

4 CHAPTER 1.1.1 The typical rail-to-rail input stage consists of a combination of an n- and p- type differential input stage (Fig. 1.1.1) feeding a high impedance load (Fig. 1.1.6). As the input moves from the low to the high rail, the effective gain moves from the n- to the p-type differential input stage. This makes the overall input transconductance a function of the input voltage, which has led to a lot of research focused on minimizing this variation. This variation could result in increased distortion[l], non optimal compensation[2], and reduced common mode rejection ratio[3]. Several gain stages have been reported in the literature, but the favorite one seems to be a stacked cascode load, which is known to be able to go close to both rails while maintaining a high impedance load for the input stage[4]. By feeding an n-type differential pair into a p-type cascode load and a p-type differential pair into an n-type cascode load, rail to rail input/output can be achieved by simply stacking the two cascode loads as shown in Fig. 1.1.6. This is, however, a high impedance node, and a separate buffer stage has to be added to enable driving resistive loads. The standard n- and p-type input stage with a stacked cascode load will drive the two sides of the stack out of phase. For rail-to-rail, low power applications, a class-ab output stage is required, which typically uses one side of the stack to drive an NMOS output transistor while the other side drives a PMOS output transistor. If we make both sides move in phase, one turns on more as the other turns off, which enables us to go significantly closer to the rails operating the output transistors more efficiently. If we also include a control loop to prevent either side from turning off, we achieve class-ab operation. This is typically done with some kind of feedback into the stacked cascode stage. This chapter will first present some of the well established concerns of low voltage, low power operational amplifier design. We will then present a set of cells that can be combined in various combinations to obtain whatever goals are required with minimum redesign time. This is done by presenting three amplifiers designed with different goals in mind. A basic simple ended amplifier structure will be introduced first, optimized to drive heavy loads with minimum noise and distortion. Two fully balanced, class-ab amplifiers will be presented next, based on the single ended structure. These combines class-ab operation with a programmable common mode output voltage. 1.1.1.2 Input Stages The typical rail-to-rail input stage consists of an n-type differential pair biased by a p-type current mirror and a p-type differential pair biased by a n-type current mirror as shown in Fig 1.1.1 As the input voltage approaches the lower rail, the n-type differential pair turns off, while as the input approaches the positive rail, the p-type differential pair turns off. The total differential current going to the load, is the sum of the two differential currents, thus the total transconductance of the stage is the sum of the two transconductances. Therefore, the input transconductance, and thus the gain, is a function of the input voltage. If the amplifier is compensated for sufficient phase margin operated at midrail, where the input transconductance is the sum of the two, it will be over compensated at either rail. Close to the rails, the gain will be cut in half, and assuming the dominant pole doesn t move, it will be over compensated.

EMERGING TECHNOLOGIES 5 Figure 1.1.1 Basic rail-to-rail input stage The total input transconductance is given by the following equation: where K = ;pucoxw/n. As a unity gain follower, the variation in gain leads to distortion, since the error voltage measured between the two input terminalis of the operational amplifier is no longer a linear function of the input voltage. As the error varies non linearly with the input, we get harmonic distortion, which might be significant for low gain amplifiers. To reduce the effect of this problem, several approaches can be taken. Most commonly, the bias current of the two stages are made a function of the input voltage such that the sum of the two transconductances are independent of the input voltage. Alternatively additional input pairs can be added as one of the other pairs turn off. A rather constant overall transconductance could be achieved by simply adding a second n-type input stage to the first one whenever the p-type input stage turns off, and similarly add another p-type stage when the n-type turns off. Thus, we would always have a set of two input stages operational, and by tuning the tripping points, the overall input transconductance can be made reasonably independent of the input voltage [3]. If we design the circuit such that KN = Kp and add a control circuit to keep the sum of the square roots of the two biasing currents constant a constant input transconductance will be achieved. One possible implementation was given in [a] and is shown in Fig. 1.1.2. By adding the gate-source voltages for M1 through M4, we obtain the following equation which satisfies Eqn. 1, given KN = Kp. VGSMl - VGSM2 + VGSM3 - VGSM4 = 0 (2) = 2 6 (3) The common source of the n-type differential input pair is biased by In, and the p- type differential input pair is biased by Ip. Thus, level shifted version of the input voltage is applied to the gate of M6 through the n-type differential pair, which controls how the total bias current of 410 gets split between Ip and In. Fig. 1.1.3 shows a different approach, which does not require KN to be equal to Kp, presented in [5, 61. By keeping the sum of the gate-to-source voltage of a PMOS device (M3)

6 CHAPTER 1.1.1 Figure 1.1.2 Constant gm input stage, assuming I(N = Kp Vdd Figure 1.1.3 Constant gm input stage, KN = Kp not required biased with the n-channel bias current (In), and the gate-to-source voltage of an NMOS device (M4) biased with the p-channel bias current (Ip) constant, a constant input transconductance can be achieved. This is done by biasing M1 and M2 with current sources to set the voltage at node A. The overall input transconductance is given by the following equation:

EMERGING TECHNOLOGIES 7 However, for most low frequency applications, a constant gm rail-to-rail input stage is not required, as most of the distortion originates from other sources. For high gain amplifiers, with a gain of at least 60dB, most of the distortion will be introduced by different mismatch between the n- and p-type input stage. As the gain varies, the error term seen between the two input terminals changes, yielding distortion. However, this error term is dominated by changes in the input referred mismatch which directly add to the output. Fig. 1.1.4 shows the input, output, and the error term measured across the two input terminals with and without an 0.5mV mismatch added to the p-type differential pairs, and a -0.5mV mismatch added to the n-type differential pair. At mid-rail, both input stages are operational, and Input. output driving 0hm. loop load 3V at Vdd49V 05- > 0- -05- -1 b 3 Figure 1.1.4 Input, output, and error signal with and without mismatch. Note that input and output are identical on the scale shown here the mismatch introduced by the n-side cancel the mismatch from the p-side, and the plot for the devices with and without mismatch roughly follow one another. This is to be expected since both input stages would be designed to have identical transconductance. As the input goes high, the PMOS input stage turns off, and the -0.5mV NMOS mismatch gets added to the error. As the input goes low, the NMOS input stage turns off, and the 0.5mV PMOS mismatch stage gets added to the error. Thus, for distortion at low frequencies, a constant gm input stage would be a waste of silicon for this amplifier. This amplifier is driving a Q load at IkHz, and the dc gain for this load is about 90db. By adding a mismatch of f2mv between the two input stages, the total harmonic distortion (THD) went from 0.009% to 0.041% for this particular amplifier. Thus, this mismatch dominates the distortion, and a constant gm input stage would not yield any significant improvement. For practical designs, it is critical to have a cell that can be modified separately from the rest of the blocks in the amplifier, where your favorite constant-gm control loop could be added in those rare occasions where the extra silicon is justified. Fig. 1.1.5 shows a rail-to-rail input stage, where there is no common mode coupling from the input stage to the load.

8 CHAPTER 1.1.1 Vdd t O E s a d 3 1 Vn If lil ii-' I t O E *ad Gnd Figure 1.1.5 Isolated input stage The center 4 transistors of each block makes the two output currents of the block fully differential and independent of the bias current of the block. Thus, the input stage can be modified, without eflecting the operation of the rest of the circuit. The input block consists of a PMOS dii'ierential pair that is operational whenever the input is below the supply rail by the sum of a PMOS threshold and saturation voltage, and the NMOS stage is operational when the input is a minimum of an NMOS threshold and saturation volta,ge above the lower rail. For a typical single doped poly process, this would imply a minimum supply voltage of about 2.3V. Fig. 1.1.4 was obtained with an amplifier utilizing this input stage. 1.1.1.3 Gain and Output Stages In order to achieve the required gain, the output currents from the input stage are typically fed into a stacked cascode load, which again feeds a pair of NMOS and PMOS transistors. An additional control loop is added, sensing the currents through the output transistors, preventing either from turning off. Fig. 1.1.6 provides a simple block diagram of a typical architecture. The 4 differential outputs from the input stage feed the cascode load, while the outputs of the cascode load feed the output transistors. The output currents are monitored and compared to a current reference by the class-ab control circuit, and a common mode current is fed back to the cascode to achieve class-ab operation. For rail-to-rail, class-ab operation, the PMOS and NMOS output buffers need to be fed in phase. Since a differential stage provides differential signals, we must either invert one half of the input signal before we feed it to the cascode stack, or we can let the two sides of the cascode stack move out of phase and simply invert one of the outputs with a unity gain inverter before feeding it to the output drivers. The first approach requires a multitude of circuitry in the signal path [a] which will generate noise, while the second approach simply requires an inverting amplifier made out of two transistors [l]. The additional stage on the one side will effect the settling behavior somewhat, but is the preferred approach for low frequency applications. In the following sections we will look at three amplifiers,

EM ERG IN G TECHNOLOGIES 9 a - Rail-to-rail n-outputs p-outputs - + + I VB2 4 Vdd I I 1 I 1 I programipg classdg Class-AB monitor -- 7 circuit I 1 In-sensor I Gnd L Figure 1.1.6 Block diagram of rail-to-rail class-ab amplifier based on the same architecture presented in [I], but optimized for three different applications. 1.1.1.4 Single Ended Audio Amplifier Fig. 1.1.7 shows the gain and output stage of the single ended audio buffer. Figure 1.1.7 Single ended audio amplifier The buffer was designed for minimum quiescent current, minimum distortion, and minimum noise while driving an audio frequency, ac-coupled 160R, pf load 3Vpp at a V supply. For rail to rail input and minimumcoupling between stages, the input stage given in Fig 1.1.5 was used. The output transistors, M12 and M15, are fed bly the two branches of the cascode load. Since the cascode outputs move out of phase, the signal feeding M15 is first inverted by M1 and M2.

10 CHAPTER 1.1.1 M10, M14, and M17 sense the currents through the output devices, and feed the class-ab control loop. M11 sets the minimum current, and if either the current through M10 or M14/17 becomes too small, the differential stage consisting of M5 through M7 prevents either output transistor from turning off. If the voltage betaween A and B changes, M6 and M7 will feed a common mode current into the upper cascode to drive both outputs in whichever direction needed to prevent the output transistors from turing off. The class-ab control loop consists of the differential amplifier, M5 through M7, and the translinear loop consisting of M3, M4, M8, and M9 [l]. The class-ab control loop is here shown biased with a PMOS source follower below the supply rail. The minimum supply voltage for the output stage is determined by the bias voltage of the translinear loop, added to a p-channel VGS (M9/M3) and an n- channel VDssat (M14/M17). For operation down to 2.3V a slightly more elaborate circuit was included to provide a fixed voltage supply close to the supply rail feeding the translinear loop. This circuit is however not shown here. Compensation was mainly achieved with C1 and C2. Not shown are other capacitors which were added to achieve good phase margin for all loading conditions. Fig. 1.1.8 shows the input, output and the error term for a 3Vpp signal when the buffer is driving a 16052, loopf load at Hz operated at V. - + 9 tllm Input and output. RL=160, CL=lOOpF. VDD3 3V 4 1 10 02 04 06 08 1 12 14 16 18 2 n Time x lo-3 Error term, RL=160 CL =IWpF. VDDA.3V " O t I -5 - Figure 1.1.8 Buffer driving 1600, loopf load The maximum error signal for this load is about 0.5mV. Since the effective input mismatch switches from the mismatch seen across the n-stage to the p-stage or a, combination of both as the input voltage goes from the upper to the lower rail, this mismatch will be the dominant source of distortion. The input referred mismatch will typically be more than about 2mV, and will thus dominate. Without any mismatch, the total ha,rmonic distortion (THD) was 0.016% for a 3V swing with a V supply driving 160R, loopf load. With a 2mV difference in mismatch between the p- and n-type differential pair the total harmonic distortion (THD) was 0.041%.

EM ERG IN G TECH N o LO GIES 11 Table 1.1 lists total harmonic distortion (THD) as a function of load, voltage swing, supply voltage, and frequency. For supply voltages below 2.3V we see significant THD degradation. Table 1.1 f Hz 1k 1k - RL R - 130 30 25 Simulated harmonic distortion CL pf - VIN v 3.1 3 2.5 2 2 2.5 2.5 2.5 2 2 1.5 - VDD V 3.0 2.7 2.5 2.3 2.0 -- TIJD %l -- 0.016 0.009 0.006 0.016 0.023 0.005 0.009 0.018 0.006 0.008 01.871 Fig. 1.1.9 shows the current through the output transistors and the supply for a 160R, l00pf load driven 3Vpp. -0 035 Driver and supply currents RL=160. CL=iOOpF. VDD=3 3V o::fi!3ii7-0015 010 02 U4 06 08 1 12 14 16 18 2 ~oe3z2 Time x 1u-3 Expanded minimum currents -0-15 0 U1 02 03 04 05 06 07 08 09 1 Time xio= Figure 1.1.9 Output and supply currents, maximum load From Fig. 1.1.9 we find that the current through the output transistors goes from a minimum of about pa, determined by the current set by M11 and the appropriate scaling to a maximumof about, S.4mA This corresponds to 1.5V across a 160R load, or 3Vpp for an ac coupled load. The total quiescent power supply current is about 350pA.

12 CHAPTER 1.1.1 Fig. 1.1.10 shows the frequency response of the amplifier with no load and with a 160R, loopf load. This simulation was done with the input at mid rail using nominal model parameters. Frequency response, gain, Open and maximum load Frequency response. phase, open and maximum load Figure 1.1.10 Nominal frequency response, no and max load The amplifier has a phase margin of 68 degrees at 3.2MHz, driving a 16OR, loopf load, and a phase margin of 72 degrees at 5.8MHz without the load. The corresponding DC gains are 84db and l26db, which is sufficient to enable us to disregard the distortion caused by the variation in gain with input voltage. This amplifier was optimized for noise as well as distortion, and the input referred noise was about -18.5dbrnc. Noise optimization was particularly simple with this structure, since sizing could be done independently on each stage. There is no need to be concerned with matching between devices in the output stage with devices in the input stage, thus enabling resizing for optimum noise figure independently in the two stages. 1.1.1.5 filly Balanced Amplifiers To achieve optimum performance at low voltages, fully balanced architectures are preferred. This doubles the available signal swing, cancels all even order harmonics, and reduces coupling from common made noise murces. Hawever, the single ended amplifier presented utilizes common mode feedback to the cascode load to achieve class-ab operation, obtaining a fully balanced version is not trivial. In the next section we will present a technique to get around this problem and discuss two fully balanced, class-ab amplifiers. 1.1.1.5.1 High Speed, Low Distortion Amplifier Fig. 1.1.11 shows a schematic of a high speed, fully balanced, class-ab amplifier with rail-to-rail output. This amplifier was designed for use in high speed, sample data systems, such as switched capacitor filters and switched capacitor Sigma Delta modulators. The

EMERGING TECHNOLOGIES 13 Figure 1.1.11 High speed, rail-to-rail amplifier most critical design criteria were thus fast settling, high slew rate, and low noise when driving capacitive loads less than about 50pF. The input signals to these blocks are typically already fully balanced, and rail-to--rail input is not required. To achieve a high slew rate, we allowed direct coupling between the input and output stage. The input devices, Mil and Mi2, draws quiescent current from the upper side of the stacked cascode load, unlike what was done in the previous design. For the single ended amplifier, the output of the input stage was a purely differential signal current. An output stage similar to the single ended one was used for this architecture, with an additional driver added, driven out off phase with the first output. This was achieved by simply connecting it to the oppositle sides of the cascode load. If the one side is operating in class-ab we know the second side will, since they are identical circuits driven by the same nodes, just out of phase. Thus, a single class-ab control loop was shared between the two. A common mode feedback loop senses the voltage across a resistive voltage divider, and compares it to the asserted common m0d.e input voltage. The output current of the common mode stage sinks or sources current into nodes 3 and 4, turning the NMOS transistors on more or less heavily, thus moving the common mode output. This common mode loop will have significantly less gain than the signal path, but this is beneficial in achieving the appropriate common mode phase margin. Additional gain can be achieved by scaling the bias currents set up by Mc3 through Mc5, or simply sizing Mcl and Mc2 as required.

14 CHAPTER 1.1.1 Fig. 1.1.12 shows the differential mode frequency response when both outputs are loaded by a 15pF capacitor. Difierenfial mode frequency respanse, gain each side dual 15pF load 0 50 glf3il 1 no 1 0' 1 o4 1 o6 i n8 HZ Differential mode frequency response. phase each side, dual 15pF load 01 O0 1 o2 1 Hz o4 1 n6 1 O8 Figure 1.1.12 Differential mode frequency response The amplifier was optimized for maximum speed without ringing. From this plot we find that the nominal unity gain frequency is about ISM& with about 45 degrees of phase margin. The low frequency gain was about 120db. Fig. 1.1.13 shows the common mode frequency response with and without a 15pF load attached to both outputs. As we can see, the common mode dc gain is Common mode trequency response. gain, open and dual 15pF load Hz Common mode frequency response phase open and dual 15pF load Hz Figure 1.1.13 Common mode frequency response only about 48db, and the unity gain frequency is about 2MHz with a phase margin of 70 degrees. From these plot we also see there are minimal change in frequency behavior with and without the 15pF load attached.

EM ERG IN G TECH N 0 L 0 G 1 E S 15 The small common mode gain makes frequency compensation of this loop less critical, and we only need to be concerned about the differential mode stability. As long as the inputs >!ml;l are fully balanced, the slower response of the common mode loop is less of a concern, and this trade off is typically welcome. Fig 1.1.14 shows the input waveforms and differential output of the amplifier hooked up as a charge redistribution amplifier when the input capacitors are 50pF and the output capacitors are 25pF for a gain of 2. Input voltages, switched capacitor integrator 1 0 1 2 3 4 5 sec Differential ou$ut, switched capacitor integrator x lo-. 6-2 -4 1 2 3 4 5 6 sec x Figure 1.1.14 Inputs and output of amplifier driving 25pF Fig. 1.1.15 shows the current through the outpiit devices and from the supply for the same simulation. 1 0.5 - in- Current. output transistors -05- -1 x 1 7 sec Current, supply rail x106-0 5 U -1-1 5 1 2 3 4 5 6 sec x Figure 1.1.15 Output devices and supply current

16 CHAPTER 1.1.1 From these plots, the slew rate is found to be about 35V/p-sec, which corresponds to a current of 0.75mA into a 25pF load as can be seen from the second curve. The quiescent power consumption of the amplifier was about 450pA total, out of which two thirds is for the output stages a.nd the differential input stage. This amplifier was used in a second order switched capacitor filter and a second order switched capacitor Sigma Delta modulator. Therefore, we need to drive rather large capacitive loads to minimize kt/c noise, and the amplifier had to introduce a minimum amount of noise to the system. If we assume fully balanced inputs, the noise will be introduced by the differential signal path. The critical devices were scaled to meet an input noise requirement of -22dbrnc. 1.1.1.5.2 Low Distortion Audio Amplifier For audio applications, a better approach would be to keep the input and output stage separated. The input stage shown in Fig. 1.1.5 combined with the fully balanced output stage shown in Fig. 1.1.11 yields a high performance input output rail-to-rail class-ab amplifier suitable for low frequency applications where noise, distortion, and power consumptions are critical. However, for most applications, rail-to-rail input range would not be required for a fully balanced amplifier structure. Table 1.2 provides the simulated distortion figures achieved utilizing the amplifier as a unity gain inverter, driving two lokr loads Table 1.2 Simulated harmonic distortion 12.1 VDD V 2.5 2.3 2.1 1.9 THD % 0.002 0.018 0.024 0.632 0.002 0.015 0.071 1 J.1.6 Conclusion We have looked at designing low voltage amplifiers using a modular approach to enable quick redesigns and optimizations. Both input/output rail-to-rail amplifiers were operational at supply voltages down to 2.2V, and were implemented without any low threshold or depletion mode devices. First we presented the basic single ended architecture, which was used in a low distortion, low noise single ended audio amplifier capable of driving 160R, loopf to within 0.15V of either supply with less than 0.016% distortion. Next, we looked at how to convert this architecture into a fully balanced structure, and how we could utilize this structure to design a high speed, fully balanced, class-ab amplifier with a slew rate of about 35V/p-sec driving loads of up to 50pF. This amplifier was designed for operation on a fully balanced signal, and did thus not include a rail-to-rail input stage. Finally

EMERGING TECHNOLOGIES 17 we looked at an input/output rail-to-rail, fully balanced class-ab amplifier suitable for low distortion, low noise, low frequency continuou,s time signal processing. This amplifier was designed to drive a 5kR, 15pF load to within 0.1V of the supply with less than 0.005% THD for frequencies below 4kBz and less than -20dbrnc input referred noise. We showed that for most applications, a constant gm input stage is not critical for low distortion applications. As long as the gain of the amplifier exceeds about 80db, most of the distortion will originate from the different mismatch seen between the n-type and p-type input stage. Acknowledgments: The author would like to acknowledge S. Salturai, D. Rich, and D. Marsh for their constructive criticism and comments related to this work, and D. Olejnick for lay-out. REFERENCES [l] S. Sakurai, Design of Rail-to-Rail CMOS Operational Amplifiers for a 3-V Supply, Dissertation Ohio State University 1994. [a] J. Botma, R. Wiegerink, S. Gierkink and R.F. Wassenaar, Rail-to-Rail Constant gm Input Stage and Class AB Output Stage for Low Voltage CMOS Op Amps, Analog Integrated Circuits and Signal Processing, pp. 121-135, Sept. 1994. [3] R. Hogervorst, S. Morteza Safai, J. Tero and J. Huijsing, A programmable 3-V CMOS rail-to-rail opamp with gain boosting for driving heavy resistive loads, IEEE International Symposium on Circuits and Systems, pp. 1544-1547, 1995. [4] S. Zarabadi, F. Larsen and M. Ismail, A Reconfigurable Op-Amp/DDA CMOS amplifier architecture, IEEE Transactions on Circuits and Systems, Part-11, pp. 484-487, June 1992. [5] S. Sakurai and M. Ismail, Low voltage CMOS Operational Amplifiers: Theory, design, and implementation, Kluwer Academic Publishers, 1995. [6] S. Sakurai and M. Ismail, Constant Transconductamce Bias Circuit and Method, U.S. patent No.5,384,548, filed Aug.25,1993, issued. Jan.24, 1995.