Expanding film and process for high efficiency 5 sides protection and FO-WLP fabrication

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2017 IEEE 67th Electronic Components and Technology Conference Expanding film and process for high efficiency 5 sides protection and FO-WLP fabrication Kazutaka Honda, Naoya Suzuki, Toshihisa Nonaka, Hirokazu Noma, Yoshinobu Ozaki Packaging Solution Center, Hitachi Chemical Co., Ltd. 48 Wadai, Tsukuba-shi Ibaraki, 300-4247, Japan E-mail:kz-honda@hitachi-chem.co.jp Abstract The novel expanding film and the process have been developed for the fabrication of 5 sides protection of die and fan out wafer level package. This can skip the time-consuming diereplacement process for die gap widening. The process consists of the steps of expanding of diced-wafer on the film, transferring the dice to the carrier, over-molding and mold dicing. Every die edge protection by molding compound and the singulation was demonstrated. The die gap was able to be controlled from 0.5 mm to 3.5 mm. In the case of 1.5 mm die gap, the standard deviation was about 0.05 mm. It was also indicated that the film could be applied for 1 mm 1 mm, 5 mm 5 mm and 10 mm 10 mm size dice. Keywords Wafer level package; FO-WLP; high productivity; effective use of wafer conventional epoxy compound material. Finally, the molding wafer is singulated to the packages by dicing. The process does not need the die re-placement and the wasteful wide curf. The proposed film and the process can also be applied to a die first type FO-WLP fabrication [4-6]. To make a molded wafer the current typical process has die-replacement for die gap widening and molding. Re-distribution layers are formed on the molded wafer. Expanded die gap area can be used for fan out wiring. The die-replacement needs die mounter and takes a long time. Elimination of the die re-placement step can change the FO-WLP fabrication process simpler [7]. 1. Introduction Wafer level package (WLP) application is expanding recently due to the advantages of small form factor, thermal dissipation and electrical performance by the short circuit length and so on. There are two types of WLP. One is fan in (FI-WLP) and the other is fan out (FO-WLP) type. WLP is a substrate-less structure, which makes the package thinner. The feature is well fit to mobile devices which require small, thin and light bodies. FI-WLP is fabricated by building up redistribution dielectric and metal layer on device wafer and attaching ball, and then it is diced to singulated packages. Device semiconductor die side is exposed in such a FI-WLP. Semiconductor materials, which are silicon and compound material, are intrinsically fragile material. Therefore, side wall protection by molding compound has been used to prevent the crack. FI-WLP fabrication process needs wide die gap to squeeze molding compound and to dice with blade, leaving the molding compound on the die side wall for the protection. Two type processes are known to obtain the wide die gap. One is die re-placement approach and the other is that dice are fabricated with wide gap on the wafer in semiconductor manufacturing process [1-3]. The former process needs additional step of die re-placement. On the other hand non device area occupies larger in the wafer by the latter process, which may decrease the numbers of device per wafer. The typical process is as follows: the first step of wide blade dicing, the second step of resin molding and the third step of narrow blade dicing at the center of the dicing curf derived from the first step. The process needs a wide curf, which cannot be used as the device area. To get the greater productivity and enhance the usage of the device area in the wafer, the expandable film and the novel process have been developed (Fig. 1). After the blade dicing process, the curf of diced wafer is expanded. Then it is over-molded with Expanding process (Before expanding) Molding process Expanding process (After expanding) Dicing process Figure 1. Concept of the fabrication process of 5 sides protection with expanding film. 2. Experiments 2-1. Fabrication process The fabrication process of the 5 sides protection was composed of 7 serial steps as illustrated in Fig. 2. The expanding film with diced-wafer was put on the expander. And then the film was expanded. After that the film was fixed to the grip ring and the film was cut out along the outer rim of the ring. After the singulated dice were transferred to the carrier with keeping the expanded die gap, the grip ring was removed. Then the expanding film was removed from the carrier. After the over-molding, the molded wafer was 2377-5726/17 $31.00 2017 IEEE DOI 10.1109/ECTC.2017.293 331

singulated by dicing and 5 sides protected packages were obtained. Setting on the expander Film expanding Figure 3. Film expansion by thrust-up type expander. 2-4. Die gap measurement The distance between the dice after expanding was measured by a microscope. As shown in Fig. 4, the measurements were carried out at the center and the four outer areas. The film may have an oriented expanding character originated from the preparation process. The die gaps were measured both in the machine (MD) and the transvers directions (TD) in the 5 areas. The average of these distances was hereinafter referred to as die gap. Film fixing and cutting Die transfer and grip ring remove Expanding film remove Over-molding Figure 4. Measured areas of the wafer and the points of each die gap. 2-5. Die transfer condition The dice on the film were transferred to the carrier with the conditions of the temperature of 60 C and the pressure of 0.5 MPa for 30 s. Molding material dicing Figure 2. Detail fabrication process of 5 sides protected package with the expanding film. 2-2. Wafer and die size specification 8 inch size wafer was used in this experiment. The thickness was 250 m. The wafer was diced into 5 mm 5 mm in size. The curf (die gap before expanding process) was about 50 m. 2-3. Film expanding condition The expander of thrust-up type was used for the expanding process (Fig. 3). The thrust-up height was set to 100 mm. The speed was 5 mm/s. The stage temperature was 50 C. 2-6. Film removing condition The film was removed at 25 C after the ultraviolet (UV) light irradiation. The energy density was 300 mj/cm 2. 2-7. Over-molding condition The specimen was over-molded with epoxy compound material at 150 C for 10 min using compression molding equipment. 2-8. Molded wafer dicing The molded material was diced with a 250 m thick blade. The cutting and the blade rotation speeds were 20 mm/s and 30000 rpm, respectively. 332

2-9. Measurement conditions of stress-strain curve Stress-strain measurement was performed at 25 or 50 C at the rate of 5 mm/s. The film thickness was 100 m. C before and after expanding are shown in Fig. 7 (a) and (b), respectively. 2-10. Measurement conditions of peel strength Peel test was done at 25 C with the rate of 5 mm/s. The film thickness and width were 100 m and 25 mm, respectively. Diced wafer Expanded wafer 3. Evaluation of each process 3-1. Expanding process As depicted in Fig. 5, five films (A to E) having different stress-strain curves were prepared. (a) Before expanding (b) After expanding (After dicing) Figure 7. Photographs of the dice on the expanding film before and after expanding. Each die gap was almost regularly widened as shown in Fig. 7. Film C and D showed the different die gap after expansion, while the stress-strain curves measured at 50 C of them showed no significant difference, which was shown in Fig. 5. The stress-strain curves of film C and D at 25 and 50 C are seen in Fig. 8. The schematic diagram of temperature condition during the expanding process is illustrated in Fig. 9. Figure 5. Stress-strain curves at 50 C. Film expanding test was performed as the next step. All the film thicknesses were 100 m. The obtained die gap and the standard deviation ( ) are described in Fig. 6. Figure 8. Stress-strain curves. Figure 6. Die gap and standard deviation. The die gap of film A and B couldn t be measured because the film was detached from the fixing jig of the expander during expanding. The large tensile stress might cause the trouble. On the other hand, films C, D and E demonstrated successful expansions. The die gap becomes smaller as the stress becomes smaller. Film C having the largest die gap was selected to the further evaluation. The photographs of the film Figure 9. Film temperature during expanding process. 333

The gaps in the edge area were wider than those in the center area. Since the expanded area of the film was not heated, which was exposed to room temperature of about 25 o C, the temperature was no more 50 o C. Fig. 9 describes the situation. The temperature dependence of the strain stress curve of film C indicates that the edge area with lower temperature should have much stronger tensile strength than that of the area still on the heating stage. It is thought that the center area of the film was expanded larger. In contrast, film D should have comparable tensile strengths in both areas. They were expanded evenly so that the narrower gap between the dice was obtained. Furthermore, front and back side of the film before and after expanding were observed in detail. As shown in Fig. 10, neither film crack nor delamination was observed. After the expanding process, film C was laminated onto a carrier. The carrier and the dice were separated from the film after UV irradiation. Some dice were delaminated from the carrier during the film removing process as the photograph in Fig. 11. We tried to decrease the peel strength of the film after UV irradiation while maintaining the value before the irradiation. As described in Fig. 12, we succeeded in decreasing only peel strength after UV irradiation by optimizing the UV curing resin of the film C. Film removing process was also implemented using the improved film C. The photograph in Fig. 13 shows that the dice were successfully transferred to the carrier and separated from the film. Carrier Die Figure 13. Photographs of the dice after transfer to the carrier. (a) Front surface observation (b) Back surface observation Figure 10. Observation after expanding. 3-2. Dice transfer and the film removing process 3-3. Over-molding and following dicing process Over-molding process was performed. The carrier was removed after the molding and then the die gap was measured. The photographs are shown in Fig.14 and the die gap is summarized in Fig.15 [8-9]. Figure 11. Film separation. Molding material Die Figure 14. Photographs of the dice after over-molding. Figure 12. Peel strength of the improved film C. Figure 15 Die gap after each process. 334

The die gap remained almost constant through the processes from the expanding to the molding. The molded wafer was diced in the next step. The Photographs are shown in Fig. 16. Figure 18. Die gap of each die size after expanding process. Comparison of the die gap shown in Fig.18 (a) and (b) indicated that the die gap becomes smaller as the die size becomes smaller. It is thought that increasing the number of dicing line (curf) made the expanding force between dice dispersed. (a) Part A (b) Part B Figure 16. Photographs of the dice after dicing. 4-2. Die gap enlargement We have succeeded in enlarging the die gap up to 3.5 mm by increasing the film thickness and reducing the expanding rate. Fig. 19 shows the photographs of the expanded samples with die size of 5 mm 5 mm. The molding material dicing was successfully performed both in part A and B. Mold thicknesses of die edges in part A were relatively uniform comparing with those in part B. 4. Application to other packages 4-1. Change in die size The improved film C was evaluated with the dice of 2 different sizes. Those were 1 mm 1 mm and 10 mm 10 mm. The wafer size and the thickness were the same as the previous evaluation. Fig. 17 (a) and (b) are photographs of the samples after expanding and Fig. 18 summarizes the die gap. (a) Die size 1 mm 1 mm (b) Die size 10 mm 10 mm Figure 17. Photographs after expanding process. Grip ring Figure 19. Photographs of the dice after expanding. As demonstrated results above, the developed film and proposed process can be applicable for various die sizes. 5. Conclusions The novel expanding film and process which can remove time-consuming die-replacement process of WLP were developed. The stress-strain curve of the film was optimized so that the die gap becomes large. Moreover, the die gap was able to be controlled from 0.5 mm to 3.5 mm. In the case of 1.5 mm die gap after expansion, the standard deviation was about 0.05 mm. Furthermore, the film was applicable to die sizes 1 mm 1 mm, 5 mm 5 mm and 10 mm 10 mm. Acknowledgment The authors would like to thank OHMIYA IND. Co., Ltd. for the useful technical discussion and the equipment support in expanding process. 335

References 1. T. Tang, A. Lan, J. Wu, J. Huang, J. Tsai, J. Li, A. Ho, J. Chang and W. H. Lin, Challenges of Ultra-thin 5 Sides Molded WLCSP, Proceedings of 2016 Electronic Components & Technology Conference, pp. 1067-1071. 2. K. Chen, K. Lim, K. Seah, Y. Lin and S. W. Yoon, Innovative Wafer Level Package Manufacturing with FlexLine, Proceedings of 2014 IEEE 16th Electronics Packaging Technology Conference, pp. 11-15. 3. H. Gee, E. Estiller and U. Sharma, Wafer Level Process Formation of a Polymer Isolated Chip Scale Package, Proceedings of the International Wafer-Level Packaging Conference 2016. 4. C. F. Tseng, C. S. Liu, C. H. Wu and D. Yu, InFO (Wafer Level Integrated Fan-Out) Technology, Proceedings of 2016 Electronic Components & Technology Conference, pp.1-6. 5. S. Chen, S. Wang, J. Hunt, W. Chen, L. Liang, G. Kao and A. Peng, A Comparative study of a Fan Out Packaged Product : Chip First and Chip Last, Proceedings of 2016 Electronic Components & Technology Conference, pp.1483-1488. 6. S. G. Chow, Y. Lin, E. Ouyang, B. Ahn, A Finite Element Analysis of Board Level Temperature Cycling Reliability of Embedded Wafer Level BGA (ewlb) Package, Proceedings of 2012 Electronic Components & Technology Conference, pp.1448-1454. 7. C. Palesko and A. Lujan, Cost Analysis of Die Assembly for 2.5D and 3D Packaging, Proceedings of the International Wafer-Level Packaging Conference 2016. 8. T. Hasegawa, H. Abe and T. Ikeuchi, Wafer Level Compression Molding Compounds, Proceedings of 2012 Electronic Components & Technology Conference, pp.1400-1405. 9. C. Bishop, B. Rogers, C.Scanlan, T. Olson, Adaptive Patterning Design Methodologies Proceedings of 2016 Electronic Components and Technology Conference, pp. 7-12. 336