Space Vector Modulation of Multi-Level and Multi-Module Converters for High Power Applications. Maryam Saeedifard

Space Vector Modulation of Multi-Level and Multi-Module Converters for High Power Applications by Maryam Saeedifard A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto Copyright c 28 by Maryam Saeedifard

Abstract Space Vector Modulation of Multi-Level and Multi-Module Converters for High Power Applications Maryam Saeedifard Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto 28 This thesis presents and investigates Space Vector Modulation (SVM) switching strategies for (i) a multi-level Diode-Clamped Converter (DCC) and (ii) a multi-module Voltage-Sourced Converter (VSC) system in which each module is a conventional twolevel VSC. Although the SVM strategies are general and applicable for n-level DCC and n-module VSC systems, this text only concentrates on five-level DCC and four-module VSC systems. For a five-level DCC, a computationally efficient SVM algorithm is proposed. The algorithm, that is based on a classifier Neural Network (NN), reduces the computational time for the SVM realization. Therefore, adequate saving of processor execution time, in each sampling period of SVM, is provided to carry out other functions, e.g. the calculations required for DC-capacitor voltage balancing task. The thesis also proposes a DC-capacitor voltage balancing strategy to counteract the voltage drift phenomenon of (i) a passive-front-end five-level DCC, and (ii) a back-to-back connected five-level DCC system. The proposed balancing strategy, that is based on augmenting the proposed SVM algorithm, takes advantage of the redundant switching states to minimize a quadratic cost function associated with voltage deviations of the DC-capacitors. The salient features of the proposed balancing strategy are (i) online calculation of SVM to select the best switching states, (ii) minimization of switching frequency, (iii) minimization of the THD content of the AC-side voltage, and (iv) no requirement for additional power circuitry. ii

For a four-module VSC system a sequential sampling SVM strategy is proposed. The proposed strategy (i) provides harmonic cancellation/minimization at the net AC-side voltage of the multi-module VSC system, and (ii) offers a low switching frequency for each VSC module. Technical feasibility of the proposed SVM strategies for a five-level DCC and a fourmodule VSC system, as a STATCOM and a back-to-back HVDC system, are investigated and presented. The studies are conducted in the time-domain, in the PSCAD/EMTDC software environment. iii

Dedication In the memory of my dear father and Dedicated to my loving mother iv

Acknowledgements I would like to express my sincere gratitude to my supervisor, Professor Reza Iravani, for his invaluable supervision, encouragement, and financial support throughout my Ph.D. studies. Furthermore, I should acknowledge great efforts of the entire Ph.D. exam committee: Professor Richard Bonert, Professor Peter Lehn, and Professor Bin Wu for their review of this thesis, discussions, and constructive comments. I would also like to recognize the financial support of the University of Toronto and Ontario Graduate Scholarships. I would like to extend my appreciation to my friends in Toronto with whom I shared great memories. I cannot end without thanking my lovely family, on whose constant encouragement, support, and love, I have relied throughout my life. Without their intense care and compassionate support, I would have never been able to come this far. v

Contents Introduction. Statement of the Problem...........................2 Thesis Objectives............................... 3.3 Background.................................. 4.3. Multi-Level DCC........................... 4.3.2 Multi-Module VSC.......................... 6.4 Thesis Outline................................. 7 2 SVM Switching Strategy for a Multi-Level DCC 9 2. Introduction.................................. 9 2.2 Principles of Operation of a Multi-Level DCC............... 2.3 SVM for a n-level DCC............................ 2.3. Space Vector Plane, Sectors, and Switching Vectors........ 2.3.2 Conventional SVM Algorithm.................... 3 2.4 Proposed SVM Algorithm.......................... 5 2.4. Fast SVM Algorithm Based on Kohonen s Competitive NN.... 6 2.4.2 Determination of Reference Vector Location............ 9 2.4.3 Duty-Cycle Calculations....................... 2 2.4.4 Determination of Switching States Corresponding to Switching Vectors................................... 22 2.4.5 Study Results............................. 24 2.5 Summary and Conclusions.......................... 25 3 DC-Capacitor Voltage Control of a Five-Level DCC 32 3. Introduction.................................. 32 3.2 Five-Level DCC................................ 33 vi

3.2. Fundamentals of Operation..................... 33 3.2.2 Theoretical Limits to Capacitors Voltage Balancing........ 34 3.2.3 DC-Capacitor Voltage Drift Phenomenon.............. 35 3.3 SVM For a Five-Level DCC......................... 4 3.3. Space Vector Plane, Sectors, and Switching Vectors........ 4 3.3.2 Effects of Different Switching States on DC-Intermediate Branch Currents................................ 43 3.4 DC-capacitor Voltages Balancing Based on Minimum Energy Property. 49 3.4. Space Vector Sequence and Switching Frequency.......... 53 3.5 Study Results................................. 55 3.5. Limits of Operation.......................... 56 3.5.2 Capacitor Voltages Balancing Under Balanced Linear Load Conditions.................................. 57 3.5.3 Capacitor Voltages Balancing Under Unbalanced or Distorted ACside Conditions............................ 58 3.6 Summary and Conclusions.......................... 59 4 Modeling and Control of a Five-Level DCC-based STATCOM 64 4. Introduction.................................. 64 4.2 System Structure............................... 65 4.3 System Model................................. 66 4.3. System Model in abc Frame..................... 66 4.3.2 System Model in dq Frame...................... 68 4.4 System Controls................................ 69 4.4. AC-Side Current Control....................... 69 4.4.2 Net DC Voltage Controller...................... 7 4.4.3 PCC Voltage Controller....................... 72 4.5 Case Studies.................................. 72 4.5. Case-: Load and STATCOM Energization............. 74 4.5.2 Case-2: Reactive Power Control................... 75 4.5.3 Case-3: Load Voltage Control.................... 76 4.5.4 Case-4: Load Energization Under Unbalanced Source Conditions. 76 4.5.5 Case-5: Three-Phase Fault...................... 77 4.6 Summary and Conclusions.......................... 78 vii

5 Five-Level DCC-Based Back-to-Back HVDC System 85 5. Introduction.................................. 85 5.2 Five-Level DCC-Based HVDC System Structure.............. 86 5.3 Voltage Balancing of the DCC System................... 87 5.3. Space Vector Sequence and Switching Frequency.......... 9 5.4 Mathematical Model of the HVDC System................. 92 5.4. System Model in abc Frame..................... 92 5.4.2 Expression of abc Model in dq-frame................ 94 5.5 AC-Side Current Control of DCC System.................. 95 5.6 DC-Bus Voltage Control........................... 96 5.7 Performance Evaluation........................... 98 5.7. Study System............................. 98 5.7.2 Study Results............................. 98 5.8 Summary and Conclusions.......................... 3 6 A SVM-Based Multi-Module HVDC Converter System 9 6. Introduction.................................. 9 6.2 Multi-Module HVDC System Structure................... 6.3 Proposed SVM Switching Strategy..................... 6.3. Sequential Sample and Hold Voltage Synthesis........... 2 6.3.2 Sequential Sampling SVM Technique................ 4 6.3.3 SVM Switching Pattern....................... 5 6.4 System Model................................. 22 6.4. System Model in abc Frame..................... 22 6.4.2 Transformation of abc Model to dq-frame............. 24 6.5 AC-Side Current Control of VSC Systems................. 25 6.6 DC-Bus Voltage Control........................... 27 6.7 Performance Evaluation........................... 29 6.7. Study System............................. 29 6.7.2 Study Results............................. 29 6.8 Summary and Conclusions.......................... 33 7 Conclusions 39 7. Summary................................... 39 viii

7.2 Conclusions.................................. 4 7.3 Thesis Contributions............................. 42 7.4 Future Work.................................. 43 A Harmonic Analysis of a SVM-Based N-Module VSC 44 A. Harmonic Analysis of one VSC module................... 44 A.2 Harmonic Analysis of a N-Module VSC................... 46 B Analysis of DC-Capacitor Voltage Drift Phenomenon of a SPWM- Switched, Back-to-Back Connected Five-Level DCC System 48 ix

List of Figures 2. Circuit diagram of a three-phase n-level DCC............... 2.2 A schematic representation of the n-level DCC of Fig. 2. based on n-pole fictitious switches............................... 2 2.3 Representation of space voltage vectors of a n-level DCC in αβ plane.. 3 2.4 First sector corresponding to the space voltage vectors of an n-level DCC 4 2.5 Schematic diagram of the classification algorithm............. 6 2.6 Representation of the reference vector and switching vectors of a 2-level converter in the αβ plane: (a) all sectors, (b) the winners of the competition 7 2.7 Space vector representation of an n-level DCC in the first sector..... 2 2.8 Schematic diagram of the classification algorithm for a multi-level DCC. 24 2.9 AC-side voltage waveform of a 3-level DCC; m =.8, f sw = 288Hz.... 27 2. AC-side voltage waveform of a 3-level DCC; m =.6, f sw = 288Hz.... 27 2. AC-side voltage waveform of a 3-level DCC; m =.4, f sw = 288Hz.... 28 2.2 AC-side voltage waveform of a 4-level DCC; m =.8, f sw = 288Hz.... 29 2.3 AC-side voltage waveform of a 4-level DCC; m =.6, f sw = 288Hz.... 29 2.4 AC-side voltage waveform of a 4-level DCC; m =.4, f sw = 288Hz.... 3 2.5 AC-side voltage waveform of a 5-level DCC; m =.8, f sw = 288Hz.... 3 2.6 AC-side voltage waveform of a 5-level DCC; m =.6, f sw = 288Hz.... 3 2.7 AC-side voltage waveform of a 5-level DCC; m =.4, f sw = 288Hz.... 3 3. Schematic representation of passive-front-end five-level DCC....... 33 3.2 SPWM waveforms of a five-level DCC.................... 35 3.3 Voltage balancing region of a passive-front-end n-level DCC (n ).. 36 3.4 Schematic representation of the five-level DCC system of Fig. 3. based on five-pole fictitious switches........................ 36 3.5 An equivalent circuit of the five-level DCC of Fig. 3.4........... 38 x

3.6 Switching functions of phase-a of a SPWM-switched five-level DCC solid lines: exact switching functions dashed lines: continuous mathematical switching functions........ 39 3.7 Space voltage vectors for a five-level DCC................. 42 3.8 Adjacent switching states of V ref in odd sectors.............. 45 3.9 Adjacent switching states of V ref in even sectors.............. 46 3. Mapping sectors II to VI to sector I such that shaded areas overlap... 47 3. Schematic diagram of the balancing strategy based on the augmented SVM switching strategy............................... 54 3.2 Schematic representation of the system Fig. 3. including AC-side current sources..................................... 55 3.3 Limits of the proposed SVM-based balancing method for a four-level and a five-level passive-front-end DCCs A: operating point corresponding to Fig. 3.4 B: operating point corresponding to Fig. 3.5 C: operating point corresponding to Fig. 3.6............... 57 3.4 Converter waveforms for operating condition of P F = and m =.7: (a) AC-side voltage, (b) AC-side currents, and (c) DC-capacitor voltages.. 6 3.5 DCC waveforms for operating condition of P F = and m =.5: (a) AC-side voltage, (b) AC-side currents, and (c) DC-capacitor voltages.. 62 3.6 DCC waveforms under balanced loading condition of P F =.35 and m =.9: (a) AC-side voltage, (b) three-phase AC-side currents, and (c) DCcapacitor voltages.............................. 62 3.7 DCC waveforms under unbalanced loading condition of P F =.35 and m =.9: (a) AC-side voltage, (b) three-phase AC-side currents, and (c) DC-capacitor voltages............................ 63 3.8 DCC waveforms under operating condition of P F =.35, m =.9, and distorted AC-side currents: (a) AC-side voltage, (b) three-phase AC-side currents, and (c) DC-capacitor voltages.................. 63 4. Schematic diagram of a five-level DCC-based STATCOM connected to a utility system at the load terminal...................... 65 4.2 An equivalent circuit of the system of Fig. 4. based on the DCC equivalent circuit of Fig. 3.5............................... 66 xi

4.3 Simplified equivalent circuit of Fig. 4.2................... 67 4.4 Block diagram of the proposed current controller for the STATCOM of Fig. 4..................................... 7 4.5 Block diagram of DC-bus voltage controller of the STATCOM of Fig. 4. 72 4.6 Block diagram of the PCC voltage controller of STATCOM of Fig. 4... 72 4.7 A block diagram representation of the system of Fig. 4. including power and control sub-systems........................... 73 4.8 Block diagram of the overall controllers of the STATCOM........ 74 4.9 Dynamic behavior of the system of Fig. 4.7 to load and STATCOM energization: (a) STATCOM current, (b) load current, (c) STATCOM DC voltage, (d) STATCOM line-to-line terminal voltage, (e) load voltage, and (f) DC capacitor voltages........................... 79 4. Dynamic response of the system of Fig. 4.7 to a step change in reactive power command: (a) STATCOM reactive current component, (b) STATCOM DC voltage, (c) reactive current component of utility system current, (d,e) load and STATCOM current, (f) magnitude of load voltage, (g) STAT- COM terminal voltage and (h) capacitor voltages............. 8 4. Control of load voltage in the system of Fig. 4.7: (a) load current, (b) magnitude of load voltage, (c,d) STATCOM reactive and active current components, (e) utility system reactive current components, (f) capacitor voltages.. 8 4.2 Control of load voltage in the system of Fig. 4.7 when the utility system voltages are unbalanced: (a,b) three phase voltages of the utility system and load, (c) load current, (d) magnitude of load voltage (e,f) STATCOM and utility system reactive current components, (g) DC capacitor voltages 82 4.3 Transient response of the system of Fig. 4.7 to a three-phase fault: (a) STATCOM current, (b) load voltage magnitude, (c) STATCOM DC voltage, (d,e) real and reactive current components of STATCOM, and (f,g) real and reactive current components of the utility system......................... 83 4.4 Trajectory of the STATCOM operating point subsequent to the threephase fault scenario.............................. 84 5. Schematic diagram of a five-level DCC-based HVDC converter system.. 86 5.2 An equivalent circuit of the HVDC system of Fig. 5. based on the DCC equivalent circuit of Fig. 3.5......................... 87 xii

5.3 Block diagram of DC-link balancing strategy for the converter system of Fig. 5..................................... 9 5.4 Simplified equivalent circuit of Fig. 5.2................... 92 5.5 Block diagram of the decoupled dq-frame current controllers....... 96 5.6 Dynamic response of the system of Fig. 5. to a step change in the DC voltage reference when P = P 2 =.45 pu: (a) DC-link voltage, (b,c) real current components of AC System- and AC System-2, (d,e) real power components of AC System- and AC System-2, and (f) DC-capacitor voltages...................................... 5 5.7 Dynamic response of the system of Fig. 5. to step changes in real and reactive power commands: (a,b) real and reactive current components of AC System-, (c,d) real and reactive power components of AC System-, (e,f) real and reactive current components of AC System-2, (g,h) real and reactive power components of AC System-2, (i) net DC-link voltage, and (k) DC-capacitor voltages.......................... 6 5.8 Dynamic response of the system of Fig. 5. to a real power reversal demand: (a,b) real components of AC System- current and power, (c,d) real components of AC System-2 current and power, (e,f) recative power components of AC System- and AC System-2, (g,h) phase-a currents of AC System- and AC System-2, (i,j) modulation indices of DCC- and DCC-2, (k) net DC-link voltage, and (l) DC-capacitor voltages...... 7 5.9 Dynamic response of the system of Fig. 5. to step changes in real and reactive power demands where the HVDC system interfaces a 5 Hz system to a 6 Hz system: (a,b) real and reactive components of AC System- currents, (c,d) real and reactive power components of AC System-, (e,f) real and reactive components of AC System-2 currents, (g,h) real and reactive power components of AC System-2, (i,j) phase-a currents of AC System- and AC System-2, (k) net DC-link voltage, and (l) DC-capacitor voltages.................................... 8 6. Schematic diagram of a four-module back-to-back HVDC converter station 6.2 Schematic diagram of each VSC module.................. 6.3 Principle of sequential sample and hold voltage synthesis technique... 2 xiii

6.4 Output voltages of individual units and the resultant output voltage of the proposed sequential sample and hold voltage synthesizer (ideal case). 3 6.5 Schematic representation of the sequential sampling SVM technique... 4 6.6 Sequential sampling based SVM for the four VSC modules of Fig. 6. in Sector I. As the reference voltage vector rotates in the αβ plane, each modulator samples at a specified instant................... 5 6.7 Proposed space vector switching pattern in Sector I and II........ 6 6.8 AC-side line voltage of one VSC module.................. 7 6.9 Magnitudes and phase angles of harmonics versus sampling angle for m = for the VSC modules of the four-module converter system of Fig. 6.: (a) magnitude, (b) phase angle.......................... 8 6. AC-side line voltage spectra of the four-module VSC system of Fig. 6. versus modulation index m.......................... 2 6. Harmonics as percentages of the fundamental component versus modulation index for VSC modules of the four-module converter system of Fig. 6.2 6.2 AC-side voltage of a four-module VSC that operates based on the proposed sequential sample and hold VSC: (a) line voltage, and (b) line voltage spectrum.................................... 2 6.3 AC-side voltage of an eight-module VSC that operates based on the proposed sequential sample and hold VSC: (a) line voltage, and (b) line voltage spectrum................................. 2 6.4 Block diagram of the decoupled dq-frame current controllers....... 27 6.5 Steady state current and voltage waveforms of the four-module converter system of Fig. 6.: (a,b) line voltage of VSC- terminal and its spectrum, (c,d) line voltage of top VSC module of VSC- and its spectrum, (e,f) AC System- current and its spectrum, (g) net DC-link voltage, (h) permodule DC-capacitor voltage........................ 35 6.6 Dynamic response of the system of Fig. 6. to step changes in real and reactive power demands: (a,b) real and reactive components of AC System-2 currents, (c,d) real and reactive power components of AC System-2, (e) net DC-link voltage, (f,g) real and reactive components of AC System- currents, and (h,k) real and reactive power components of AC System-. 36 xiv

6.7 Dynamic response of the system of Fig. 6. to a real power reversal demand: (a,b) real components of AC System- current and power, (c,d) real components of AC System-2 current and power, (e,f) reactive current components of AC System- and AC System-2, and (g,h) phase-a currents of AC System- and AC System-2...................... 37 6.8 Transient response of the system of Fig. 6. to a temporary single-phase to ground fault: (a) AC System-2 phase-a current, (b) DC-link voltage, (c,d) real and reactive components of AC System-2 currents, and (e,f) real and reactive components of AC System- currents............. 38 A. Modulation function of SVM-based VSC module.............. 45 xv

List of Tables 2. Switching states of a n-level DCC...................... 2.2 Switching states and corresponding space voltage vectors......... 8 2.3 Relationship between switching states in sectors I to VI.......... 23 3. Switching states of a five-level DCC..................... 33 3.2 Relationship between the DC-intermediate branch currents and AC-currents for different switching states in Sector I................... 44 3.3 Interchanging the AC-side currents for switching states in odd-numbered sectors..................................... 45 3.4 Interchanging the AC-side currents for switching states in even-numbered sectors..................................... 49 3.5 Interchanging the AC-side currents for switching states in sectors I to VI 49 3.6 Interchanging the switching states in sectors I to VI............ 53 3.7 Parameters of the system of Fig. 3.2.................... 56 4. Parameters of the study system of Fig. 4.7................. 75 5. Parameters of the study system of Fig. 5.................. 99 6. Parameters of the study system of Fig. 6.................. 3 xvi

List of Abbreviations VSC: IGBT: IGCT: HVDC: DCC: PWM: SPWM: SVM: NN: THD: STATCOM: PD: POD: APOD: SISO: PI: dq: PCC: PLL: Voltage-Sourced Converter Insulated Gate Bipolar Transistor Integrated Gate Commutated Thyristor High Voltage Direct Current Diode-Clamped Converter Pulse Width Modulation Sinusoidal Pulse Width Modulation Space Vector Modulation Neural Network Total Harmonic Distortion STATic COMpensator Phase Disposition Phase Opposition Disposition Alternative Phase Opposition Disposition Single-Input Single-Output Proportional-Integral direct-quadrature Point of Common Coupling Phase-Locked Loop xvii

List of Symbols S: switching function d: duty cycle e: error signal f sw : switching frequency f sampling : sampling frequency i: current s: Laplace transform variable t: continuous time v: voltage θ: phase angle ω: frequency xviii

Chapter Introduction. Statement of the Problem The two-level, forced-commutated, Voltage-Sourced Converter (VSC) is the main building block for AC-DC and AC-DC-AC converter systems for low- and medium-power applications. Recent developments in semiconductor technology and commercial availability of high power switches, e.g. Insulated Gate Bipolar Transistor (IGBT) and Integrated Gate Commutated Thyristor (IGCT), have resulted in a widespread acceptance of the two-level VSC for high-power applications as well. However, for some applications, e.g. HVDC converters and FACTS controllers, the voltage ratings of power semiconductor devices still are not sufficient to meet the required voltage levels by one single-module of a two-level VSC. To meet high voltage/power levels, multi-level and multi-module VSC configurations are the options [] [3]. The main features of these two configurations, as compared with the two-level VSC, are their capabilities to reduce (i) harmonic distortion of the AC-side waveforms, (ii) dv/dt switching stresses, and (iii) switching losses. In the technical literature, three different types of multi-level topologies, i.e. the Diode-Clamped Converter (DCC), the capacitor-clamped converter, and the cascaded H-bridge converter with separated DC sources have been proposed [4] [7]. Applications of the capacitor-clamped converter are limited since the clamping capacitors result in a bulky and expensive converter system. The cascaded H-bridge converter needs DC sources and is more attractive for applications that include isolated DC sources, i.e. fuel cells and photovoltaic energy sources. The multi-level DCC is the most promising topology among the three, particularly for electric power transmission and distribution applications. The multi-level DCC does not have the limitations associated with the

Chapter. Introduction 2 other two topologies [4]. However, the DC-side capacitor voltage drift phenomenon of an n-level DCC, particularly for n > 3, is a challenging task under both steady-state and transient conditions. The existing Pulse-Width Modulation (PWM) strategies for a multi-level DCC are based on (i) selective harmonic elimination techniques [8] [], (ii) Sinusoidal PWM (SPWM) techniques [4], and (iii) Space Vector Modulation (SVM) techniques. Among the PWM strategies, the SVM techniques are the preferred switching strategies for a multi-level DCC, particularly in view of their inherent properties for digital implementation. However, in the context of a multi-level DCC, the existing SVM strategies do not offer (i) computationally efficient algorithms for real-time implementation, (ii) capabilities to counteract DC-capacitor voltage drift phenomenon, and (iii) the minimum switching frequency [] [4]. The first objective of this thesis is to propose and develop a computationally efficient SVM strategy that (i) enables mitigation of the DC-capacitor voltage drift phenomenon, and also (ii) provides minimum DCC switching frequency (losses). Multi-module VSC configurations, from the viewpoint of power circuitry and switching technique, are classified into two major categories [3], i.e. the multi-pulse VSC system [3] and PWM-based multi-module VSC system [5]. A multi-pulse VSC offers (i) higher degree of utilization of DC-side voltage, (ii) minimum switching losses, and (iii) low order harmonic elimination capability [6]. The drawbacks of a multi-pulse VSC are (i) the need for complicated phase-shifting transformer windings, and (ii) lack of modularity since the transformers are not identical [3]. A PWM-based multi-module VSC can overcome the limitations of a multi-pulse VSC. In this thesis we only consider PWMbased multi-module VSC systems, and hereinafter we refer to them as multi-module VSC systems. In a multi-module VSC system, multiples of identical n-level VSC modules are connected in series [5],[7],[8]. The existing multi-module VSC systems are based on either two-level VSC units [5] or n-level (n 3) DCC units [],[7],[8]. The AC-side voltages of the VSC modules are added up through identical transformers to generate a multi-level AC-side voltage waveform. A multi-module VSC system offers (i) full modular design and scalability, and (ii) equal loss of semiconductor switches [3]. To minimize losses of a multi-module VSC system, the switching frequency of the VSC modules has to be at the lowest possible value. However, low switching frequency generates low-order harmonics at the AC-side voltages of the individual modules. To avoid low-order harmonic filtering

Chapter. Introduction 3 and improve the AC-side voltage waveform of a multi-module VSC system, harmonic cancellation/minimization strategies are required. The existing PWM strategies that provide harmonic cancellation/minimization for a multi-module VSC system are based on the phase shifted carrier SPWM techniques [5]. Although SVM switching strategies are conceptually the preferred PWM strategies for a VSC module, they have neither been used nor considered for multi-module VSC systems since the existing SVM strategies cannot offer harmonic cancellation/minimization. A SVM strategy with a low switching frequency and without any harmonic cancellation/minimization capability deteriorates the AC-side voltage of a multi-module VSC system and necessitates low-order filtering. A SVM switching strategy that (i) provides a low switching frequency and, (ii) provides harmonic cancellation/minimization for a multi-module VSC system has not been reported in the technical literature. This thesis also provides a SVM switching strategy, for a multi-module VSC system composed of two-level VSC units, with the capability to cancel/minimize low-order harmonics based on a low switching frequency..2 Thesis Objectives The main objectives of this thesis are:. To propose a SVM-based DC-capacitor voltage balancing strategy that mitigates/ prevents the capacitor voltage drift phenomenon of (i) a passive-front-end DCC, i.e. a DCC that is supplied by a single DC source, and (ii) a back-to-back connected DCC system, without the need for external power circuitry. In addition, since adequate saving of processor execution time, in each sampling period of the SVM is required to perform DC-capacitor voltage balancing task, a computationally efficient SVM strategy should also be developed. 2. To propose a SVM strategy for a multi-module VSC system to (i) maximize the fundamental component of AC-side voltage, (ii) minimize harmonic distortions, and (iii) minimize the switching frequency and consequently the switching losses. Technical feasibilities of the proposed SVM strategies for a five-level DCC and a fourmodule VSC system are investigated and validated in the context of STATCOM and back-to-back HVDC system applications.

Chapter. Introduction 4.3 Background.3. Multi-Level DCC The three-level DCC, also known as Neutral-Point Clamped (NPC) converter [9], has been extensively investigated as an alternative to the conventional two-level VSC, for industrial, transmission and distribution systems applications. Modeling, control and analysis of the three-level DCC for such applications have been reported in the technical literatures [], [2] [29]. Furthermore, the voltage drift phenomenon of DC-capacitors of a three-level DCC has been extensively investigated, and correspondingly various remedial measures proposed/implemented to resolve the issue [2] [28]. For high-power applications, a five-level DCC (or an n-level, n > 5) is more attractive due to its capability to operate at a higher voltage level and to provide waveforms with lower Total Harmonic Distortion (THD) contents. In addition, the five-level DCC obviates/minimizes the interface transformer. This unique feature reduces the overall system volume and footprint which is of importance for some applications. Despite merits of a five-level DCC for high power/voltage applications, its capacitor voltage drift phenomenon has been neither comprehensively formulated/analyzed nor the corresponding remedial measures fully developed. Unlike a three-level DCC, the DC capacitor voltage drift phenomenon of a five-level DCC is application (load) dependent and, thus, its mitigation/prevention not a straightforward task [3] [32]. When the DCC exchanges non-zero real power, the average values of the DC capacitor currents are not zero values and lead to the voltage drift of the DC capacitors. The voltage drift phenomenon deteriorates the AC-side voltage waveforms and consequently results in the operational failure of the DCC, if not counteracted. In the technical literature, the DC-capacitor voltage balancing of a n-level DCC (n > 3) has been proposed based on the following approaches: The first approach proposes separate DC sources, one per capacitor, to maintain the capacitor voltages [33]. The DC sources are usually provided by transformers through diode bridge rectifiers. Such a supply system is large, heavy, inefficient, expensive and potentially with adverse impacts on the power quality of the prime power supply. The second approach is based on an auxiliary converter to inject current components in the DC-side intermediate branches of the DCC to balance the DC-side

Chapter. Introduction 5 voltages [34] [44]. The main shortcoming of this approach is the need for additional power hardware which adds to the system cost and complexity, particularly at high voltage/power levels. The third approach proposes modification of the DCC switching pattern, according to a control strategy, to balance and maintain the DC-capacitor voltages [4], [45], [46]. Although this approach requires a more elaborate switching strategy/algorithm as compared with the previous methods, it provides an economically viable approach to address the main technical issue of the DCC. However, the existing approach for a five-level DCC is based on off-line calculations that need look-up tables and practically may not be achievable or enforced. In this thesis, we propose an on-line strategy, based on the modification of the DCC switching pattern, to equalize the DC-capacitor voltages of a five-level DCC. As compared with the multi-level PWM strategies [], [47], the SVM methods provide flexibility to select and optimize switching patterns to (i) minimize harmonics, (ii) modify the switching pattern to carry out DC-capacitor voltage balancing task with no requirement for additional power circuitry, and (iii) minimize switching frequency for high power applications. However, real-time implementation of the conventional SVM strategies is faced with time limits due to the calculation overhead time. Therefore, fast algorithms are required to overcome complexity of calculations. A fast SVM algorithm can save the processor execution time to perform the required calculations of DC-capacitor voltage balancing task. Several SVM algorithms, with low computational burden and simplified calculations, have been proposed and reported in the technical literature [48] [5]. In [49] a new coordinate system is constructed to simplify the calculations. However, the algorithm has not been augmented with a voltage balancing strategy and it is not clear if it is able to carry out the voltage balancing task over a reasonable SVM sampling period. Another modified SVM algorithm for the three-level DCC is proposed in [5]. This algorithm is based on decomposition of the SVM hexagon diagram of a three-level converter into that of a two-level converter. Although, the decomposition method can be extended for higher level DCCs, the computational cost is noticeably increased with the number of levels [5]. A fast Neural Network (NN)-based SVM algorithm, based on a classification technique, for the conventional two-level converter is developed in [52]. The algorithm uses a

Chapter. Introduction 6 simple classifier NN to identify the switching vectors and calculate their duty cycles with no requirement to trigonometric functions. In this thesis, we generalize the NN-based SVM algorithm of [52] for a n-level DCC [53] to significantly reduce the computational overhead time of the SVM algorithm. Furthermore, the generalize algorithm is augmented with an online DC capacitor voltage balancing approach to prevent the voltage drift phenomenon of both a passive-front-end DCC and a back-to-back connected DCC system, with no requirement for additional power circuitry [54]. Applications of a n-level (n > 3) DCC for transformerless STATCOM systems [39], [44], [55] and back-to-back connected DCC units for AC motor drives [34], [38], [56] have been reported in the technical literature. Nevertheless, neither of them provides a comprehensive dynamic model nor a systematic approach to its control design. Furthermore, a n-level DCC has neither been investigated nor studied as a back-to-back HVDC system. In this thesis, the technical feasibility of the proposed SVM switching strategy and the balancing approach is investigated for a five-level DCC in the context of a STATCOM [57] and a back-to-back HVDC system [58]. The investigations also include development of dynamic models of the corresponding study systems and design of controllers..3.2 Multi-Module VSC For very high-power applications, a multi-module VSC system is another alternative, and potentially preferable, to a multi-level DCC [3]. A multi-module VSC is the preferred potential candidate for HVDC system applications [5]. The most interesting aspect of a multi-module HVDC system lies in its modularity and its potential for use in extra highpower applications. Capability of a multi-module VSC to handle high power/voltage indicates that a multi-module HVDC system can be an option to accommodate VSCbased HVDC systems at ultra high power and voltage ratings, e.g. at the voltage level of ±8 kv and power ratings above 3, MW [59] [62]. The AC-side voltage waveform of a multi-module VSC system is a multi-level waveform with a low harmonic dostortion content provided that an appropriate harmonic cancellation/minimization technique is used. A harmonic cancellation/minimization technique introduces appropriate phase shifts among the same-order harmonics of individual modules, while the fundamental voltage components of all modules are kept in phase. Therefore, a set of harmonics are cancelled out/minimized when the module voltages are added up by the interface transformers. Harmonic cancellation/minimization for a

Chapter. Introduction 7 multi-module VSC system is conventionally achieved based on the phase-shifted carrier SPWM techniques [5], [8], [63]. The main feature of this strategy is its simplicity for implementation. Its main drawbacks are that (i) practically it can be used, if the SPWM frequency modulation index is larger than (or at least equal to) 9 which indicates a relatively high switching frequencies and losses, and (ii) the SPWM inherent per-phase switching nature results in redundant switchings that also results in switching losses. The space vector modulation (SVM) is the preferred PWM strategy for low- and medium-power three-phase VSC units, particularly in view of its inherent property for digital implementation. However, the conventional SVM methods require relatively high switching frequency, and thus are not the best option for high power applications. The concept of a low switching frequency SVM strategy for a multi-module converter system has been proposed in [64] and [65]. This thesis develops, applies and investigates the low switching frequency SVM concept of [65] for a multimodule HVDC converter system [66]. The salient features of the proposed SVM strategy are as follows. It can operate at switching frequencies lower than that of a phase-shifted carrier SPWM. It can provide appropriate phase shift among the corresponding harmonics of the VSC modules of a converter for harmonic cancellation/minimization through the use of identical transformers for the VSC modules, and thus eliminates the need for complicated transformer windings and enhances modularity of the HVDC converter structure. It guarantees maximum possible ac-side voltage by keeping the fundamental voltage components of all the VSC modules inphase..4 Thesis Outline The next six chapters of the thesis are organized as follows: Chapter 2 proposes a computationally efficient SVM algorithm, based on a classifier NN. The principle of the classifier NN for the implementation of SVM strategy of a two-level VSC is explained and then, the algorithm is generalized for a n-level DCC. Time-domain simulation results are presented to validate the features of the proposed SVM strategy.

Chapter. Introduction 8 Chapter 3 analyzes and formulates the voltage drift phenomenon of a passivefront-end five-level DCC. Chapter 3 also proposes a SVM-based voltage balancing strategy to counteract the voltage drift phenomenon of a five-level DCC. Capability of the proposed SVM-based balancing strategy to maintain the capacitor voltages equal, is evaluated based on time-domain simulation studies. Chapter 4 investigates a five-level DCC-based STATCOM that operates based on the SVM-swiching strategy of Chapter 2 and the DC-capacitor voltage balancing strategy of Chapter 3. A mathematical model of the STATCOM is developed. Based on the developed model and the voltage balancing strategy of Chapter 3, the AC-side current controllers, the DC-bus voltage controller, and the load voltage controller are designed. Dynamic performance of the STATCOM under different operating conditions, based on time-domain simulation studies, is also presented. Chapter 5 modifies the DC-capacitor voltage balancing strategy of Chapter 3 to balance the DC-capacitor voltages of a back-to-back, five-level DCC-based HVDC system. Chapter 5 also develops a mathematical model for the HVDC system. Based on the developed model, controllers are designed to control power flow and regulate DC-bus voltage. Effectiveness of the voltage balancing strategy under steady-state and dynamic conditions, based on digital time-domain simulation studies is presented. Chapter 6 proposes a SVM-based switching strategy, that is based on a sequential sampling technique, for a multi-module VSC system. The proposed SVM strategy is developed for a four-module VSC-based, back-to-back HVDC system which links two AC systems. Chapter 6 also develops a dynamic model of the HVDC system, and provides a comprehensive evaluation of the proposed SVM strategy for the system. Chapter 7 concludes the thesis and highlights the contributions.

Chapter 2 SVM Switching Strategy for a Multi-Level DCC 2. Introduction This chapter proposes a classification algorithm for real-time implementation of a SVM strategy for a n-level DCC. The proposed algorithm is based on a classifier NN which provides a computationally efficient and a conceptually simple approach without the use of trigonometric calculations or look-up tables to identify (i) location of the tip of a reference voltage vector, (ii) adjacent switching voltage vectors of the reference voltage, and (iii) on-duration time intervals of the switching voltage vectors. The salient feature of the proposed algorithm is that it reduces the computational overhead of the SVM. The algorithm avoids trigonometric calculations for the SVM and the involved calculations are performed by a NN through simple mathematical operations. Therefore, considerable reduction in execution time is achieved to fit the entire processing time within a modulation period for real-time implementation. Thus, adequate time is provided for other tasks, e.g. sensing control variables, performing command calculations, and achieving DC-capacitor voltage balancing. Feasibility of the proposed SVM algorithm is validated based on theoretical analysis and time-domain simulation studies. 9

Chapter 2. SVM Switching Strategy for a Multi-Level DCC V dc n V dc n n C n n 2 C n 2 n 3 S S 2 S n 2 S n V dc S S 2 V dc n V dc n 2 C 2 C S n 2 S n va vb vc Figure 2.: Circuit diagram of a three-phase n-level DCC 2.2 Principles of Operation of a Multi-Level DCC Fig. 2. shows a schematic diagram of a three-phase n-level DCC in which the DC-link consists of capacitors C, C 2,..., C n 2, and C n [4]. Corresponding to the net DC-link voltage of V dc, voltage across each capacitor is ideally V dc /(n ). Each leg of a n-level DCC consists of 2n 2 switches. There are n complimentary switch pairs in each phase. For a complimentary switch pair, e.g. S and S, turning on one of the switches excludes the other from being turned on. Using phase-a as an example, the four complementary pairs are (S, S ), (S 2, S 2 ),..., (S n, S n ). Gating signals S, S 2,..., S n 2, and S n are generated by inverting S, S 2,..., S n 2, and S n respectively. There are n switch combinations to synthesize n-level voltages at the AC-side terminals. To synthesize each voltage level, out of 2n 2 switches in each leg of the DCC of Fig. 2., n contiguous switches must be in the on-state. Considering voltage of node as the reference voltage, the switching combinations to synthesize different voltage levels are summarized in Table 2.. A functional diagram of the DCC of Fig. 2. is shown by Fig. 2.2 in which each phase is interfaced to the DC-link terminals through a fictitious

Chapter 2. SVM Switching Strategy for a Multi-Level DCC Table 2.: Switching states of a n-level DCC Switching S S 2... S n 2 S n S S2... Sn 2 Sn Phase States Voltage I...... V dc II...... (n 2) V dc n.................................... n 2...... 2 V dc n n...... n-pole switch. S ij, i = a, b, c, j =,,..., n is a switching function which denotes the position of the fictitious n-pole switches. S ij is equal to one, if output i is connected to voltage level j, otherwise it is zero. Considering the lower DC-side voltage level as zero, level in Fig. 2.2, the AC-side voltage is defined by a specific number of series capacitor voltages and expressed as n j v i = (S ij V Cp ), i = a, b, c. (2.) j= p= Ideally, when the DC-capacitor voltages are balanced (equal), (2.) is simplified to v i = V n dc (js ij ), i = a, b, c, (2.2) n which denotes a staircase, i.e. an n-level, symmetric waveform. j= 2.3 SVM for a n-level DCC 2.3. Space Vector Plane, Sectors, and Switching Vectors Since there are n distinct switching states for each phase of the converter of Fig. 2.2, the total number of switching state vectors is n 3. Each switching state is represented by (i, j, k) where i, j, k ɛ [,,..., n ], and defines appropriate connection of n-pole switches of the three phases. For example switching state (n, n 2, ) denotes the state in which S a(n )=, S b(n 2)= and S c =.

Chapter 2. SVM Switching Strategy for a Multi-Level DCC 2 V dc n V dc n n C n n 2 C n 2 n 3 S a ( n 2) S a ( n ) S a V dc S b ( n 2) S b ( n ) S b V dc n V dc n 2 C 2 C v a vb S c ( n 2) S c ( n ) S c vc Figure 2.2: A schematic representation of the n-level DCC of Fig. 2. based on n-pole fictitious switches A set of balanced three-phase voltages in abc frame can be transformed into a twodimensional αβ complex frame by the following transformation [67] v /2 /2 v α = v β 3/2 a v 3/2 b, (2.3) where v a, v b, and v c are the three-phase voltages in the abc frame, and v α and v β are the corresponding voltages in the αβ plane. Applying the transformation to the output phase voltages corresponding to the n 3 v c switching states results in a set of switching voltage vectors that form a (n )-layer hexagon centered at the origin of the αβ plane, and n zero voltage vectors located at the origin, Fig. 2.3. The hexagon is divided into six 6 sectors specified by I to VI. Projection of three-phase reference voltages into the αβ plane is a vector called the

Chapter 2. SVM Switching Strategy for a Multi-Level DCC 3 v SectorII Upper limit of linear modulation (m=) SectorIII 4-level SectorI 3-level V ref 2-level v SectorIV SectorVI SectorV Figure 2.3: Representation of space voltage vectors of a n-level DCC in αβ plane reference voltage vector, V ref, with a constant magnitude. V ref rotates counterclockwise with a constant angular frequency of ω as shown in Fig. 2.3. Fig. 2.4 shows sector I of the hexagon. Each sector includes (n ) 2 equilateral triangles. 2.3.2 Conventional SVM Algorithm A SVM is a discrete type of modulation technique in which a sampled reference vector, V ref, is synthesized by the time average of a number of appropriate switching state vectors. When the reference voltage vector, V ref, is located in sector I, at any sampling instant the tip of the voltage vector lies in a triangle formed by the three switching vectors adjacent to it, Fig. 2.3, which constitute the best set of vectors to synthesize the reference voltage

Chapter 2. SVM Switching Strategy for a Multi-Level DCC 4 v 3 ( V, V dc dc ) 2 2 ( n 2) Vdc ( n 2) 3Vdc (, ) 2( n ) 2( n )... I 3Vdc 3 3Vdc (, ) 2( n ) 2( n ) Vdc 3Vdc (, ) ( n ) ( n ) p j,2 Vdc 3Vdc (, ) 2( n ) 2( n ) pj p j, n Vdc 2 n V dc 3 n V dc 4 n V dc... Figure 2.4: First sector corresponding to the space voltage vectors of an n-level DCC n 2 n V dc V dc v vector based on p j d j + p j, d j, + p j,2 d j,2 = V ref T, d j + d j, + d j,2 = T, (2.4a) V ref = V ref e jθ, θ = V ref, (2.4b) m = 2 V ref, 3 V dc (2.4c) where T is the switching period, m is the modulation index, p j, p j, and p j,2 are the three switching vectors adjacent to the reference voltage vector, and d j, d j, and d j,2 are the calculated duty cycles of the switching vectors, respectively. The same applies when the tip of the reference voltage is in the other sectors. Based on Fig. 2.3, a reference voltage magnitude of 3V dc /2 corresponds to the maximum fundamental component of the AC-side voltage obtained in the linear mode, that is m =. In the conventional SVM strategy, the coordinates of each switching vector in the

Chapter 2. SVM Switching Strategy for a Multi-Level DCC 5 cartesian coordinates system, i.e. v α and v β, are calculated by v α = (v a v b + v c ), (2.5a) 2 3 v β = 2 (v b v c ). (2.5b) The coordinates of space voltage vectors are shown in Fig. 2.4. Depending on the position of the reference vector and the triangle in which the tip of the vector is located within, Fig. 2.4, the on-duration time intervals of appropriate switching vectors are calculated from the solution of (2.4). Computational burden to synthesize a reference voltage is mostly associated with trigonometric calculations for (i) identification of the sector and the triangle in which the tip of the reference vector is located within, (ii) selection of appropriate switching voltage vectors, and (iii) calculation of on-duration time intervals of switching voltage vectors. Moreover, as the triangle in which the tip of the reference vector is located within changes, the equations used for the calculations of the on-duration time intervals are changed. Thus, in the conventional SVM strategy, each triangle has its own equations for calculation of the on-duration time intervals. Therefore, as the number of levels of a DCC increases, the computational burden and the complexity of calculations significantly increase. The following section shows that the aforementioned computational requirement can be substantially reduced by means of a general classification technique. 2.4 Proposed SVM Algorithm Reference [52] demonstrates that a SVM algorithm for a conventional two-level converter can be developed by means of a classification algorithm based on Kohonen s competitive NN. Kohonen s competitive NN classifies a group of input vectors into a number of class vectors in its training mode, and assigns a class vector to an input vector in its recalling mode [68]. Since a SVM is a deterministic process and all class vectors are known in advance in the Kohonen s competitive NN, there is no need to train the NN. This salient feature is exploited to develop a fast and simple NN-based SVM algorithm. The following section utilizes the advantage of this feature and presents a real-time computing approach, based on a classification algorithm, to intelligently identify the desired switching voltage vectors and calculate the corresponding on-duration time intervals.