Appliction Note AN367 Differentil Amplifier Author: Dve n Ess Associted Project: Yes Associted Prt Fmily: CY8C9x66, CY8C7x43, CY8C4x3A PSoC Designer ersion: 4. SP3 Abstrct For mny sensing pplictions, desirble feture is to mplify the difference of two inputs. Trditionlly this hs been done with instrumenttion mplifiers. However, for ADCs with differentil inputs, ll tht is required is differentil mplifier. The unique configurtion of the PSoC continuous time nlog blocks llows the implementtion of severl different types of differentil mplifiers. Detils re given showing their construction with Progrmmble Gin Amplifier (PGA User Modules. Introduction Be it mesuring the voltge cross current shunt or mesuring the voltge cross resistive stress guge bridge, it is often necessry to be ble to mplify only the difference of two voltges. Single-ended inputs re defined s being referenced to some ground reference. Amplifiction is esily done with PSoC PGA User Module. The topology is shown in the figure below. For the PGA, this feedbck is string of resistors hving totl resistnce of 6 units. The feedbck tp selects specific ttenution tht sets the gin. The resistnce vlues re defined ( 6 {,,,,3,4,5,6,7,8,9,0,,,3,4,5,6} 3 3 f ( Combining Equtions ( nd ( results in the following: in out Gin 6 (3 f Figure. Progrmmble Gin Amplifier The gin eqution is defined out f i Gin in ( i Differentil Signls equire Differentil Methods Suppose you hve 0.0 ohms current shunt tht sits t nominl voltge of 3 volts. With no current running through it, both sides of the shunt should be 3 volts. This is the common mode vlue for these two signls. Now, if A current is pssed through the shunt, 0 m develops cross it. This is the differentil voltge. These two points re combintion of common nd differentil voltge. Now, 0 m is not much of signl to digitize. Obviously technique must be found to provide gin to only the differentil prt of the signl. Such topology is shown in Figure. 4/4/006 evision A - -
AN367 out (6- out Figure. Differentil Amplifier Ech output is function of the input voltges nd resistnce vlues s shown in the eqution out ( 6 ( out out in (4 errnging this eqution results in the eqution shown out out diff 6 out ( out 6 ( in (5 Figure 4. Differentil Amplifier Prmeter Settings For this exmple, Amp is set to unity gin. Amp is set for gin of four nd the bottom of the resistor string is connected to Amp. Both mplifiers re brought out to individul output buffers. To show the common mode effect, pp sinusoid on ½ dc bis is fed into both nd. The outputs re shown in Figure 5. It is pprent tht the common signl ( psses through t unity gin while the differentil signl ( - gin is 6/. This topology cn be implemented with two PGAs. The block plcement nd prmeter settings re shown below. Figure 5. Outputs for pp ½ dc Figure 3. Block Plcement for Differentil Amplifier Chnnel is out nd Chnnel is out. Since the sme signl is fed into both inputs, by definition the differentil input is zero. Consistent with Eqution (5, out is the sme vlue s its input. out should be this common mode signl plus four times the differentil input. Becuse this differentil input is zero, out equls out. The oscilloscope mth pckge is used to clculte the difference of the two outputs. As expected, it is zero. 4/4/006 evision A - -
AN367 Now chnge the input to be ½ dc. The outputs re shown in Figure 6. Differentil Dynmic nge The input rnge of differentil input is function on the gin, common mode voltge ( cm nd the supply voltge ( dd. It is defined in the eqution 0 < cm < Gin cm indiff < dd dd < Gin cm (6 So given gin of four, supply voltge of 5 nd common mode voltge of 4, the mximum differentil input is ¼. The minimum differentil input is -. Figure 6. Outputs for pp ½ dc, ½ dc Trditionl Differentil Amplifier The trditionl differentil mplifier hs blnced gin. Its topology is shown in Figure 8. For this exmple, the common mode voltge is ½ dc, while the differentil voltge is pp. As expected, out is this ½ dc common mode signl. out is this common mode signl plus four times the differentil input. The clculted difference of these two outputs is - pp. Now swp the inputs so tht i n gets the ½ dc while gets the full pp ½ dc signl. The outputs re shown in Figure 7. out (6- (6- out Figure 8. Trditionl Differentil Amplifier This type of mplifier is used s the first stge for most instrumenttion mplifiers. The outputs re functions of the input voltges nd resistnce vlues s shown in the eqution Figure 7. Outputs for ½ dc, pp ½ dc For this exmple, the common mode voltge is pp ½ dc. The differentil voltge is - pp. As expected, out is this pp ½ dc common mode signl. out is this common mode signl plus four times the differentil input. This clcultes out to pp ½ dc 4*(- pp. It simplifies to: -3 pp ½ dc. The clculted difference of these two outputs is -4 pp. out out ( 6 ( 6 ( ( errnging this eqution results in the eqution shown (7 4/4/006 evision A - 3 -
AN367 out out diff out out 6 6 6 ( (8 For this exmple, Amp nd Amp re set exctly the sme with gin of four nd the lower hlf of the resistor string set to nlog ground. Softwre is required to detch the resistor strings from nlog ground nd connect to ech other. This connection is mde using the exmple It is pprent tht the common signl is the verge of the two input voltges. It psses through t unity gin. The differentil gin is 6/6 with hlf the gined differentil signl dded to the common signl on out nd hlf the gined differentil signl subtrcted from the common signl on out. This topology cn be implemented with two PGAs. The block plcement nd prmeter settings re shown below. Amp_Strt(Amp_HIGHPOWE; Amp_Strt(Amp_HIGHPOWE; Amp_GAIN_C3 0x0; //Diff Amp Connection Amp_GAIN_C3 0x0; //Diff Amp Connection Code. To connect the two resistor strings together requires tht bit in ech block s control register 3 (C3 be set high. To show the common mode effect, pp sinusoid on.5 dc bis is fed into both nd. The outputs re shown in Figure. Figure 9. Block Plcement for Differentil Amplifier Figure. Outputs for pp ½ dc By definition, the common mode signl is the verge of the two signls, or pp ½ dc. The differentil signl is the difference of the two inputs, or zero. Both outputs re just the common mode voltge ( pp ½ dc. The clculted difference of these two outputs is zero. As in the erlier exmple, chnge input to.5 dc. The outputs re shown in Figure. Figure 0. Differentil Amplifier Prmeter Settings 4/4/006 evision A - 4 -
AN367 With different resistor rtios, ech output is function of the input voltges nd resistnce vlues s shown in the eqution out out ( 6 ( 6 ( ( (9 errnging this eqution results in tht shown Figure. Outputs for pp ½ dc, ½ dc By definition, the common mode signl is the verge of the two signls, or ½ pp ½ dc, while the differentil signl is pp. As expected, out is the common mode signl minus hlf of the gined differentil signl. This works out to -½ pp ½ dc. ou is the common mode signl plus hlf of the gined differentil signl. This works out to ½ pp ½ dc. The clculted difference of these two outputs is 4 pp. The differentil dynmic rnge is hrder to clculte. Chnge to single input cuses both chnges in the differentil signl nd the common mode signl. But generlly, the dynmic input rnge is the sme s tht defined by Eqution (6. Trditionl Schmditionl It is not necessry to mke both sme. In fct, interesting results hppen if you intentionlly mke them different. The new topology is shown in Figure 3. out (6- (6- out out diff in 3 in in 3 in 3 out out ( in (0 It is pprent tht the common signl is the weighted verge of the two input voltges. It psses through t unity gin. The differentil gin is 3/( with hlf the gined differentil signl dded to the common signl on out nd hlf the gined differentil signl subtrcted from the common signl on out. With gin of 6/, there were only 8 options for gin rnging from to 48. But know with gin of 3/(, there re 8 possibilities. emoving redundnt solutions leves remining 65 unique gin vlues rnging from to 48. They re displyed in the tble Tble. Unique Gin Settings 48.00 6.40 3.43.34.60 3.00 6.00 3.3.9.5 4.00 5.65 3.0.3.45 9.0 5.33 3.0.8.39 6.00 5.05 3.00.3.33 3.7 4.80.9.09.8.00 4.57.8.04.3 0.67 4.36.74.00.9 9.60 4.7.67.96.4 8.73 4.00.59.9.0 8.00 3.84.53.88.07 7.38 3.69.46.78.03 6.86 3.56.40.68.00 out Figure 3. Throwing Trdition to the Wind 4/4/006 evision A - 5 -
AN367 Appendix A gives tble of gin vlues given nd. Also, the combintions of the two vlues llow for weighting of the common voltge output to select the common mode output tht offers the best differentil dynmic rnge for your specific ppliction. eding the Differentil lue It is necessry to hve n ADC with differentil inputs. The user modules re the ADCINC nd the DELSIG. The plcement nd prmeters to connect n ADCINC to the differentil mplifier re shown in the figures Why Not Use n INSAMP? The INSAMP, when configured with three opmp topology, is trditionl differentil mplifier followed by switch cpcitor block (SC block configured s n A minus-b stge. One problem with A-B stge is tht the mximum llowble column clock is MHz. For the ADCINC nd the DELSIG, the mximum column clock is 8 MHz. The differentil stges exmined here hve no switched cpcitor blocks so there is no such limittion. So the ADC cn operte 8 times fster with differentil mplifier thn with three opmp INSAMP. Also, if SC blocks re scrce resource in our design, then the solution tht uses less of them is preferred. Summry Differentil mplifiers mke it possible to mplify ny differentil signl. Both trditionl nd nontrditionl topologies hve been discussed nd instruction given to construct them. Figure 4. Block Plcement for DiffAmp nd ADCINC Figure 5. ADCINC Prmeter Settings The input connections re obvious. A subtle point is tht the NegInputGin prmeter must be set to for the ADC to hve differentil inputs. About the Author Nme: Title: Bckground: Contct: Dve n Ess Principl Appliction Engineer Cypress Semiconductor An Engineer by trining, poet by temperment, n outlw in Nebrsk, nd one heck of nice guy. Dve is cpble of bstrct thought, concrete nlysis, nd ruthless implementtion. BSEE from University of Cliforni, Berkeley. More thn 8 Yers experience in circuit, signl processing, digitl, softwre, nlog, nd system design. Holder of six U.S. Ptents (plus three pending for medicl systems, signl processing, nd digitl block enhncements. Author of numerous ppliction notes, web csts, nd technicl rticles. Joined Cypress Semiconductor t the dwn of the New Millennium. dwv@cypress.com 4/4/006 evision A - 6 -
AN367 Appendix A Differentil Gin lues for & \ 0.33 0.67 3 4 5 6 7 8 9 0 3 4 5 6 0.33 48.00 3.00 4.00 3.7 9.60 7.38 6.00 5.05 4.36 3.84 3.43 3.0.8.59.40.3.09.96 0.67 3.00 4.00 9.0.00 8.73 6.86 5.65 4.80 4.7 3.69 3.3 3.00.74.53.34.8.04.9 4.00 9.0 6.00 0.67 8.00 6.40 5.33 4.57 4.00 3.56 3.0.9.67.46.9.3.00.88 3.7.00 0.67 8.00 6.40 5.33 4.57 4.00 3.56 3.0.9.67.46.9.3.00.88.78 3 9.60 8.73 8.00 6.40 5.33 4.57 4.00 3.56 3.0.9.67.46.9.3.00.88.78.68 4 7.38 6.86 6.40 5.33 4.57 4.00 3.56 3.0.9.67.46.9.3.00.88.78.68.60 5 6.00 5.65 5.33 4.57 4.00 3.56 3.0.9.67.46.9.3.00.88.78.68.60.5 6 5.05 4.80 4.57 4.00 3.56 3.0.9.67.46.9.3.00.88.78.68.60.5.45 7 4.36 4.7 4.00 3.56 3.0.9.67.46.9.3.00.88.78.68.60.5.45.39 8 3.84 3.69 3.56 3.0.9.67.46.9.3.00.88.78.68.60.5.45.39.33 9 3.43 3.3 3.0.9.67.46.9.3.00.88.78.68.60.5.45.39.33.8 0 3.0 3.00.9.67.46.9.3.00.88.78.68.60.5.45.39.33.8.3.8.74.67.46.9.3.00.88.78.68.60.5.45.39.33.8.3.9.59.53.46.9.3.00.88.78.68.60.5.45.39.33.8.3.9.4 3.40.34.9.3.00.88.78.68.60.5.45.39.33.8.3.9.4.0 4.3.8.3.00.88.78.68.60.5.45.39.33.8.3.9.4.0.07 5.09.04.00.88.78.68.60.5.45.39.33.8.3.9.4.0.07.03 6.96.9.88.78.68.60.5.45.39.33.8.3.9.4.0.07.03.00 Cypress Semiconductor 700 6 nd Street SW, Building D Lynnwood, WA 98087 Phone: 800.669.0557 Fx: 45.787.464 http://www.cypress.com/ Copyright 006 Cypress Semiconductor Corportion. All rights reserved. PSoC is registered trdemrk of Cypress Semiconductor Corp. "Progrmmble System-on-Chip," PSoC Designer nd PSoC Express re trdemrks of Cypress Semiconductor Corp. All other trdemrks or registered trdemrks referenced herein re the property of their respective owners. The informtion contined herein is subject to chnge without notice. Mde in the U.S.A. 4/4/006 evision A - 7 -