Meets or Exceeds Requirements of ANSI EIA/TIA-422-B and ITU Recommendation V. -State, TTL-Compatible s Fast Transition Times High-Impedance Inputs Single -V Supply Power-Up and Power-Down Protection Designed to Be Interchangeable With Motorola MC487 A Y Z,2EN 2Z 2Y 2A GND D OR N PACKAGE (TOP VIEW) 2 4 6 7 8 6 4 2 0 9 V CC 4A 4Y 4Z,4EN Z Y A description The MC487 offers four independent differential line drivers designed to meet the specifications of ANSI EIA/TIA-422-B and ITU Recommendation V.. Each driver has a TTL-compatible input buffered to reduce current and minimize loading. The driver outputs utilize -state circuitry to provide high-impedance states at any pair of differential outputs when the appropriate output enable is at a low logic level. Internal circuitry is provided to ensure a high-impedance state at the differential outputs during power-up and power-down transition times provided the output enable is low. The outputs are capable of source or sink currents of 48 ma. The MC487 is designed for optimum performance when used with the MC486 quadruple line receiver. It is supplied in a 6-pin dual-in-line package and operates from a single -V supply. The MC487 is characterized for operation from 0 C to 70 C. logic symbol logic diagram (positive logic),2en A 2A,4EN 4 7 2 EN EN 2 6 Y Z 2Y 2Z,2EN A 2A 4 7 2 6 Y Z 2Y 2Z A 4A 9 0 4 Y Z 4Y 4Z,4EN A 2 9 0 Y Z This symbol is in accordance with ANSI/IEEE Std 9-984 and IEC Publication 67-2. 4A 4 4Y 4Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, Texas Instruments Incorporated POST OFFICE BOX 60 DALLAS, TEXAS 726
schematics of inputs and outputs FUNCTION TABLE (each driver) INPUT OUTPUT OUTPUTS ENABLE Y Z H H H L L H L H X L Z Z H = TTL high level, L = TTL low level, X = irrelevant, Z = High impedance VCC EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC Input 9 Ω NOM absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note )............................................................. 8 V Input voltage, V I........................................................................... V voltage, V O......................................................................... 7 V Continuous total power dissipation..................................... See Dissipation Rating Table Operating free-air temperature range, T A.............................................. 0 C to 70 C Storage temperature range, T stg................................................... 6 C to 0 C Lead temperature,6 mm (/6 inch) from case for 0 seconds: D or N package................ 260 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : All voltage values, except differential output voltage, VOD, are with respect to the network ground terminal. PACKAGE DISSIPATION RATING TABLE TA 2 C DERATING FACTOR TA = 70 C POWER RATING ABOVE TA = 2 C POWER RATING D 90 mw 7.6 mw/ C 608 mw N 0 mw 9.2 mw/ C 76 mw 2 POST OFFICE BOX 60 DALLAS, TEXAS 726
recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.7.2 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V Operating free-air temperature, TA 0 70 C electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VIK Input clamp voltage II = 8 ma High-level output voltage VIL = 0.8 V, VIH = 2 V, IOH = 20 ma 2. V Low-level output voltage VIL = 0.8 V, VIH = 2 V, IOL = 48 ma 0. V VOD Differential output voltage RL = 00 Ω, See Figure 2 VOD Change in magnitude of 4 differential output voltage RL = 00 Ω, See Figure ±0.4 V VOC Common-mode output voltage RL = 00 Ω, See Figure VOC Change in magnitude of 4 common-mode output voltage RL = 00 Ω, See Figure ±0.4 V IO current with power off VCC = 0 VO = 6 V 00 VO = 0.2 V 00 impedance V O = 2.7 V 00 IOZ High-impedance-state output current enables at 0.8 V V O = 0. V 00 II Input current at maximum input voltage VI =. V 00 µa IIH High-level input current VI = 2.7 V 0 µa IIL Low-level input current VI = 0. V 400 µa IOS Short-circuit output current VI = 2 V 40 40 ma s disabled 0 ICC Supply current (all drivers) ma s enabled, No load 8 VOD and VOC are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. In ANSI Standard EIA/TIA-422-B, VOC, which is the average of the two output voltages with respect to ground, is called output offset voltage, VOS. Only one output at a time should be shorted, and duration of the short circuit should not exceed one second. switching characteristics over recommended operating free-air temperature range, V CC = V PARAMETER TEST CONDITIONS MIN MAX UNIT tplh Propagation delay time, low- to high-level output 20 ns tphl Propagation delay time, high- to low-level output CL = pf, See Figure 2 20 ns Skew time 6 ns tt(od) Differential-output transition time CL = pf, See Figure 20 ns tpzh enable time to high level 0 ns tpzl enable time to low level 0 ns CL =0pF F, See Figure 4 tphz disable time from high level 2 ns tplz disable time from low level 0 ns µa µa POST OFFICE BOX 60 DALLAS, TEXAS 726
PARAMETER MEASUREMENT INFORMATION VOD VOC Generator (see Note A) Figure. Differential and Common-Mode Voltages TEST CIRCUIT SW CL = pf (see Note B) 200 Ω See Note C V Input tplh Y Z Skew tphl tplh TAGE WAVEFORMS tphl Skew NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ns, tf ns, PRR MHz, duty cycle = 0%, ZO =. B. CL includes probe and stray capacitance. C. All diodes are N96 or N064. Figure 2. Test Circuit and Voltage Waveforms Generator (see Note A) CL RL = 00 Ω CL = pf (see Note B) Input tt(od) 90% 0% tt(od) TEST CIRCUIT TAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ns, tf ns, PRR MHz, duty cycle = 0%, ZO =. B. CL includes probe and stray capacitance. Figure. Test Circuit and Voltage Waveforms 4 POST OFFICE BOX 60 DALLAS, TEXAS 726
PARAMETER MEASUREMENT INFORMATION or SW SW V 200 Ω Generator (see Note A) CL = pf (see Note B) kω See Note C SW2 TEST CIRCUIT Enable Input tphz tplz 0. V 0. V SW Closed SW2 Closed SW Closed SW2 Closed Enable Input tpzl tpzh SW Closed SW2 Open SW Open SW2 Closed TAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ns, tf ns, PRR MHz, duty cycle = 0%, ZO =. B. CL includes probe and stray capacitance. C. All diodes are N96 or N064. Figure 4. Driver Test Circuit and Voltage Waveforms POST OFFICE BOX 60 DALLAS, TEXAS 726
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