A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier

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Transcription:

A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier Hyunui Lee, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan

Outline Background Body voltage controlled amplifier 12-bit, 300 MS/s interpolated pipeline ADC Simulation and measurement results Conclusion 2

Background Body voltage controlled amplifier 12-bit, 300 MS/s interpolated pipeline ADC Simulation and measurement results Conclusion 3

Background To realize high order modulation, high performance ADC is required (Bit Error Rate) BER 1 0.1 0.01 1. 10 3 1.10 4 1. 10 5 6) 1. 10 6 1. 10 7 1. 10 8 1.10 9 1. 10 10 D N F rate s QPSK 16QAM 64QAM 256QAM 0 10 20 30 40 D rate : Data rate N: ADC s resolution F s : Sampling frequency [1] A. Matsuzawa, AVIC, 2012 SNR (db) 4

Interpolated Pipeline ADC 10-bit, 320 MS/s with low-gain amplifier No calibration for MDAC stage Pipeline Stage Pipeline Stage [2] M. Miyahara, et al., VLSI Circuits, 2011. 5

45-dB gain op-amp (with feedback) Amplifier s Linearity Issue Open-Loop SD-amp is not enough for 12-bit ENOB ENOB [bit] 12.0 11.8 11.6 11.4 11.2 11.0 10.8 10.6 10.4 10.2 10.0 N 1 2 log 2 1 + a 2.9 a 3 1 V 2 FS 2 Calculation Simulation N 3 0 0.5 1 1.5 2 2.5 3 3.5 a 3 /a 1 2 N 1st a 3 /a 1 : Amplifier s non-linearity N: ADC resolution (12) N 1st : 1 st stage resolution (4) V FS : full-scale reference range (+/- 75 mv) Source Degeneration (SD) amplifier (Open-loop) 6

Background Body voltage controlled amplifier 12-bit, 300 MS/s interpolated pipeline ADC Simulation and measurement results Conclusion 7

Conventional Amplifier Topologies Folded Cascode Telescopic Power High (4I) Low (2I) Swing Range Wide (V DD -4V ds ) Narrow (V DD -5V ds ) 8

Body Voltage Controlled Amplifier V INP V BP V BN Output Commonmode Feedback V OUTN M 1 I V COM φ 1,2 M 3 M 4 M 9 V BIASP C 1 C 2 I M 10 M 7 M 5 M 6 M 8 V BIASN C FB M 2 V OUTP V INN Only 2I flows No tail current source M 1 ~M 4 : Input M 5 ~M 6 : Current mirroring M 7 ~M 10 : Gain enhancement V BC Bias Current Feedback φ 1,2 V COM 9

Current Biasing Method W 1 : αw 2 = i : αi Current mirroring Current biasing by NMOS body bias control 10

Amplifier for Current Biasing Current variation transferred via C 1 C 2 for generating DC voltage for feedback 11

Current Biasing Range Current biasing range : 5.5 ~ 10.5 ma g mb is maintained higher than 8.5 ms 12

Amplifier for CMFB Outputs are averaged in C 3 Averaged voltage is transferred via C 4 φ 2 V OUTP V COM 200fF C φ 1 1 V OUTN 100fF φ 2 C 3 4pF φ 1 C 4 100fF C 2 A P V DD V OUT (V BIASP ) 13

Background Body voltage controlled amplifier 12-bit, 300 MS/s interpolated pipeline ADC Simulation and measurement results Conclusion 14

ADC Architecture 5 stages (1-bit redundancy in 1 st ~ 4 th ) 1 st stage utilizes closed-loop topology 15

Amplifier s Offset Calibration Amplifier s offset is cancelled by DAC 16

AC Simulation Results ENOB keeps higher than 11.5-bit until 400 MS/s @ 50 MHz input 10.8-bit of ENOB is achieved @ 400 MS/s and Nyquist input All transistor model Room temperature Without transient noise and component mismatch 17

ADC Chip Photo 1P9M 90 nm CMOS, Core area is 0.48 mm 2 18

DC Measurement Results DNL: + 1.4 / - 1 INL : + 4.5 / - 5.8 DC characteristic is degraded by parasitic components in input and ref. nodes DNL [LSB] INL [LSB] 19

Measured FFT Spectrum 300 MS/s and 100 khz input 10-bit of ENOB is achieved 0-20 -40-60 -80-100 -120 0 5 10 15 Frequency [MHz] 20

Amplifier Performance Table To achieve 12-bit, 400 MS/s ADC operation, Topology Body voltage control DC Gain [db] 45 Power Consumption [mw] 15.6 ( 40 % from Folded-Cascode) Settling Time [ps] 500 Output Swing Range [mv pp ] 600 ( 12.5 % from Telescopic) 21

ADC Performance Table This work [3] [4] [5] Resolution [bit] 12 12 12 12 F sample [MS/s] 300 800 1000 3000 V DD [V] 1.2 1 / 2.5 1.8 / 3.3 1 / 2.5 Power [mw] 60 105 550 500 ENOB peak [bit] 9.96 (100 khz) 9.5 9.5 (by SNR) FoM [pj/conv.] 0.2 0.18 0.76 0.23 Technology [nm] 90 40 180 (SiGe) Core Area [mm 2 ] 0.48 0.88 2.35 0.4 Linearity Compensation No Yes Yes Yes Interleave No 4-times No 2-times [3] D. Vecchi, et al., JSSC 2011. [4] R. Payne, et al., ISSCC 2011. [5] C. Y. Chen and J. Wu, VLSI Circuits, 2011. 9.5 40 22

Background Body voltage controlled amplifier 12-bit, 300 MS/s interpolated pipeline ADC Simulation and measurement results Conclusion 23

Conclusion Body voltage controlled amplifier is proposed Low power consumption & wide swing range 12-bit, 300 MS/s interpolated pipeline ADC with proposed amplifier is demonstrated No linearity calibration ADC achieves 10-bit of ENOB with slow input Performance can be improved by elimination of input parasitic components 24

Acknowledgement This work was partially supported by NEDO, MIC, CREST in JST, STARC, Berkeley Design Automation for the use of the Analog Fast SPICE (AFS) Platform, and VDEC in collaboration with Cadence Design Systems, Inc. and Huawei. 25

Thank you for your interest! Hyunui Lee, lee@ssc.pe.titech.ac.jp 26

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