1 Advanced Digital IC Design A/D Conversion and Filtering for Ultra Low Power Radios Dejan Radjen Yasser Sherazi Contents A/D Conversion A/D Converters Introduction ΔΣ modulator for Ultra Low Power Radios Measurement Results Sub-VT Digital Circuits Motivation and Sub-VT Basics High-level Modeling in the Sub-V T Domain Energy-Throughput Analysis w.r.t. different V T s Reliability Analysis Conclusions Low Power Circuits, Dejan and Yasser, 2012-02-14 1 Low Power Circuits, Dejan and Yasser, 2012-02-14 2 Why is this important? A/D Conversion Low Power Circuits, Dejan and Yasser, 2012-02-14 3 Low Power Circuits, Dejan and Yasser, 2012-02-14 4
2 A/D converters introduction A/D converters introduction White noise approximation accuracy Accurate for rapidly changing and random input signals Increases with the number of bits in the quantizer Least accurate for 1-bit quantizers but used anyway Maximum theoretical SNR for an N-bit ideal ADC SQNRdB = 6.02N + 1.76 Low Power Circuits, Dejan and Yasser, 2012-02-14 5 Low Power Circuits, Dejan and Yasser, 2012-02-14 6 Basic principle of oversampling Basic principle of oversampling Low Power Circuits, Dejan and Yasser, 2012-02-14 7 Low Power Circuits, Dejan and Yasser, 2012-02-14 8
3 ΔΣ modulation for A/D conversion SQNR controlled by Order of the loop filter Number of bits in the quantizer Oversampling ratio General ΔΣ-modulator Y( z) = STF( z) X( z) + NTF( z) E( z) Signal Transfer Function: STF( z) Noise Transfer Function: NTF( z) Linear model ΔΣ ADCs vs. Nyquist ADCs + High resolution obtained with few bits in the quantizer + Mismatch in the quantizer suppressed by the loop - Additional analog blocks in the loop filter - Feedback loop stability issues Low Power Circuits, Dejan and Yasser, 2012-02-14 9 Low Power Circuits, Dejan and Yasser, 2012-02-14 10 Ultra Low Power Receiver Continuous Time ΔΣ-modulators Synchronization RF front end ΔΣ modulator Decimation filters Matching filters Analog decoder Continuous time domain Discrete time domain Sampling operation moved after the loop filter Implicit anti alias filtering inherited Specifications Supply voltage: 900 mv Maximum input signal: 200 mv diff Power consumption: 300 μw Bandwidth: 125 khz SNDR target: 70 db Sampling frequency: 4 MHz Digital Baseband Low Power Circuits, Dejan and Yasser, 2012-02-14 11 Low Power Circuits, Dejan and Yasser, 2012-02-14 12
4 CT Modulator for ULP Radios DAC mismatch A third order, 3-bit CT ΔΣ modulator has been implemented in CMOS In multi-bit DACs, mismatch between DAC cells causes nonlinearities Digital correction techniques are used to correct for mismatch One successful correction technique is called Data Weighted Averaging g (DWA) [1] D. Radjen, P. Andreani, M. Anderson and L. Sundström, A Low Power Continuous Time ΔΣ Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback, Norchip, Nov. 2011. Low Power Circuits, Dejan and Yasser, 2012-02-14 13 Low Power Circuits, Dejan and Yasser, 2012-02-14 14 DWA algorithm Layout Implementation of the DWA algorithm Decoupling capacitors Loop filter Flash ADC DWA Output buffers DAC1 DAC2 DAC3 Low Power Circuits, Dejan and Yasser, 2012-02-14 15 Low Power Circuits, Dejan and Yasser, 2012-02-14 16
5 Measurement Results Measurement Results Output spectrum Results summary HD 3 =-73dBFS HD 2 =-73dBFS Chip photo DWA on DWA off Low Power Circuits, Dejan and Yasser, 2012-02-14 17 Low Power Circuits, Dejan and Yasser, 2012-02-14 18 Measurement Results Conclusions SNR/SNDR vs. amplitude Peak SNDR=70 db @ -2.5 dbfs Peak SNR=74 db @ -1.7 dbfs ΔΣ modulators achieve high resolution using a few bits in the quantizer Multi-bit CT ΔΣ are sensitive to errors in the feedback DAC Digital correction needed ΔΣ modulation Usually employed for moderate resolution o but pushing towards higher resolutions and higher frequencies Low Power Circuits, Dejan and Yasser, 2012-02-14 19 Low Power Circuits, Dejan and Yasser, 2012-02-14 20
6 Motivation and Sub-VT Basics Sub-VT Digital Circuits Energy minimum operating voltage in sub-vt. Circuit operates at critical path speed, idle time is minimized. Delay increases exponentially. Energy Optimum Region Low Power Circuits, Dejan and Yasser, 2012-02-14 21 Low Power Circuits, Dejan and Yasser, 2012-02-14 22 Main Sources of Leakage Normalized average leakage in Inverter Circuitry using RBB Gate leakage Tunneling of electrons from bulk and the overlapped p-n diffusion region into the gate through the thin oxide. P-N junction leakage Flow of the minority carries drifting from the reverse p-n junction between both source and drain to bulk (BTBT). BTBT BULK GATE SUB BTBT Sub-threshold leakage Caused by diffusion of carriers in weak inversion region. At V DD =0.1V, we get 6% leakage reduction. At V DD = 0.3V, we get 16% leakage reduction. At V DD = 1.2V, we get 20% leakage reduction. Low Power Circuits, Dejan and Yasser, 2012-02-14 23 Low Power Circuits, Dejan and Yasser, 2012-02-14 24
7 High level Modeling in the Sub V T Domain [1] Energy Model Application No standard/commercial flow available which simply characterizes designs with V DD 400 mv. Effect of Switching Activity on EMV [3] Script Based Processing Good For Initial Charaterization High level Energy Model Conventional EDA tools. SPICE accurate in a fraction of SPICE simulation time. Any RTL design. Standard and full custom based designs. For Sign Off, recharaterized Sub VT lib flow is used to get better timing information [2] [1] O. Akgun, J. Rodrigues, Y. Leblebici, and V. Owall, High level energy estimation in the sub V T domain: Simulation and measurement of a cardiac event detector, in IEEE TBIOCAS. [2] Pascal Meinerzhagen, Oskar Andersson, Yasser Sherazi, Andreas Burg, and Joachim Rodrigues, Synthesis Strategies for Sub V T Systems ECCTD 2011. Low Power Circuits, Dejan and Yasser, 2012-02-14 25 High switch activity shifts EMV to lower voltages. Sub optimal operational frequency leads to high energy dissipation. [3] Oskar Andersson, S. M. Yasser Sherazi, and Joachim N. Rodrigues, Impact of Switching Activity on the Energy Minimum Voltage for 65 nm Sub V T CMOS. Submitted Low Power Circuits, Dejan and Yasser, 2012-02-14 26 Energy Model Application Energy Throughput Analysis w.r.t. different V T s Decimation Filter Chain [4,5] Original Requirements Minimum energy per sample operation. Decimate data from 8 Msamples/s to 025M 0.25 Msamples/s. Questions: Optimal operational voltages. Parallelized by 4 Architectures that provide sufficient throughputs need to be developed. Selection of cells based on threshold options in 65 nm. Various architectures of a half band digital filter (HBD) are implemented: Parallelized by 2,4, and 8. [4] S. Sherazi, J. Rodrigues, O. Akgun, H. Sjöland, and P. Nilsson, Ultra low power sub V T decimation filter chain, Norchip, 2010. [5] S. Sherazi, P. Nilsson, O. Akgun, H. Sjöland, and J. Rodrigues, Design exploration of a 65 nm sub V T CMOS digital decimation filter chain, ISCAS, 2011. Energy vs V DD. Minimum Energy HVT cells have least energy dissipation. HVT = High V T Cells SVT = Standard V T Cells LVT = Low V T Cells Throughput @ 250 mv Energy vs Throughput. SVT cells have least energy dissipation for moderate throughput requirments. Low Power Circuits, Dejan and Yasser, 2012-02-14 27 Low Power Circuits, Dejan and Yasser, 2012-02-14 28
8 Dual V T Implementations [5] Standard Cell Based Memory [6] Minimum Energy H+S SVT HVT Throughput @ 250 mv H+S SVT HVT Super V T or Nominal Voltage SRAM macro cells become significantly larger due to the need for 8 T or 10 T [7] bit cells Additional assist circuits required for reliable sub V T operation (sense amplifier). Energy vs Voltage No advantage is observed for H+S combination. [5] S. Sherazi, Joachim N. Rodrigues, Omer C. Akgun, Henrik Sjöland, and Peter Nilsson Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual V T CMOS in the Sub VT Domain, MicroProcessor, Elsevier 2011 (Finial revision) Low Power Circuits, Dejan and Yasser, 2012-02-14 29 Latch arrays are smaller than SRAM macro cells for storage capacities of up to around 1 kbit. [6] N. Verma and A. Chandrakasan, A 65nm 8 10T sub V T SRAM employing sense amplifier redundancy, in Proc. IEEE ISSCC, Feb. 2007. [7] P. Meinerzhagen, S. M. Y. Sherazi, A. Burg, and J. N. Rodrigues, Benchmarking of standard cell based memories in the sub V T domain in 65 nm CMOS technology, IEEE Journal on JETCAS, 2011. Low Power Circuits, Dejan and Yasser, 2012-02-14 30 Standard Cell Based Memories (SCM) [7] Energy Analysis of SCMs Energy vs Voltage Flip Flop based implementation are a bit faster. [7] P. Meinerzhagen, S. M. Y. Sherazi, A. Burg, and J. N. Rodrigues, Benchmarking of standard cell based memories in the sub V T domain in 65 nm cmos technology, IEEE Journal on JETCAS, 2011. Low Power Circuits, Dejan and Yasser, 2012-02-14 31 Energy vs Voltage Latch based multiplexer clock gate architecture for R = 256, C = 128 and for R = 128, C = 256. The Δ corresponds to [8], a hard macro SRAM memory. [8] B. H. Calhoun and A. P. Chandrakasan, A 256 kb 65 nm subthreshold SRAM design for ultra lowvoltage operation, in IEEE J. of Solid State Circuits, 2007. Low Power Circuits, Dejan and Yasser, 2012-02-14 32
9 Reliability Analysis Conclusions SNM A high level energy flow for sub V T domain characterization was presented. Enablesarchitectural architectural design space exploration. SNM Dual V T implementations may not be beneficial. Eye diagram of the latch used in the SCM architecture for V DD =0.4V and V DD =0.25V. 1000 point Monte Carlo circuit simulation assuming within die process parameter variations. Operation is still possible below V T, but the SNMs are small and reliability starts to become critical at 250mV. SCM are promising option for sub V T memories. Proper knowledge of input stimuli is crucial for system specification. Low Power Circuits, Dejan and Yasser, 2012-02-14 33 Low Power Circuits, Dejan and Yasser, 2012-02-14 34