CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2005

CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2005 EXPERIMENT 1 FUNDAMENTALS 1. GOALS : Lern how to develop cr lrm digitl circuit during which the following re introduced : CS2204 l fundmentls, nd Digitl Circuit Design fundmentls 2. L Work : 2.1. L Fundmentls : The L will tke plce in CIS L 227RH. Ech section will hve three hours per week in the l. The l is structured to develop term project y using the Xilinx Foundtion 4.2i softwre pckge nd the Digilent XLA5 FPGA (Field Progrmmle Gte Arry) ord. An FPGA chip is hrdwre progrmmle chip tht ehves like the circuit designed on the computer. The L will introduce current digitl design techniques nd tools. It will emulte n environment where engineers grouped together s tem, design projects lock y lock under the guidnce of project mnger. In CS2204, two students will work s tem. Tems re formed lpheticlly. Strting with the third l session, the focus will e on digitl circuit design. A succession of six design experiments will led to the completion of the term project. Ech experiment will mke use of erlier experiments. Experiment 1 nd 2 will introduce Xilinx softwre, Digilent hrdwre nd digitl circuit. Experiments 3, 4, 5 nd 6 re term project phses. Experiment 6 completes the term project. Experiments will e incresingly more complex. Students re strongly suggested tht they keep their experiment files nd directories well orgnized. The L will not ffect the term grde directly, ut l ttention grdes tht men student s motivtion (L ttendnce, rrivl/deprture to/from the L), concentrtion on the experiments, how much they re le to work with their temmtes nd whether their circuits work, will e given. The lst three design experiments will e reviewed nd comments will e mde. 2.2. Softwre Pckge nd the Hrdwre Bord : In order to develop circuits, softwre pckge from Xilinx, the Xilinx Foundtion 4.2i will e used. This softwre is different from the one which comes with the textook. The textook softwre will not e used. The design will e tested on prototyping ord which is the hrdwre students will use in the l. The ord, the Digilent XLA5 FPGA ord, mkes the design process nd verifying tht the design works more concrete. The Digilent ord contins n 84-pin SPARTAN FPGA chip. The circuit developed y using the softwre on the computer is downloded to the FPGA on the Digilent ord. Downloding mens the FPGA chip is hrdwre progrmmed. The progrmmed FPGA chip chrcteristics re often close to those of the gol : custom chip. Thus, if the circuit works correctly on the FPGA chip, one would quickly develop the custom chip from tht. 2.3. Getting Strted in the L : Xilinx Foundtion projects mke use of mny files s it is n industry softwre pckge. In order to help students keep trck of their files, it is decided tht students keep their files in one plce ccessile on cmpus : the LABS domin which corresponds to the S drive on l PCs. The S drive is on server ccessile from lptops nd ny PC t Poly. In order to log on to 227RH PCs, students need to hve n ccount for the LABS domin. Students who do not hve LABS domin ccount cn get it t the Informtion Systems (IS) help desk. Students hve to hve the ccount y the third l session. Hving the LABS domin ccount is not enough to ccess the S drive. This drive must e ctivted s well. If the drive is not ctive, students need to request it from the IS help desk too. The informtion Systems (IS) help desk : Polytechnic University Pge 1 of 6 Experiment 1- Fundmentls Ferury 8, 2005

Room : 337 RH help@duke.poly.edu (718) 260-3123 In cse students hve 227RH l relted prolems or would like to hve the l open, they contct the CS l supervisor Mr. Keni Yip t (718) 260-3023, keni@poly.edu. His office is 225RH. The L softwre nd hrdwre, coupled with 3-hour l sessions nd widely ccessile project storge re re intended to provide students with semless digitl circuit development environment. 3. Developing Cr Set-Belt Alrm Circuit : In order to ccomplish the gols mentioned on pge 1, we will develop smll digitl circuit. The circuit is cr lrm circuit which sounds the lrm if the driver turns on the cr engine efore fstening the set elt. The first development cycle is the development cycle on computers which is the schemtic (determintion of components nd their wiring) sed on design fctors. If the circuit is simple, one cn completely design the circuit, the schemtic, on pper. Then, the schemtic is copied from the pper to the computer. If the circuit is complex, s mny rel-life circuits re, then the high-level design with locks nd sulocks is determined on pper. Then, the schemtic (component determintion nd wiring) is crried out on computers. Once the schemtic is complete, it is tested (simulted) on the computer to see if it works nd stisfies product requirements, otherwise it is modified. Thus, the development cycle on computers consists of three steps : logic design test modify The first step of the development cycle on computers/pper is clled logic design since logicl concepts re pplied to otin the schemtic. Logic design consists of otining the precise input-output reltionship of the circuit nd implementtion of the circuit. 3.1. Development Cycle on Pper/Computers : 3.1.1. Logic Design : 3.1.1.1. The Input-Output Reltionship : The input-output reltionship mens tht the circuit is viewed s lck ox with only its inputs nd outputs considered. Then, the outputs re relted to the inputs. Tht is, we try to determine when (for which input comintions)n output is 1 nd when it is 0. As lck ox, the cr set-elt lrm circuit is shown elow with two inputs nd one output : Pin 28 Pin 27 SW1 SW2 Cr Set-Belt Alrm Circuit lrm LD8 Pin 60 Input is connected to the engine. It is normlly 0. It is 1 when the driver turns on the engine. The input is emulted y switch 1, SW1, which is connected to pin 28 of the FPGA chip. Input is connected to the set elt. It is normlly 0, mening the elt is not fstened. It ecomes 1 if the set elt is fstened. The input is emulted y switch 2, SW2, which is connected to pin 27 of the FPGA chip. Output lrm is normlly 0, mening no lrm. When it is 1 the lrm sounds, i.e. the driver hs turned on the engine efore fstening the set elt. The output is emulted y LED light 8, LD8, which is connected to pin 60 of the FPGA chip. Note tht the pin ssignment of the FPGA chip is given on pge 8 of the Development Cycle on Bredords with FPGAs hndout. Polytechnic University Pge 2 of 6 CS2204 Experiment 1 - Fundmentls Ferury 8, 2005

Textully, the opertion of the digitl circuit, or the input-output reltionship of the circuit cn e specified s follows : The lrm sounds when the engine is turned on AND the set elt is NOT fstened. An equl wy to descrie the input-output reltionship y concentrting on the output = 1 cse nd without ignoring the output = 0 cse is : The output is 1 when input is 1 AND input is 0. Soon we will see tht often we prefer to specify ll input nd output vlues when they re 1. Then, the new input/output reltionship is : The output is 1 when input is 1 AND input is NOT 1. We see tht in the textul description there re two sentences forming compound sttement y mens of the word AND : one sentence is the engine is turned on nd the other one is the set elt is NOT fstened. We lso see tht the second sentence is in the negtive form. Ech sentence specifies wht vlue ech input should hve to sound the lrm. The word tht comines the two sentences, AND, indictes if the input vlues should e 1 simult- Note tht this is the forml wy the textul reltionship is given in digitl circuit design. Another wy to descrie the input-output reltionship is y mens of truth tle tht shows the vlue of the output for ech input comintion : lrm 0 0 0 0 1 0 1 0 1 1 1 0 3.1.1.2. The implementtion : The implementtion mens the schemtic (digitl circuit components nd their wiring) is determined sed on the given product gols (fctors) : speed, cost, power consumption, reliility, size, weight, etc. For Experiment 1, we will not focus on these gols to e le to concentrte on the components, wiring, the softwre, nd the hrdwre. Let s strt with the determintion of the components : the input-output reltionship indictes tht we need digitl circuit tht outputs 1 when it detects tht input is 1 nd input is 0. Wht we re given re components (digitl electronic circuits) nmed gtes. We re given AND, OR nd NOT gtes to use. We will implement the lrm circuit y using these gtes. Truth tles (input-output reltionships) nd symols of these gtes re s follows : AND 0 0 0 0 1 0 1 0 0 1 1 1 OR 0 0 0 0 1 1 1 0 1 1 1 1 NOT 0 1 1 0 AND Gte AND OR Gte OR NOT Gte NOT An AND gte outputs 1 if oth outputs re 1 simultneously. An OR gte outputs 1, if t lest one of the inputs is 1. A NOT gte flips the input vlue. Note tht gte is the simplest digitl electronic circuit one hs. Which gtes cn e used nd how they re connected to ech other re sed on the textul description given ove : The lrm sounds when the engine is turned on AND the set elt is NOT fstened. Polytechnic University Pge 3 of 6 CS2204 Experiment 1 - Fundmentls Ferury 8, 2005

neously or not. In this cse, they should e 1 simultneously. The second sentence indictes we need to hve the inverse vlue of the input to sound the lrm. Thus, we come to the conclusion tht the two circuit inputs re ANDed fter the second input is negted (NOT). Tht is, ll we hve to do is to use the gtes implied y the words AND nd NOT in the compound sentence. We cn determine the implementtion (which gtes, how mny of ech nd their wiring) in different wy! Implementing the circuit lso mens implementing the truth tle of the digitl circuit y using the truth tles of the gtes. The lrm circuit truth tle is similr to the AND gte truth tle, except the ottom two rows. An AND gte, coupled with NOT gte on the input would mke the ottom two rows of the two tles identicl. Tht is, the lrm circuit truth tle is implemented y the truth tles of the AND nd NOT gtes : y (NOT ) lrm ( AND y) ( AND NOT ) NOT = y AND y = AND NOT = lrm 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 0 Since the input-output reltionship of the circuit, (its truth tle) is identicl to the truth tle of the cr set-elt lrm circuit, we conclude tht the ove circuit implements the lrm circuit. A digitl circuit like the one ove, consisting of gtes, is clled gte network. There is field in Mthemtics tht dels with textul description of digitl circuits : Truth-Functionl Clculus. It works on declrtive sentences connected y legl connectives, forming truth-functionl compound ( compound sttement). A declrtive sentence cn e either true or flse. The legl connectives cn e AND, OR, NOT, mong others. Ech sentence is ssigned vrile nd the connectives re represented y their symols. For exmple, AND is Λ, ORis nd NOT is. One cn then convert long text (truth-functionl compound) to truth functionl clculus expression with vriles nd symols only. For exmple, the ove lrm circuit expression is ( Λ ()). Truth-functionl clculus is concerned out when the compound (the text) is true (1, one) nd flse (0, zero). It does not cre out the mening of the sentences s long s they re true or flse. Also, truth functionl expression concentrtes on the input nd output vlues tht re equl 1 s it is cler in the ove truth functionl expression. Converting declrtive sentences nd connectives is strightforwrd, only for simple circuits, since the textul inputoutput reltionship is short. Rel-life prolems re complex nd their textul description is very difficult to convert to n expression y mens of truth-functionl clculus. Now tht we know wht is in the lck ox on pge 2, we end the gte network design of the lrm circuit on pper. We re now redy to move the design to the computer : drwing the schemtic circuit on computer, using Xilinx Foundtion softwre. For this, we will copy the circuit digrm from pper to computer, then simulte it nd modify it if necessry. The simultion of the circuit is done on computer. Modifiction is the chnge of the design sed on test results if errors re discovered. After the modifiction the circuit is simulted gin to verify the circuit modifiction is correct. Often logic design on pper is interleved with or done concurrently with logic design on computers, especilly for complex circuits. Therefore, strting with Experiment 4, we will stop designing them sequentilly. Design on pper will e concurrent with design on computer. 3.1.1.3. Circuit Design on the Computer (Xilinx Softwre) : Follow the steps given elow to develop the circuit. Note tht throughout the semester, steps to go through will e given where ullet symol such s tht shows new step. Key presses nd mouse selections re shown in old. Also, throughout the semester, the hndouts will e prepred y ssuming tht students use their S drive s their project storge spce. If students re not le to ccess the S drive, for exmple, in plce where no network connection is possile, they should use the defult Xilinx project directory which hs the pth \Fndtn\ctive\projects\... Lter, students should move their project to the S drive when they estlish the connection. Another convention to rememer is tht when we sy click the mouse, we men clicking the left mouse utton. The right mouse click will e explicitly mentioned. Polytechnic University Pge 4 of 6 CS2204 Experiment 1 - Fundmentls Ferury 8, 2005

First tsk efore strting new project : In order to keep our designs orgnized, we need to hve them stored with respect to their experiment numer. For ech experiment, we will hve directory on the S drive. Therefore, for the current experiment, we will do the following : Crete new directory nmed exp1 under cs2204. We will hve our lrm circuit project under this exp1 directory. Strting the Xilinx softwre : On your PC, strt the Xilinx Project Mnger y doing one of the two elow : Doule click on the Xilinx Project Mnger icon, Go through menu selections : Strt (on the lower left corner) -> Progrms -> Xilinx Foundtion 4.2 -> Project Mnger. You will see dilogue ox titled Getting Strted in the foreground while the Project Mnger window is in the ckground. Creting New Project : Since we hve not designed ny project yet, we will strt with creting new project. In the Getting Strted dilogue ox, click on the rdio utton with lel Crete New project. Click OK A dilogue ox with the nme New Project will pop up. In the dilogue ox, enter lrm s the nme of your design. We will chnge the directory of the project to the exp1 directory on the S drive : Click on the Browse... utton nd select the project directory (your working directory) s the exp1 directory. All your lrm circuit files will e sved there. Click on the rdio utton with lel Schemtic since we will hve schemtic design, not n HDL design. Finlly, there re three list oxes on the lst row. They re out the FPGA chip specificlly. We hve to mke sure tht the choices re Sprtn, S10PC84, nd 3. Click on the rrow in the Flow re nd scroll until you see Sprtn. Select it. Click on the rrow in the re to the right nd scroll down until you see S10PC84. Select it. Click on the rrow in the re to the right nd select speed 3 for the FPGA. Press OK. The computer shows the Project Mnger window with three pnels. The upper right one which we will constntly use, shows the flow of the project until it completes. We re now redy to open the Schemtic editor to egin the design of the lrm circuit. The schemtic design Click on the Schemtic Editor utton on the upper right pnel to strt the schemtic editor. A lnk design sheet (window) will e shown. At this time, when the schemtic editor is strted, it is lwys in the Select nd Drg mode. In order to plce components (such s n AND gte) on the design sheet, we need to chnge the mode to the Sym- Polytechnic University Pge 5 of 6 CS2204 Experiment 1 - Fundmentls Ferury 8, 2005

ols mode. This cn e done in three different wys : Click on the Symols toolox icon on the left side of the screen : Pull down the menu Mode then select Symols, or Press key F3. The SC Symols window ppers on the right side. This is the lirry of components we will use this semester. Scroll down the list to ecome fmilir with it : Let s plce one of the two components, the 2-input AND gte on the sheet : Click on the AND2 component inside the window on the lirry list. Now n AND2 gte is ttched to your mouse nd you cn plce it on the design sheet wherever you wnt. Drg the mouse to the left nd click it in the middle of the sheet. From this point on follow the steps shown y the professor to complete the implementtion, testing nd downloding. CONTACTS : 1) Students cn see the professor nd teching djuncts (TAs), out the lectures, homework, nd l experiments. 2) Professor s contct informtion : Room : 114 LC (718) 260-3101 Fx : (718) 260-3609 hldun@photon.poly.edu Open-door policy to see the professor. If the door is closed, he might e in the l. Present in the l : Mondys (4-6), Wednesdys (3-5) nd Fridys (2-4) 3) The TAs of the course re Nikhil Joshi, Spn Shenoy, Jeff To, Bo Yng nd Peng Yo. 4) All hndout nd l files re t the course we site : http://cis.poly.edu/cs2204 5) When short-term prolems re encountered in PC ls, students re dvised to contct : help@duke.poly.edu or (718) 260-3123 or go to Room : 337 RH. For CS2204 l relted issues nd to hve the l open, students need to contct the CIS l supervisor Mr. Keni Yip t (718) 260-3023, keni@poly.edu. His office is 225RH For longer-term prolems in PC ls nd ny other mtter, students should not hesitte to contct the professor nd TAs. Polytechnic University Pge 6 of 6 CS2204 Experiment 1 - Fundmentls Ferury 8, 2005