ADC16x250-8 coax rev 1 Independent noise test guide. 2013apr-2013may Matt Dexter
PAPER Receiver as noise sources Topward PSU Set to 15 VDC PAPER Receiver Atten 1 SMA-F adapters 20 db Rterm 20 db In In Upper Source 1 out 6ft LMR195 Atten 2 S/N 005 Lower SHP 100 SLP 300 out 50 ohm 12 SMA to SMB coax 10dB or SMA Chunk BPF HP Power meter measurements : approx dbm With Atten1 = 10 and Atten2 = 4 db : -17.5 With Atten1 = 10 and Atten2 = 3 db : -16.5 With Atten1 = 10 and Atten2 = 0 db : -13.5 With Atten1 = 6 and Atten2 = 0 db : -9 to -10 Out of band level is 38 or more db down. Flow F1dB F3dB F6dB F10dB F20dB F30dB PowerOne 15VDC Linear PSU PAPER Receiver Atten 1 SMA-F adapters 20 db Rterm 20 db In In Upper out 114.3 111.6 110.1 108.6 106.6 104.9 out 50 ohm Fhigh 175 184.3 189 190.5 192.5 194.2 bandwidth 60.7 MHz 72.7 MHz 78.9 MHz 81.9 MHz 85.9 MHz 89.3 MHz Source 2 4dB S/N 002 Lower to to to to to to SLP 250 LMR195 6 ft Atten 2 SHP 100 or SMA Chunk BPF 12 SMA to SMB coax 10dB
Test setup for measuring crosscorrelation of independent noise inputs versus ADC IC inputs, dbm and gain settings and so on. PAPER RCVRs as noise sources Source 2 Source 1 6dB 6dB Here the A3 vs D2 inputs are under test. To test different paths move the noise source cables to different SMB inputs on the faceplate. SMB 6dB D2 6dB A3 Customized Roach2 rev2 1U enclosure faceplate HP 8644A 200 MHz clock 8.085 conformable coax +4.x dbm Net total power: ~ -13.X dbm balun balun host computer Generic PC PSU ADC A ADC D ADC16x250-8 coax rev 1 S/N 001 Zdok+ 0 Roach2 rev 2 S/N D01020401 bare board (not in a chassis) Programming Outputs through the ZDok+ to configure the ADC ICs including setting the digital voltage gain. boffiles: adc16_test_2013_apr_18_1223.bof.gz and r2poco8_testbench_v005_2013_apr_18_2351.bof.gz
RAL L Band Test setup for measuring crosscorrelation of independent noise SRC1 Noise source SRC2 inputs versus ADC IC inputs, -84.6 6ft coax -84.1 dbm and gain settings and so cables dbm/hz dbm/hz at 500 MHz on as also used for ADC16x250-8 differential rev 1 tests 12 db 12 db Here the A3 vs D2 inputs are under test. To test different paths move the noise source cables to different SMB inputs on the faceplate. SMB SLP 70 LPF SLP 70 LPF A3 D2 Customized Roach2 rev2 1U enclosure faceplate 8.085 conformable coax HP 8644A 200 MHz clock balun host computer Generic PC PSU Net total power: -13 dbm balun ADC A ADC D ADC16x250-8 coax rev 1 S/N 001 Zdok+ 0 Roach2 rev 2 S/N D01020401 bare board (not in a chassis) Programming Outputs through the ZDok+ to configure the ADC ICs including setting the digital voltage gain. boffiles: adc16_test_2013_feb_24_201 and r2poco8_testbench_v005_2013_feb_27_1539.bof
Generic test algorithm Initialize the ADC16 and FPGA using the Roach2 rev2 POCO bof file Set the ADC's digital Vgain, Vcm drive,... Check RF cabling, adjust the Vgain register etc Verify histogram and frequency response of ADC samples Run poco for at least 104 10second scans Run deepint.rb to integrate all scans and produce magnitude and phase plot More input combinations to test? No Generate test report Yes Move the test signals to the new inputs under test
Generate test report Continued from Generic test algorithm Part 2 At this point there is a large collection of ps plots generated by the deepint.rb script run for each of the different configurations of input power levels and ADC IC digital Vgain settings. To get some sense of the imperfections added by changing the ADC IC's digital Vgain register or other changes plots for the various cases were overlaid over each other using the Inkscape program. Much nicer plots could be changed by rewriting the deepint.rb script to output ascii or some other format data to be imported into matlab or some other package so the different responses can be directly manipulated as numerical arrays rather than working with the output ps files. A nice task for a future rainy day... Please see the ASCII text test notes for the exact test setup and power levels and ADC rms counts for the different cases. The filenames of the save plot files won't be an exact match All the raw plots and acquired data has been saved for the interested student to mine for additional useful information.
ADC16x250-8 coax rev1 with cables mounted in the customized 1U faceplate The #4-40 1/4 tall standoffs are in use because the lab setup has no enclosure. Both the Roach2 rev2 and this board are sitting on a flat shelf with the same 1/4 tall standoffs.
ADC16x250-8 coax rev 1 S/N 001 close up view of bottom side coax cable to balun connections.
ADC16x250-8 coax rev 1 S/N 001 lab setup
ADC16x250-8 coax rev 1 S/N 001 close up view of top side shield for input A2
ADC16x250-8 coax rev 1 S/N 001 close up view of bottom side shield for input A1 Height of the shield is set by the distance to the bottom of the 1U chassis and is Approximately 1/4.
ADC16x250-8 Coax rev 1 Top side ADC D U8 ADC A U5 ADC B U6 ADC C U7 IC inputs In4 In3 In2 In1 IC inputs In4 In3 In2 In1 IC inputs In4 In3 In2 In1 In4 In3 In2 In1 In8 In7 In6 In5 In12 In11 In10 In9 T4 T3 T2 T1 T8 T7 T6 T5 T12 T11 T10 T9 IC inputs In4 In3 In2 In1 In16 In15 In14 In13 T16 T15 TOP TOP Bottom Bottom 0 0.11 0.22 0.33 0.67 0.78 0.89 1.00 approximate spacing in inches Same approximate physical spacing is used for all ICs. Note: the spacing from IC n input 4 to IC n+1 input 1 (0.34 ) is just over the spacing from IC n input 4 to IC n input 1 (0.33 ). Also note that the baluns on opposite sides of the board overlap just a fraction of 1 pin's solder pad width. Not to scale (X axis is slightly to scale) T14 T13
ADC16x250-8 coax rev 1 S/N 001 close up view of physically relocated B2 top side balun
ADC16x250-8 coax rev 1 S/N 001 close up view of physically relocated C2 top side balun Also shown is the shifted B2 balun as well as the extra mu-metal shield wall between the B4 and B2 baluns.
ADC16x250-8 coax rev 1 S/N 001 close up view of physically rewired D1 bottom side input jumpers to use the D3 input Cshunt and ADC IC pins. Making this change increased the coupling by approximately 10 db to -27 to -30 db; just the same if the original rev 1 D3 path was used.