ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2016 Khanna Adapted from GATech ESE3060 Slides

Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout! Inverter Layout! Gate Layout and Stick Diagrams! Design Rules! Standard Cells! Linear Elements 2

MOSFET V GS = V G - V S V DS = V D - V S! Metal Oxide Semiconductor Field Effect Transistor " Primary active component for the term " Three terminal device " Voltage at gate controls conduction between two other terminals (source, drain) 3

MOSFET IV Characteristics 50 V DS I DS Drain current [arbitrary unit] 40 30 20 10 0 0 2 4 6 8 10 Gate to source voltage [V] V GS Define: V th = Threshold Voltage 4

MOSFET IV Characteristics I DS V GS -V th V DS 5

MOSFET IV Characteristics V DS <V GS -V TH I DS V GS -V th V DS V GS -V TH V DS 6

MOSFET Zeroeth Order Model! Ideal Switch V GS > V th # switch is closed, conducts V GS < V th # switch is open, does not conduct! Gate draws no current from input " Loads input capacitively (gate capacitance) 7

MOSFET Zeroeth Order Model I DS V GS 8

MOSFET N-Type, P-Type! N negative carriers " electrons! Switch turned on positive V GS! P positive carriers " holes! Switch turned on negative V GS V th,n > 0 V GS > V th,n to conduct V th,p < 0 V GS < V th,p to conduct 9

Symmetry! NMOS: " Electrons are carriers " Electrons flow from source-to-drain " From lowest voltage#highest " Drain is most positive terminal " Current flows from drain-tosource! Symmetric Device " Like a resistor, doesn t know difference between two ends " Drain and source are defined by circuit connections 10

Symmetry! Symmetric Device! PMOS: " Holes are carriers " positively " Holes flow from source#drain " Flow from highest voltage#lowest " Drain is most negative terminal " Current flows from source-todrain " Like a resistor, doesn t know difference between two ends " Drain and source are defined by circuit connections 11

Typical N-Well CMOS Process 13

Typical N-Well CMOS Process 14

Interconnect Cross Section ITRS 2007 15

CMOS Layers! Standard n-well Process " Active (Diffusion) (Drain/Source regions) " Polysilicon (Gate Terminals) " Metal 1, Metal 2, Metal3 " Poly Contact (connects metal 1 to polysilicon) " Active Contact (connects metal 1 to active) " Via (connects metal 2 to metal 1) " nwell (PMOS bulk region) " n Select (used with active to create n-type diffusion) " p Select (used with active to create p-type diffusion) 16

NMOS vs PMOS! NMOS built on p substrate! PMOS built on n substrate " Needs an N-well 17

MOS Layout Well, Active, Select 18

MOS Layout Poly Gate 19

Wiring and Contact Layout Diffusion (Active) Contact Poly Contact Via (metal1-metal2) 21

Substrate and Well Contacts! Properties " Set Well and Substrate Voltages to Vdd and Gnd " Prevent Forward Biasing and Latch-Up " Must Be at Least One per Well " Should Be Placed Regularly 22

Layout Example: CMOS Inverter! Set Pitch (place well and power/ground busses) 23

Layout Example: CMOS Inverter! Add Transistors (active, select and poly) 24

Layout Example: CMOS Inverter! Make Connections (poly, metal, and contacts) 25

Layout Example: CMOS Inverter! Add Substrate and Well Contacts 26

Layout Example: CMOS Inverter! Add External Wiring and Resize 27

Example: Mystery Gate 28

Example: NAND Gate 29

Example: NAND Gate (Horizontal) 30

Symbolic Layout! Stick diagrams capture spatial relationships, but abstract away design rules (coming up next )! What gate is this? " How many NMOS? PMOS? D/S connections? 31

Layout Design Rules! Physical Layer " Design Rules are a set of process-specific geometric rules for preparing layout artwork to enable the layout to be manufacturable, i.e. preserve all of the circuit structures and feature geometries intended by the chip designers! Purpose " Realize fabricated chips that are die area efficient and manufacturable by balancing the conflicting objectives to minimize die area and maximize yield! Design Rule Waiver " Explicit permission granted by the fabrication organization to the design organization to violate certain design rules or to allow certain design rule errors on a given design 32

Design Rules! Minimum Separation [A] " Intralayer (all layers) " Interlayer (active to poly/well/select) " From Transistor! Minimum Width (all layers) [B]! Minimum Overlap [C] " Past Transistor (poly, active) " Around Contact Cut (all contacted layers) " Around Active (well, select)! Exact Size (contact cuts) [D] 33

Scalable CMOS Rules! Definition " Design Rules Based on a Unitless Parameter (λ) " λ Scales with Process Feature Size " λ = 0.5*L min " Example: λ = 0.6 in a 1.2mm Process! Advantages " Simplifies Design - Requires Learning Only One Set of Design Rules " Facilitates Translating Designs between Processes 34

Width/Spacing Design Rules 35

Contact Design Rules 36

Potential Consequences of Design Rule Violations! Inter-Layer Design Rule Origins Intended Transistor Catastrophic Error Unintended misalignment cause Source-Drain short circuit Intended Unrelated Poly & Diffusion Catastrophic Error Unintended overlap cause fabrication of a parasitic Transistor 37

Potential Consequences of Design Rule Violations! Inter-Layer Design Rule Origins Contact and Via Masks M1 contact to n-diffusion M1 contact to p-diffusion M1 contact to poly Mn contact to Mn-1 for n = 2, 3,.. -> Contact Mask -> Via Mask Both Metal 1 & Diffusion Intended Contact Alignment Both Metal 1 & Diffusion Mask misalignment Error Unintended misalignment cause poor contact 38

Design Capture Tools! Hardware Description Languages (HDL) & " capture a textual hierarchical description of design at abstraction ranging from gate or even transistor level up to a behavioral description (eg. VHDL, Verilog)! Schematic capture " capture a structural, hierarchical graphical representation of the design netlist (eg. Cadence Composer)! Layout " capture a hierarchical view of the physical geometric aspect of a design. The units of hierarchy are called cells, and have physical extent (size). In general, good design requires that only one cell contain the design info for a particular area of the chip (eg. Cadence Virtuoso) 39

Rules Checking! Complex designs invariably suffer design and design entry errors. There are a number of tools and methodologies to detect and correct " Physical Design Rules Checking (DRC) checks for design rule violations such as minimum spacing etc. DRC checking is complicated by hierarchy and overlap between cells " Electrical Rule Checking (ERC) checks for violations such as shorts between Vdd and GND, opens, and so on " Layout vs. Schematic (LVS) checks for a one-to-one correspondence between transistor schematic and the layout! Formal verification is used to show that the design satisfies a formal description of what it should do! Simulation is used to show that the design is functional on some well selected set of input vectors! Timing analysis is used to predict design performance 40

Circuit Extraction! Circuit extraction extracts a schematic representation of a layout, including transistors, wires, and possibly wire and device resistance and capacitance.! Circuit extraction is used for LVS, and for spice simu- lation of layouts 41

Standard Cells! Lay out gates so that heights match " Rows of adjacent cells " Standardized sizes! Motivation: automated place and route " EDA tools convert HDL to layout 42

Standard Cell Area inv nand3 All cells uniform height Cell area Width of channel determined by routing 43

Standard Cell Layout Example http://www.laytools.com/images/standardcells.jpg 44

CMOS Process Enhancements C. Bipolar Transistors 45

CMOS Poly-Poly Capacitors W L 46

Resistors 47

Big Idea! Layouts are physical realization of circuit " Geometry tradeoff " Can decrease spacing at the cost of yield " Design rules! Can go from circuit to layout or layout to circuit by inspection 48

Admin! HW 1 should be submitted! HW 2 due next week 1/28 " Posted tonight after class! Office hours updated on Course website 49