Established : 3-- Revised : 3-5-9 Doc No. TT-EA-5 Revision. SC73L SC73L Asymmetric Dual Silicon N-ch Power 5..9 Unit : mm. For DC-DC Converter 7 5 Features Low Drain-source On-state Resistance : RDS(on) typ. FET : m (VGS =.5 V), FET :.5 m (VGS =.5 V) Halogen-free / RoHS compliant (EU RoHS / UL-9 V- / MSL : Level compliant) Marking Symbol :A Packaging Embossed type (Thermo-compression sealing) : 3 pcs / reel (standard) 5.9.5 3...7. Gate(FET) 5. Source(FET). Drain(FET). Source(FET) 3. Drain(FET) 7. Source(FET). Drain(FET). Gate(FET) Absolute Maximum Ratings Ta = 5 C Parameter Symbol Rating FET FET Drain to Source Voltage VDS 3 3 Gate to Source Voltage VGS Drain Current Package limited ID DC * ID 3 * * Drain Current (Pulsed) IDp Ta = 5 C, DC * PD.7.5 Total Power Ta = 5 C, DC *3 PD Dissipation Tc = 5 C PD3 9 3 Channel to Ambient * Rth(ch-a) 7 5 Thermal Channel to Ambient Rth(ch-a) 5 Resistance Channel to Case Rth(ch-c). 3.7 C / W Channel Temperature Tch 5 Operating ambient temperature Topr - to +5 C Storage Temperature Range Tstg -55 to +5. Gate(FET) 5. Source(FET) Avalanche Current (Single pulse) * IAR A. Drain(FET). Source(FET) Avalanche Energy (Single pulse) * EAR mj 3. Drain(FET) 7. Source(FET) Note * Device mounted on a glass-epoxy board in Figure. and.. Drain(FET). Gate(FET) * Pulse test : Ensure that the channel temperature does not exceed 5 C *3 Device mounted on a glass-epoxy board in Figure.3 * VDD = V, VGS = to V, L =. mh, Tch = 5 C (initial) Unit V A W Panasonic HSO-F3-B JEITA Code Internal Circuit G S S S 7 5 FET Q S/D 3 G D D D Pin Name Q FET Outline and Figures SS S G S/D FR Glass-Epoxy Board (5. mm 5. mm. mm) GDD D D DD G Figure. (FET) Figure. (FET) Figure.3 (FET, FET) of
Established : 3-- Revised : 3-5-9 Doc No. TT-EA-5 Revision. SC73L Electrical Characteristics Ta = 5 C 3 C FET Parameter Symbol Conditions Min Typ Max Unit Drain-source Breakdown Voltage VDSS ID = ma, VGS = V 3 V Zero Gate Voltage Drain Current IDSS VDS = 3 V, VGS = V A Gate-source Leakage Current IGSS VGS = V, VDS = V A Gate-source Threshold Voltage Vth ID =. ma, VDS = V 3 V Drain-source On-state Resistance RDS(on) ID = A, VGS = V 7 RDS(on) ID = A, VGS =.5 V m Input Capacitance Ciss 7 9 VDS = V, VGS = V Output Capacitance Coss f = MHz Reverse Transfer Capacitance Crss 9 Total Gate Charge Qg.3 VDD = 5 V, VGS = to.5 V Gate to Source Charge Qgs.5 ID = A Gate to Drain Charge Qgd. Turn-on Delay Time * Turn-off Delay Time * td(on) td(off) VDD = 5 V, VGS = to V VDD = 5 V, VGS = to V 7 3 Rise Time * Fall Time * tr tf ID = A ID = A 3 pf ns ns nc Gate resistance rg f = 5 MHz. 3 Body Diode Characteristic Parameter Symbol Conditions Min Typ Max Unit Diode Forward Voltage VSD IS = A, VGS = V.. V Note:. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 73 Measuring methods for transistors.. * Measurement circuit for Turn-on Delay Time / Rise Time / Turn-off Delay Time / Fall Time FET Parameter Symbol Conditions Min Typ Max Unit Drain-source Breakdown Voltage VDSS ID = ma, VGS = V 3 V Zero Gate Voltage Drain Current IDSS VDS = 3 V, VGS = V A Gate-source Leakage Current IGSS VGS = V, VDS = V A Gate-source Threshold Voltage Vth ID =.3 ma, VDS = V.3 3 V Drain-source On-state Resistance RDS(on) ID = A, VGS = V.9.5 RDS(on) ID = A, VGS =.5 V.5 3.5 m Input Capacitance Ciss 3 7 5 VDS = V, VGS = V Output Capacitance Coss 3 f = MHz Reverse Transfer Capacitance Crss 3 9 Total Gate Charge Qg VDD = 5 V, VGS = to.5 V Gate to Source Charge Qgs 9 ID = A Gate to Drain Charge Qgd Turn-on Delay Time * Turn-off Delay Time * td(on) td(off) VDD = 5 V, VGS = to V VDD = 5 V, VGS = to V 3 Rise Time * Fall Time * tr tf ID = A ID = A 9 pf ns ns nc Gate resistance rg f = 5 MHz. 3 Body Diode Characteristic Parameter Symbol Conditions Min Typ Max Unit Diode Forward Voltage VSD IS = A, VGS = V.9. V Note:. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 73 Measuring methods for transistors.. * Measurement circuit for Turn-on Delay Time / Rise Time / Turn-off Delay Time / Fall Time of
Established : 3-- Revised : 3-5-9 Doc No. TT-EA-5 Revision. SC73L * Measurement circuit for Turn-on Delay Time / Rise Time / Turn-off Delay Time / Fall Time VDD = 5 V V V Vin PW = s D.C. % D FET : ID = A FET : ID = A Vout Vin G.7 S 9 % Vin % 9 % 9 % Vout % % td(on) tr td(off) tf 3 of
Established : 3-- Revised : 3-5-9 Doc No. TT-EA-5 Revision. Drain Current ID (A) FET Technical Data ( reference ) 3.5 V ID - VDS.5 V V V VGS = 3 V.... Drain current ID(A) Ta = C 5 C ID - VGS SC73L - C 3 5 Gate-source voltage VGS(V).3.5..5..5 A VDS - VGS A ID = A Gate-source Voltage VGS (V) Drain-source On-state Resistance RDS(on) (m ) RDS(on) - ID.5 V VGS = V Drain current ID (A) Capacitance - VDS Dynamic Input/Output Characteristics Capacitance C (pf) Ciss Coss Crss Gate-source Voltage VGS (V) VDD = 5 V. Drain-source Voltage (V) Total Gate Charge Qg (nc) of
Established : 3-- Revised : 3-5-9 Doc No. TT-EA-5 Revision. FET Technical Data ( reference ) Gate-source Threshold Voltage Vth (V).5 3.5 Vth - Ta -5 5 5 Temperature( ) PD - Ta Drain-source On-resistance RDS(on) (m ) 5 5 5 5 RDS(on) - Ta.5 V PD - Tc SC73L VGS =. V -5 5 5 Temperature( ) Total Power Dissipation PD (W).5.5.5 Measureing on glass epoxy board (5. x 5. x. mm) Total Power Dissipation PD (W) 5 5 5 5 5 5 Temperature Ta ( C) Temperature Tc ( C) Rth - tsw Safe Operating Area Thermal Resistance Rth ( C/W).. Drain Current ID (A). IDp = A Operation in this area is limited by RDS(on) Ta = 5 C, Glass epoxy board (5. 5.. mm) coatedwith copper foil, which has more than 3 mm. ms ms ms... s DC Pulse Width tsw (s) 5 of
Established : 3-- Revised : 3-5-9 Doc No. TT-EA-5 Revision. FET Technical Data ( reference ) Drain current ID (A) 3 V.5 V 3.5 V ID - VDS V VGS =.5 V Drain current ID(A) Ta = C 5 C ID - VGS - C SC73L.3.5..5..5...3 5 A VDS - VGS ID = A A Gate-source Voltage VGS (V) Drain-source On-state Resistance RDS(on) (mω) 3 5 Gate-source voltage VGS(V) RDS(on) - ID.5 V VGS = V Drain Current ID (A) Capacitance - VDS Dynamic Input/Output Characteristics Capacitance C (pf) Ciss Coss Crss Gate-source Voltage VGS (V) VDD = 5 V. 3 5 Total Gate Charge Qg (nc) of
Established : 3-- Revised : 3-5-9 Doc No. TT-EA-5 Revision. FET Technical Data ( reference ) Gate-Source Threshold Voltage Vth (V).5.5 Vth - Ta -5 5 5 Temperature Ta ( C) Drain-source On-resistance RDS(on) (m ) 5 3 RDS(on) - Ta.5 V SC73L -5 5 5 Temperature( ) VGS =. V Total Power Dissipation PD (W) 3.5.5.5 PD - Ta Measureing on glass epoxy board (5. 5.. mm) 5 5 Temperature Ta ( C) Total Power Dissipation PD (W) PD - Tc 5 3 5 5 Temperature Tc ( C) Thermal Resistance Rth ( C/W) Rth - tsw.. Pulse Width tsw (s) Drain Current ID (A). Safe Operating Area IDp = A Operation in this area is limited by RDS(on) Ta = 5 C, Glass epoxy board (5. 5.. mm) coated with copper foil, which has more than 3 mm.... ms ms ms s DC 7 of
Established : 3-- Revised : 3-5-9 Doc No. TT-EA-5 Revision. SC73L HSO-F3-B Unit : mm 5.±..9±. 7. +. -.5 5.±.. +. -.5 5.9±..5±. (7 ) 3.7 to.5.5±..±.5.5±..3±..55 max.55 max (7 ).±..99±. 3 7 5 3.9±..9±..5 max.±..±. Land Pattern (Reference) (Unit : mm).7..55.3...9.9.55.35 3.7.5..5 of
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