A 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit for Backplane Interface

Proceedings of the 5th WSEAS Int. Conf. on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL & SIGNAL PROCESSING, Dallas, USA, November 1-3, 2006 225 A 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit for Backplane Interface KWISUNG YOO, GUNHEE HAN, and SUNGMIN PARK Department of Electrical and Electronic Engineering Yonsei University 134 Sinchon-dong, Seodaemun-gu, Seoul 120-749 Republic of Korea kwisung@cad.yonsei.ac.kr http://cad.yonsei.ac.kr Abstract: - The speed of serial interface through a backplane channel suffers severe ISI (Inter Symbol Interference) caused by the limited bandwidth of the channel. In order to overcome the bandwidth limit, a pulse shaping circuit or an adaptive equalizer is used. This paper presents the comparison between two approaches. Prototype chip is designed for 10Gbps serial data communication through a 34-inch transmission line with a 0.18- CMOS process. The simulation and layout results show that the adaptive equalization has superior performance in power consumption, silicon area and the jitter performance. Key-Words: - Adaptive equalizer, backplane, ISI, pulse shaping, serial interface 1 Introduction By CMOS technology improvements, clock speed of primary circuits such as a CPU (Central Processing Unit), and a DSP (Digital Signal Processor) have continuously increased and attained several GHz operation. At this point, speed-up of a total system is bounded by the chip-to-chip or board-to-board communication speed. In case of several GHz data communications on a backplane channel, PCB lines have a number of imperfections such as flat loss, frequency dependent loss due to its limited bandwidth, and reflection due to the impedance mismatch. These non-idealities degrade signal integrity considerably and hence pulse shaping or adaptive equalization techniques are frequently employed to compensate the bandwidth limit as depicted in Fig. 1. [1] Although digital implementation is preferred for relatively low speed communication, analog implementation is employed in several GHz data communication such as OIF CEI 6+, OIF CEI 11+, XAUI, and so on [2]. This paper presents an analog adaptive equalizer and a pulse shaping circuit in operating 10Gbps data on 34-inch backplane interface. Section II describes the channel model and section III describes the architecture of the pulse shaping filter and the adaptive equalizer. Section IV proposes the circuits and section V provides the simulation results. The conclusion is provided in section VI. (a) pulse-shaping. (b) adaptive equalization. Fig. 1. Channel bandwidth compensation methods. 2 Problem Formulation The backplane channel can be modeled as a 50-Ω lossy transmission line which has FR4 PCB characteristics and 34-inch trace. The package parasitic is modeled by 0.5-pF pad capacitance, and 1.3-nH package inductance as shown in Fig. 2(a). Fig. 2(b) and (c) shows the simulated frequency response and the impulse response of the channel model. The frequency response shows that the

Proceedings of the 5th WSEAS Int. Conf. on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL & SIGNAL PROCESSING, Dallas, USA, November 1-3, 2006 226 channel has about 5dB attenuation at 1GHz and 40dB attenuation at 10GHz. This limited bandwidth causes long tail in impulse response as shown in Fig. 2(b). The ISI components for proceeding symbol sequences are -11dB, -18dB, -23dB and so on. This long tail of impulse response causes ISI and completely closes the eye opening in the received signal as shown in Fig. 2(d). The closed eye means that the received data can not be recovered by a conventional clock data recovery circuits. X ( n) = hk Dn k = h0 DN 1 + h1d N 2 + + hn 1D0. k (1) The multiplication is implemented by changing the polarity of the binary data. The optimal coefficients are obtained by the inverse of the channel model that is obtained from a system identification algorithm [9]. Since the characteristic of the channel can not be obtained in the transmitter side, the pulse shaping is applicable only for the known fixed channel. In this paper, a 3-tap FIR filter is chosen through the simulation using the channel model described in section II. (a) Equivalent channel schematic. Fig. 3. Architecture of the pulse shaping circuit. (b) Frequency response. (c) Impulse response. Fig. 4 shows the architecture of the adaptive equalizer [6]. The HPF is capable to control DC gain and the location of the zero. The DC gain is controlled by feeding back the low frequency signal power difference between the comparator input and the output. The location of zero is controlled by feeding back the signal power difference between the comparator input and the output. The detailed adaptation mechanism and convergence analysis can be found in [10] (d) Eyediagram of the (e) Eyediagram of the transmitted signal. received signal. Fig. 2 Channel model of backplane serial interface. 3 Architecture of Pulse Shaping Filter and Adaptive Equalizer Either a FIR (Finite Impulse Response) type filter or a IIR (Infinite Impulse Response) type filter can be employed for bandwidth compensation. The FIR type is preferred for the pulse-shaping due to the simplicity of implementation [3][4] while IIR type is commonly used for the adaptive equalizer due to simplicity of the adaptation circuitry [5]-[8]. Fig. 3 shows the architecture of the FIR pulse shaping filter whose impulse response is described by, + + Fig. 4. Architecture of the adaptive equalizer. 4 Circuit description As shown in Fig. 3, the main blocks for pulse shaping are DFF (D Flip Flop) as a delay element, XOR gate as a multiplier, and an adder. The DFF and XOR gate are designed using CML (Current Mode Logic) configuration with inductive peaking technique for 10Gbps operation as shown in Fig. 5 [11]. The adder

Proceedings of the 5th WSEAS Int. Conf. on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL & SIGNAL PROCESSING, Dallas, USA, November 1-3, 2006 227 block is implemented with an array of differential pairs whose output currents are summed at the output node. The filter coefficients are realized by applying the bias current that corresponds to each coefficient. The adaptive equalizer consists of a controllable HPF, a comparator and two square difference circuits. A novel controllable HPF is proposed in this work as shown in Fig. 6(a). A trans-conductance from the input to the output node is given as As the output of the HPF is large enough, cascade of two differential amplifiers without inductive peaking technique is enough. Gm 1 g m ( sr2c1+ 1) = + R1 sr2c1+ 1+ g m R2 2. (2) (a) Proposed controllable HPF. (a) D latch. (b) XOR gate. (b) Square difference and integrator. (c) Adder. Fig. 5. Building block circuit diagrams for pulse shaping. Therefore, The DC gain is decided by the variable resistor R 1 and the zero of the filter is decided by the variable capacitance C 1. It is clear that the pole is located at higher frequency than the zero. The variable resistor is implemented with NMOS transistor operating in linear region. The variable capacitor is implemented with PMOS-type MOS capacitor whose source, drain, and bulk are tied together. In order to realize floating capacitor, two MOS capacitors are employed, whose gate is used as control node. The square difference and integrator is implemented as shown in Fig. 6(b). The differential output current of the squarer is given by as [5] KW 2 2 I d1 I d 2 = ( v in, 1 v in, 2 ). L (3) The second part of the circuit transforms the voltage signal into a current signal, and then integrates that currents. Fig. 6(c) shows comparator schematic which makes equalization output signal into digital signal. (c) Comparator. Fig. 6. Building block circuit diagram of the equalizer. (a) DC gain control. (b) Zero frequency control. Fig. 7. Controllability of the proposed HPF.

Proceedings of the 5th WSEAS Int. Conf. on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL & SIGNAL PROCESSING, Dallas, USA, November 1-3, 2006 228 5 Simulation and layout results The pulse shaping filter and the adaptive equalizer with the proposed controllable HPF are designed for 10-Gbps operation using 0.18um CMOS process. Fig. 7 shows the SPICE simulation result of the designed controllable HPF. Fig. 7(a) shows the DC gain controllability without changing the zero frequency and the bandwidth. The control range of DC gain is 1~1.3. Fig. 7(b) shows zero controllability without changing the DC gain and the bandwidth. The control range of zero frequency is 500MHz ~ 1GHz. (a) Output waveform of the pulse shaping filter. Fig. 8. Transistor level simulation result of designed pulse shapping and equalizer circuits. The designed pulse shaping circuit and the adaptive equalizer are simulated using 10Gbps pseudo random bit sequence data on the channel model that is described in section II. Fig. 8(a) shows the output waveform of the pulse shaping filter. Although the high frequency component is significantly emphasized in the transmitter side, the received signal shows appropriate eye diagram as shown in Fig. 8(b). Note that the amplitude of the received signal is 1/5 of the transmitted signal. This means that an additional amplifier is required in the receiver side because the amplitude of the transmitter is limited by the current driving capability of the driver and the EMI radiation on the channel. Fig. 8(c) shows the received signal without pulse shaping. Despite the severe ISI in the received signal, the output of the equalizer s HPF shows wide and clear eye opening with large signal amplitude. Fig. 9 shows the layouts of the designed pulse shaping circuit and the adaptive equalizer. The area of the pulse shaping circuit and the adaptive equalizer are 1650 1450 and 1600 700, respectively. (b) Received signal with the pulse shaping. (c) Received signal without pulse shaping. (a) Layout of the designed pulse shaping circuit. (d) Recovered signal with the equalizer. (b) Layout of the designed adaptive equalizer. Fig. 9. The layouts of the designed circuits.

Proceedings of the 5th WSEAS Int. Conf. on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL & SIGNAL PROCESSING, Dallas, USA, November 1-3, 2006 229 Table 1 summarizes the performance of the pulse shaping and the equalization. The equalizer output has 8-ps peak-to-peak jitter and 350-mV amplitude while the pulse shaping provides 10-ps peak-to-peak jitter and 30-mV amplitude. The equalizer is not only superior in the performance but the power consumption and the silicon area as well. Table 1. The performance omparison Process Equalizer 0.18 CMOS Pre-emphasis 0.18 CMOS Amplitude 350mV 30mV Peak-to-peak jitter 8ps 10ps Area 0.56mm 2 2.24mm 2 Power consumption 10mw 60mW 6 Conclusion This paper proposed a controllable HPF for 10 Gbps equalizer. The comparison of pulse shapping and the equaliztion is obtained from the designed circuits. The simulation results clearly showed that the equalization is a better choice than the pulse shaping for 10Gbps serial interface on a band limited channel. Acknowlegements Authors fully acknowledge the technical and fabrication supports from ATLab, Inc. at Yongin, Korea. Also, IDEC (IC Design Education Center) is fully acknowledged for CAD tools. backplane transceiver in 0.25 CMOS, IEEE J. Solid-State Circuits, vol.38, pp.436-443, March 2003. [5] Kwisung Yoo, Hoon Lee, and Gunhee Han, A Low Power and Small Area Analog Adaptive Line Equalization 100-Mbps Data Rate on UTP Cable, IEICE Transaction on Electronics, vol. E87-C, no. 4, APR. 2004. [6] J. S. Choi, et al., A 0.18 CMOS 3.5-Gb/s Continuous -Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method, IEEE J. Solid-State Circuits, pp.419-425, March 2004. [7] J. Zerbe, et. al., Equalization and Clock Recovery for a 2.5-10Gb/s 2-PAM/4-PAM Backplane Transceiver Cell, IEEE J. Solid State Circuits, vol.38, pp.2121-2130, Dec. 2003. [8] M. M. Green, et al., A BiCMOS 10Gb/s Adaptive Cable Equalizer, ISSCC Dig. of Tech. Papers, pp. 482-483, Feb. 2004. [9] W. Bernard, and D. S. Samuel, Adaptive Signal Processing, New Jersey: Prentice Hall, 1985, ch. 9, 10. [10] Kwisung Yoo, Gunhee Han, and Hongil Yoon, Convergence Analysis of the Cascade Second-Order Adaptive Line Equalizer, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no.6, pp.507-511, June, 2006 [11] P. Heydari, and R. Mohanavelu, Design of ultrahigh-speed low-voltage CMOS CML buffers and latches, IEEE Trans. VLSI Syst. vol. 12, pp.1081-1093, Oct., 2004. References: [1] B. Razavi, Prospects of CMOS technology for high-speed optical communication circuits, IEEE J. Solid-State Circuits, vol. 37, pp.1135-1145, Sept., 2002. [2] Common Electrical I/O (CEI) Electrical and Jitter Interoperability agreement for 6+Gbps and 11+Gbps I/O, Optical Interconnect Forum-Contribution OIF 2004, 104.08, Sept. 2004. [3] M. Li, T. Kwasniewski, S. Wang, and Y. Tao, FIR Filter Optimization as Pre-Emphasis of High-Speed Backplane Data Transmission, Electronics Letters, vol.40, issue 14, 2004. [4] J. T. Stonick, Gu-Yeon Wei, J. L. Sonntag, D. K. Weinlader, An adaptive PAM-4 5-Gb/s