Applications 3G / 4G Wireless Infrastructure Repeaters LTE / WCDMA / CDMA 4 Pin 4x4 mm leadless SMT Package Product Features Functional Block Diagram 7-4 MHz 3 db Maximum Gain at 4 MHz 3.5 db Gain Range in.5 db Steps +4.5 dbm Output IP3 +4 dbm Output PdB.6 db Noise Figure 3-wire SPI Control Programming Pin Marking DSA In Amp Out / V CC 3 4 5 4 DSA Out 3 DSA 6-BIT SPI Amp In 9 8 7 6 5 4 Amp Out / V C LE SID 6 3 CLK 7 8 9 Amp In SOD V DD Backside Paddle /DC GND General Description The is a digital variable gain amplifier (DVGA) featuring high linearity and digital variable gain control in.5 db step sizes. This DVGA integrates a gain block, a digital-step attenuator (DSA), and a high linearity ¼-watt amplifier into a compact 4x4 mm package. The internal 6-bit DSA provides a 3.5 db gain control range and is controlled with a serial periphery interface (SPI TM ). The individual stages are accessible to external ports to allow for optimization of the last stage amplifier for individual bands and also allowing other functional blocks to be added in-between the stages. The features variable gain from db to 3 db at.4 GHz, +4.5 dbm output IP3, and +4 dbm PdB while only consuming 74 ma current from a 5V supply. The module is available in a compact 4-pin 4x4 mm leadless SMT package. Pin Configuration Pin No. Label,,4,6,7,9,,7,8,9, (No Connect),,4 3 DSA In 5 Amp Out / Vcc 8 Amp In SOD V DD 3 CLK 4 SID 5 LE 6 Amp Out / Vcc Amp In 3 DSA Out Backside Paddle /DC Ground Ordering Information Part No. -PCB9 Description ¼ W.7-4. GHz DVGA 9 MHz Evaluation Board -PCB4 4 MHz Evaluation Board Standard T/R size = 5 pieces on a 3 reel Evaluation Boards include USB control board Datasheet: Rev E 5-5-5 - of 7 - Disclaimer: Subject to change without notice
Absolute Maximum Ratings Parameter Rating Storage Temperature -55 to 5 C Input Power, CW, 5Ω, T=5 C Supply Voltage () Digital Input Voltage + dbm +5.5 V +.5 V Operation of this device outside the parameter ranges given above may cause permanent damage. Recommended Operating Conditions Parameter Min Typ Max Units Supply Voltage () 4.75 5. 5.5 V TCASE -4 +85 C Tj for > 6 hours MTTF +7 C Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions. Electrical Specifications Test conditions unless otherwise noted: =+5V, Temp= +5 C, matched 4 MHz reference circuit, max. gain setting Parameter Conditions Min Typ Max Units Operational Frequency Range 7 4 MHz Test Frequency 4 MHz Gain 9 3 35 db Gain Control Range.5 db Step Size 3.5 db Accuracy Error ±(.3+5% of Attenuation setting) db Input Return Loss 7 db Output Return Loss 3 db Output PdB +3 +4 dbm Output IP3 Pout = + dbm/tone, f = MHz +38 +4.5 dbm Noise Figure.5 db Total Supply Current 4 74 ma Amp Current 85 ma Amp Current 87 ma DSA Current ma Thermal Resistance, θjc Junction to case 36.7 C/W Datasheet: Rev E 5-5-5 - of 7 - Disclaimer: Subject to change without notice
Serial Control Interface The has a CMOS SPI TM input compatible serial interface. This serial control interface converts the serial data input stream to parallel output word. The input is 3-wire (CLK, LE and SID) SPI TM input compatible. At power up, the serial control interface resets the DSA to the minimum gain state. The 6-bit SID (Serial Input Data) word is loaded into the register on rising edge of the CLK, MSB first. When LE is high, CLK is internally disabled. Serial Control Timing Characteristics (Test conditions: V DD = +5 V, Temp.=5 C) Parameter Condition Min Max Units Clock Frequency 5% Duty Cycle MHz LE Setup Time, tlesup after last CLK rising edge ns LE Pulse Width, tlepw 3 ns SID set-up time, tsdsup before CLK rising edge ns SID hold-time, tsdhld after CLK rising edge ns LE Pulse Spacing tle LE to LE pulse spacing 63 ns Propagation Delay tplo LE to Parallel output valid 3 ns Serial Control DC Logic Characteristics (Test conditions: V DD = +5 V, Temp.=5 C) Parameter Condition Min Max Units Input Low State Voltage, VIL.8 V Input High State Voltage, VIH.4 V Output High State Voltage, VOH On SOD pin. V Output Low State Voltage, VOL On SOD pin.8 V Input Current, IIH / IIL On SID, LE and CLK pins + µa SID Control Logic Truth Table MSB 6-Bit Control Word LSB D5 D4 D3 D D D Gain Relative to Maximum Gain Maximum Gain.5 db db db 4 db 8 db 6 db 3.5 db Any combination of the possible 64 states will provide a reduction in gain of approximately the sum of the bits selected. Timing Diagram CLK is internally disabled when LE is high LE CLK SID D5-D MSB-LSB t PLO D5-D MSB-LSB t SDSUP t SDHLD t LESUP t LEPW Datasheet: Rev E 5-5-5-3 of 7 - Disclaimer: Subject to change without notice
-PCB9 Evaluation Board (869 96 MHz) L3 C8 6.8 pf 3.3 nh 4 3 9 J5-9 C L U C8 L3 3 DSA SPI 8 7 6 33 nh R5 pf uf J R R5 pf 4 5 5 4 R pf LE J5-3 DATA J5- Output L 68 nh 6 3 CLK J5- J5 Notes:. See Evaluation Board PCB Information section for material and stack-up.. All components are of 4 size. 3. The left edge of C8 is placed 88 mil from the device package. J5-. uf J Input 7 8 9 C pf SOD J5-4 J5- Bill of Material -PCB9 Reference Des. Value Description Manuf. Part Number U n/a ¼ W DVGA TriQuint C,,, pf CAP, 4, 5%. 5V. NPO/COG various. uf CAP, 4, %, 6V, X7R various uf CAP, 4, %, V, X5R various C8 6.8 pf CAP, 4, +/-.PF. 5V. NPO/COG various L 68 nh IND, 4, 5%, ceramic core Coilcraft 4CS-68NXJL 33 nh IND, 4, 5%, ceramic core Coilcraft 4CS-33NXJL 3.3 nh IND, 4, CHIP Toko LL5-FHL3N3S R,,, R5,, L3 Ω RES, 4, CHIP various Datasheet: Rev E 5-5-5-4 of 7 - Disclaimer: Subject to change without notice
OIP3 (dbm) PdB (dbm) Noise Figure (db) Gain (db) S (db) S (db) Typical Performance -PCB9 Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting Parameter Conditions Typical Values Units Frequency 869 95 96 MHz Gain 4. 4. 4.5 db Input Return Loss.5 7 8 db Output Return Loss 4 4 db Output PdB 4.4 4. 4. dbm Output IP3 Pout= + dbm/tone, Δf= MHz 39.5 38.5 37.7 dbm Noise figure... db Performance Plots -PCB9 Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting 45 43 Gain vs. Frequency -5 - Input Return Loss vs. Frequency -5 Output Return Loss vs. Frequency 4-5 - 39 - -5 37-5 -3-35 86 88 9 9 94 96-35 86 88 9 9 94 96-5 86 88 9 9 94 96 4 OIP3 vs. Pout/tone over Frequency 8 PdB vs. Frequency Noise Figure vs. Frequency 4 4 96 MHz 95 MHz 869 MHz 6 4.5 39 38 37.5 36 8 9 Pout/tone (dbm) 8 86 88 9 9 94 96 86 88 9 9 94 96 Datasheet: Rev E 5-5-5-5 of 7 - Disclaimer: Subject to change without notice
Evaluation Board 85 88 MHz Reference Design R6.5 pf C8.5 pf 4.3 4 3 9 J5-9 C L U C8 R6 3 DSA SPI 8 7 6 8 nh R5 pf uf J R R5 pf 4 5 5 4 R 8. pf LE J5-3 DATA J5- Output L 68 nh 6 3 CLK J5- J5 J5-. uf J Input 7 8 9 C pf SOD J5-4 J5- Notes:. See Evaluation Board PCB Information section for PCB material and stack-up.. Components are 4 unless specified otherwise 3. Ohm resistors may be replaced with 5 Ohm traces in the target application layout. Bill of Material 85 88 MHz Reference Design Reference Des. Value Description Manuf. Part Number U n/a Sample TriQuint C, pf CAP, 4, 5%. 5V. NPO/COG various 8. pf CAP, 4, +/-.5PF. 5V. NPO/COG various pf CAP, 4, 5%. 5V. NPO/COG various. uf CAP, 4, %, 6V, X7R various uf CAP, 4, %, V, X5R various C8,.5 pf CAP, 4, +/-.PF. 5V. NPO/COG various L 68 nh IND, 5PCT..6 GHz Coilcraft 4CS-68NXJL 8 nh IND, 4, 5%, ceramic core. Coilcraft 4CS-8NXJL 4.3 Ω RES, 4, 5%, /W, CHIP various R,,, R5, R6 Ω RES, 4, CHIP various Datasheet: Rev E 5-5-5-6 of 7 - Disclaimer: Subject to change without notice
PdB (dbm) Noise Figure (db) Attenuation Accuracy (db) OIP3 (dbm) ACLR (dbc) Gain (db) Input Return Loss (db) Output Return Loss (db) Typical Performance 85 88 MHz Reference Design Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting Parameter Conditions Typical Values Units Frequency 85 84 88 MHz Gain 33.8 33.9 33.9 db Input Return Loss -6-8 - db Output Return Loss - - - db Output PdB +4.3 +4.3 +3. dbm Output IP3 Pout= +8 dbm/tone, Δf= MHz +4. +4.6 +4. dbm WCDMA Channel Power () At 5 dbc ACLR +5. +5. +5. dbm Noise Figure.5.5.5 db Notes: ACLR Test set-up: 3GPP WCDMA, TM+64 DPCH, +5 MHz offset, PAR =. db at.% Prob Performance Plots 85 88 MHz Reference Design 36 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency 34-5 -5-3 - -5-5 - 3 - -5-3 8 85 83 855 88 - Attenuation Accuracy vs. Bit Step Part No: 85-88MHz -5 85 83 855 88 45 4 35 OIP3 vs. Pout/tone 88 MHz 84 MHz 85 MHz -35 85 83 855 88-3 -35-4 -45-5 -55-6 ACLR vs. Pout 88 MHz 84 MHz 85 MHz - 3-65 5 5 5 3 35 4 45 5 55 6 65 6 7 8 9 3 4 5 6 3 4 5 6 7 8 9 Bit Step Pout/Tone (dbm) Pout (dbm) PdB vs. Frequency 6 5 4 3 85 83 855 88 Noise Figure vs. Frequency..8.6.4...8.6.4.. 85 83 855 88 Datasheet: Rev E 5-5-5-7 of 7 - Disclaimer: Subject to change without notice
-PCB4 Evaluation Board ( 7 MHz) L3 C8. nh.8 pf. pf 4.3 4 3 9 J5-9 C L U L3 C8 3 DSA SPI 8 7 6 8 nh R5 uf pf J R R5 pf 4 5 5 4 R 8. pf LE J5-3 DATA J5- Output L 68 nh 6 3 CLK J5- J5 7 8 9 Notes:. See Evaluation Board PCB Information section for material and stack-up.. All components are of 4 size. J5-. uf J Input C pf SOD J5-4 J5- Bill of Material -PCB4 Reference Des. Value Description Manuf. Part Number U n/a ¼ W DVGA TriQuint C, pf Cap 4 5% 5V NPO/COG various 8. pf Cap 4 ±. pf 5V NPO/COG AVX 45U8BATA. uf Cap 4 ±% 6V X7R various uf Cap 4 ±% V X5R various pf Cap 4 5% 5V NPO/COG various C8. pf Cap 4 ±. pf 5V NPO/COG AVX 43UCATA.8 pf Cap 4 ±.75 pf 5V NPO/COG AVX 45UR8BATA L 68 nh Ind 4 various 8 nh Ind 4 various L3. nh Ind 4 various R,,, R5 Ω Res 4 various 4.3 Ω Res 4 various Datasheet: Rev E 5-5-5-8 of 7 - Disclaimer: Subject to change without notice
Attenuation Accuracy (db) OIP3 (dbm) PdB (dbm) NF (db) Gain (db) S (db) S (db) Typical Performance -PCB4 Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting Parameter Conditions Typical Values Units Frequency 4 7 MHz Gain 3.6 3.6 3.6 db Input Return Loss 8 8 8 db Output Return Loss 5 4 3 db Output PdB 3.8 3.9 4. dbm OIP3 Pout= + dbm/tone, Δf= MHz 4.8 4.5 43 dbm Noise figure.6.6.6 db Performance Plots -PCB4 Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting 39 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency 36 33 +85 C +5 C 4 C -5 - -5 +85 C +5 C 4 C -5 - +85 C +5 C 4 C 3 - -5 7 3 4 5 6 7-5 3 4 5 6 7-3 4 5 6 7 55 OIP3 vs. Frequency 6 PdB vs. Frequency 3 NF vs. Frequency 5 45 Pout=+ dbm/tone MHz tone spacing +85 C +5 C 4 C 5 +85 C +5 C 4 C.5 +85 C +5 C 4 C 4.5 4 35 3.5 3 3 4 5 6 7 3 4 5 6 7 3 4 5 6 7 Attenuation Accuracy vs. Attenuation.5 7 MHz -.5 4 MHz MHz - 5 5 5 3 35 Attenuation (db) Datasheet: Rev E 5-5-5-9 of 7 - Disclaimer: Subject to change without notice
5 7 MHz Reference Design L3 C8 pf.3 pf 4 3 9 J5-9 C L U L3 C8 3 DSA SPI 8 7 6 8 nh R5 pf uf J R R5 pf 4 5 5 4 R pf LE J5-3 DATA J5- Output L 8 nh 6 3 CLK J5- J5 J5-. uf J Input 7 8 9 C pf SOD J5-4 J5- Notes:. See Evaluation Board PCB Information section for PCB material and stack-up.. Components are 4 unless specified otherwise 3. Ohm resistors may be replaced with 5 Ohm traces in the target application layout. Bill of Material 5 7 MHz Reference Design Reference Des. Value Description Manuf. Part Number N/A N/A Printed Circuit Board TriQuint 9578 U N/A Variable Gain Amplifier TriQuint C,, pf CAP, 4, 5%. 5V. NPO/COG various pf CAP, 4, +/-.5PF. 5V. NPO/COG various. uf CAP, 4, %, 6V, X7R various uf CAP, 4, %, V, X5R various C8.3 pf CAP, 4, +/-.5PF. 5V. ACCU-P AVX 43JABSTR pf CAP, 4, +/-.5PF. 5V. NPO/COG various L, 8 nh IND, 4, 5%, ceramic core. Coilcraft 4CS-8NXJL R,,,, R5, L3 Ω RES, 4, CHIP various Datasheet: Rev E 5-5-5 - of 7 - Disclaimer: Subject to change without notice
PdB (dbm) OIP3 (dbm) Gain (db) Return Loss (db) Typical Performance 5 7 MHz Reference Design Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting Parameter Conditions Typical Values Units Frequency 3 5 6 7 9 MHz Gain 3.5 3. 3.8 3.6 3. db Input Return Loss 5 4 6 9 db Output Return Loss 6 3 db Output PdB +4. +4. +3.9 +3.5 +3. dbm Output IP3 Pout= + dbm/tone, Δf= MHz +4.5 +4.5 +4. +4.5 +4. dbm Performance Plots 5 7 MHz Reference Design Test conditions unless otherwise noted: =+5 V, Temp=+5 C, DSA at max. gain setting 33 3 3 3 Gain vs. Frequency -5 - Return Loss vs. Frequency Output RL Input RL 9-5 8 7-6 3 4 5 6 7 8 9 5 4 PdB vs. Frequency -5 3 4 5 6 7 8 9 43 4 OIP3 vs. Pout/tone over Frequency 3 4 4 39 38 7 MHz 6 MHz 5 MHz 37 9 3 4 5 6 7 8 9 36 8 9 Pout/tone (dbm) Datasheet: Rev E 5-5-5 - of 7 - Disclaimer: Subject to change without notice
34 36 MHz Reference Design L3.6 pf 4 3 9 J5-9 L L3 SPI 8 7 8 nh pf uf L4 C U 3 DSA 6 C.pF J R C Place piece of trace to cover the gap pf L 8 nh 4 5 6 5 4 3 R pf LE J5-3 DATA J5- CLK J5- Output 7 8 9 J5 J5-. uf J Input C pf L4. nh SOD J5-4 J5- Notes:. See Evaluation Board PCB Information section for PCB material and stack-up.. Components are 4 unless specified otherwise 3. Ohm resistors may be replaced with 5 Ohm traces in the target application layout. 4. Critical component placement: a. Distance between U to L4 (left edge): 83 mils b. Distance between to C (edge to edge): mils Bill of Material 34 36 MHz Reference Design Reference Des. Value Description Manuf. Part Number N/A N/A Printed Circuit Board TriQuint 9578 U N/A Variable Gain Amplifier TriQuint C,, pf CAP, 4, 5%. 5V. NPO/COG various pf CAP, 4, +/-.5PF. 5V. NPO/COG various. uf CAP, 4, %, 6V, X7R various uf CAP, 4, %, V, X5R various R5 Use Copper/Metal strip to connect gap various.6 pf CAP, 4, +/-.5PF. 5V. ACCU-P AVX 43JBBSTR C.pF CAP, 4, +/-.5PF. 5V. ACCU-P AVX 43JABSTR L, 8 nh IND, 4, 5%, ceramic core. Coilcraft 4CS-8NXJL L4.nH IND, 4 Multilayer Chip Toko LL5-FHNS R,,,, L3 Ω RES, 4, CHIP various Datasheet: Rev E 5-5-5 - of 7 - Disclaimer: Subject to change without notice
OIP3 (dbm) PdB (dbm) Gain (db) Return Loss (db) Typical Performance 34 36 MHz Reference Design Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting Parameter Conditions Typical Values Units Frequency 34 35 36 MHz Gain 9.6 3 9.8 db Input Return Loss 8 9 3 db Output Return Loss 9 5.5.5 db Output PdB +4. +4.6 +4 dbm Output IP3 Pout= + dbm/tone, Δf= MHz +39. +39.7 +39 dbm Performance Plots 34 36 MHz Reference Design Test conditions unless otherwise noted: =+5 V, Temp=+5 C, DSA at max. gain setting 3 Minimum Attenuation State Gain vs. Frequency Minimum Attenuation State Return Loss vs. Frequency 3-5 3-9 -5 8 7 34 345 35 355 36 - Input Return Loss Output Return Loss -5 34 345 35 355 36 4 Minimum Attenuation State OIP3 vs. Pout/tone 6 PdB vs Frequency 4.5 4 5 39.5 4 39 38.5 38 34 MHz 35 MHz 36 MHz 8 9 Pout/Tone (dbm) 3 34 345 35 355 36 Datasheet: Rev E 5-5-5-3 of 7 - Disclaimer: Subject to change without notice
Detailed Device Description The is a digital variable gain amplifier (DVGA) featuring high linearity over the entire gain control range. The amplifier module features the integration of a 5 Ω internally matched high linearity low noise amplifier gain block, a digital step attenuator (DSA), along with a high linearity ¼W amplifier as shown in the functional diagram below. The DVGA has an operational frequency range from.7 4. GHz. The three stages are individually accessible via package I/O contacts. This permits full flexibility to insert other components or filters between the stages. Functional Schematic Diagram AMP DSA AMP SPI AMP AMP is a high linearity low noise amplifier. The amplifier has high gain across a broad range of frequencies while also providing very low noise. It is internally matched and only requires an external choke and blocking/bypass capacitors for operation from a single +5V supply. The internal active bias circuit also enables stable operation over bias and temperature variations. At.9 GHz, the amplifier typically provides 9.8 db gain, +36 dbm OIP3, and.3 db Noise Figure while only drawing 85 ma of current. DSA (Digital Step Attenuator) The DSA is a high linearity, low insertion loss, 6-bit, 3.5 db Digital Step Attenuator (DSA) operating over the 7-4 MHz frequency range. The digital step attenuator uses a single positive 5V supply and has a serial periphery interface (SPI TM ) for changing attenuation states. This product maintains high attenuation accuracy over frequency and temperature. No external matching components are needed for the DSA. AMP AMP is a high-linearity driver amplifier that delivers high performance past 4GHz. With external tuning it can achieve over +4 dbm OIP3 with +5 dbm PdB while only consuming 87 ma of quiescent current. Chain Analysis Table This table provides the typical performance of individual stages in the module as well as overall module performance. Frequency = 4 MHz. Parameter AMP DSA AMP Overall Module Units Gain 9.8.6 4.4 3.6 db NF.5.6 3.9.6 db OIP3 36 55 4.5 4.5 dbm PdB 3 3.9 3.9 dbm Icc 85 87 74 ma Datasheet: Rev E 5-5-5-4 of 7 - Disclaimer: Subject to change without notice
Pin Configuration and Description Pin Marking DSA Out 4 3 9 Amp In 8 7 DSA In 3 DSA 6 Amp Out / V C 4 5 LE Amp Out / V CC 5 6-BIT SPI 4 SID 6 3 CLK 7 8 9 Amp In SOD V DD Backside Paddle /DC GND Pin No. Label Description,, 4, 6, 7, 9,, 7, No electrical connection. Land pads should be provided for PCB (No Connect) 8, 9,,, 4 mounting integrity. 3 DSA In DSA Input 5 Amp Out / VCC output / DC supply (Amp). 8 Amp In input (Amp). Band-specific matching circuit required. SOD Serial Output Data DC Supply 3 CLK Serial Clock 4 SID Serial Input Data 5 LE Latch Enable 6 Amp Out / VC output / DC supply (Amp). Band-specific matching circuit required. Amp In input (Amp). Band-specific matching circuit required. 3 DSA Out DSA Output Backside Paddle /DC GND /DC ground. Use recommended via pattern to minimize inductance and thermal resistance. See PCB Mounting Pattern. Evaluation Board PCB Information TriQuint PCB 9578 Material and Stack-up.4".6 ±.6 Finished Board Thickness.4" Nelco N-4-3 Nelco N-4-3 ε r =3.7 typ. Nelco N-4-3 oz. Cu top layer oz. Cu inner layer oz. Cu inner layer oz. Cu bottom layer Datasheet: Rev E 5-5-5-5 of 7 - Disclaimer: Subject to change without notice
Mechanical Information Package Marking and Dimensions Marking: Part number Year/week/country code - YYWW CCCC Lot code AaXXXX YYWW CCCC AaXXXX Notes:. All dimensions are in millimeters. Angles are in degrees.. Dimension and tolerance formats conform to ASME Y4.4M-994. 3. The terminal # identifier and terminal numbering conform to JESD 95- SPP-. PCB Mounting Pattern 3 6X PACKAGE OUTLINE 4X.38.5 PITCH R.9.9 4X.7.64.7.64.7 COMPONENT SIDE Notes:. All dimensions are in millimeters. Angles are in degrees.. Use oz. copper minimum for top and bottom layer metal. 3. Vias are required under the backside paddle of this device for proper /DC grounding and thermal dissipation. 4. Do not remove or minimize via hole structure in the PCB. Thermal and grounding is critical. 5. We recommend a.35mm (#8/.35") dia. bit for drilling via holes and a final plated thru diameter of.5 mm (. ). 6. Ensure good package backside paddle solder attach for reliable operation and best electrical performance. 7. There is no effect to the performance if Pads 9 and are removed from the land pattern. Datasheet: Rev E 5-5-5-6 of 7 - Disclaimer: Subject to change without notice
Product Compliance Information ESD Sensitivity Ratings Caution! ESD-Sensitive Device ESD Rating: Class A Value: Passes 5 V to < 5 V Test: Human Body Model (HBM) Standard: JEDEC Standard JS-- ESD Rating: Class Value: Passes V Test: Charged Device Model (CDM) Standard: JEDEC Standard JESD-C MSL Rating MSL Rating: Level 3 Test: 6 C convection reflow Standard: JEDEC Standard IPC/JEDEC J-STD- Solderability Compatible with both lead-free (6 C max. reflow temperature) and tin/lead (45 C max. reflow temperature) soldering processes. Contact plating: Electrolytic plated Au over Ni RoHs Compliance This part is compliant with EU /95/EC RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment). This product also has the following attributes: Lead Free Halogen Free (Chlorine, Bromine) Antimony Free TBBP-A (C5HBr4) Free PFOS Free SVHC Free Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Tel: +.53.65.9 Email: info-sales@triquint.com Fax: +.53.65.89 For technical questions and application information: Email: sjcapplications.engineering@triquint.com Important Notice The information contained herein is believed to be reliable. TriQuint makes no warranties regarding the information contained herein. TriQuint assumes no responsibility or liability whatsoever for any of the information contained herein. TriQuint assumes no responsibility or liability whatsoever for the use of the information contained herein. The information contained herein is provided "AS IS, WHERE IS" and with all faults, and the entire risk associated with such information is entirely with the user. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for TriQuint products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. TriQuint products are not warranted or authorized for use as critical components in medical, life-saving, or lifesustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Datasheet: Rev E 5-5-5-7 of 7 - Disclaimer: Subject to change without notice
Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Qorvo: TQM8796-PCB TQM8M975-PCB.3-4.GHZ EVAL BRD TQM8M976-PCB.3-4.GHZ EVAL BOARD TQM8M977-PCB.3-4.GHZ EVAL BOARD TriQuint: -PCB4