Modelling and imulation in Engineering Volume 8, Article ID 5934, 8 pages doi:.55/8/5934 Research Article Extra-High-Voltage D-D Boost onverters Topology with imple ontrol trategy P. anjeevikumar and K. Rajambal Project Engineer, imulation olutions, hennai, India Department of Electrical and Electronics, Pondicherry Engineering ollege, Pondicherry 654, India orrespondence should be addressed to P. anjeevikumar, sanjeev@yahoo.co.in Received 4 June 7; Accepted January 8 Recommended by Ivan Zelinka This paper presents the topology of operating D-D buck converter in boost mode for extra-high-voltage applications. Traditional D-D boost converters are used in high-voltage applications, but they are not economical due to the limited output voltage, efficiency and they require two sensors with complex control algorithm. Moreover, due to the effect of parasitic elements the output voltage and power transfer efficiency of D-D converters are limited. These limitations are overcome by using the voltage lift technique, opens a good way to improve the performance characteristics of D-D converter. The technique is applied to D-D converter and a simplified control algorithm in this paper. The performance of the controller is studied for both line and load disturbances. These converters perform positive D-D voltage increasing conversion with high power density, high efficiency, low cost in simple structure, small ripples, and wide range of control. imulation results along theoretical analysis are provided to verify its performance. opyright 8 P. anjeevikumar and K. Rajambal. This is an open access article distributed under the reative ommons Attribution icense, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.. Introducton Proceeding to the paper work [, other two topologies are developed for extra-high-voltage applications. Traditional D-D boost converters are used in extra-high-voltage applications. But they are not economical due to the limited output voltage, efficiency, and they require two sensors with complex control algorithm. Because of the effect of parasitic elements, the output voltage and transfer efficiency of D-D converters are limited. Voltage lift technique is a popular method widely applied in electronic circuit design. It has been successfully employed in D-D converter [ 5 applications in recent years, and opened a way to design high-voltage gain converters. The output voltage increases stage-by-stage along the geometric progression. o to overcome these limitations and to make the D-D converter with a simple control loop, a new technique called voltage lift technique is used [6. In this paper, a new series of D-D converter topologies is analyzed which is different from classical boost converter. This paper introduces positive output boost converters employed with voltage lift technique that implements the output voltage increase in a simple geometric progression. They also effectively enhance the voltage transfer gain as per power-law terms. The performance of this D-D converter is superior to classical D-D with reduced control scheme. The performance of this D-D converter is superior to classical D-D with the following advantages. (i) It performs similar to classical D-D boost converter with comparatively high-voltage transfer ratio. (ii) Wide range of control with smooth ripple at the output voltage is an added advantage of this proposed converter. (iii) High power density with high efficiency than classical boost converter. (iv) losed-loop controller requires only one sensor. In this paper, the operation and mathematical analysis of the proposed converters I and II are presented. An algorithm is developed to generate PWM pulses for the N-channel MO- FET. The simulation model of the converter is developed in
Modelling and imulation in Engineering D V D V D i i V D i i D V 3 D V R i i V 3 3 V V R i 3 D3 D Figure : Topology-I of D-D boost converter. Figure : Topology-I (switch-on equivalent circuit). MATAB7 using simulink toolbox. imulation is carried out to study the performance of the converter under line and load disturbances. The simulation results are presented and they closely match with the theoretical results. The effectiveness of the converter is shown by comparing the performance with the classical boost converter. V 3 i V V V i i R. Boost onverter ircuits i 3.. Topology-I The proposed topology of new series of boost converter is derived from the D-D boost converter circuit. Topology-I is a boost converter circuit with the voltage lift components, that is, additional three stages of inductor and capacitor along with the basic circuit are shown in Figure. In this topology, the switch is N-channel power MOFET device (NMO) and it is driven by a pulse-width-modulated (PWM) switching signal with variable frequency f and conduction duty k. For this circuit, the load is usually resistive, R = V /I. The basic principle of this circuit in boosting up the output voltage is charging and discharging reactive elements into a load, controlling the levels of charge, and consequently the output voltage by switching the D supply in and out of the circuit at very high frequencies. They include a freewheeling diode to protect the switch from the inductors high reverse currents, and this also ensures that the generated inductor energy is applied to the load. apacitors are connected in parallel with the load to filter output ripple and maintain a constant output voltage. It consists of passive components: one static switch, diodes, four inductors,,,, and capacitors,,,,and 3. apacitors and 3 perform the characteristics to lift the capacitor voltage V. The directions of all voltages and currents are defined and shown in Figure. We will assume that all the components are ideal and the capacitors are large enough. We also assume that the circuits operate in continuous conduction mode. The output voltage and current are V and I the input voltage and current are and I. Figure 3: Topology-I (switch-off equivalent circuit)... Analysis of Topology-I When switch is turned ON, its equivalent circuit is shown in Figure. The source instantaneous current is equal to i i i i 3 i. The load current flows from the addition of two voltages. That is, the source voltage and the voltage acrossthe capacitor during ON period. Also the capacitors and 3 are charged to the input voltage under switch-on condition. All the inductor current rises during switch-on period. When switch is turned OFF, source current is equal to zero. The stored energy in the inductors,,andand the capacitors and 3 discharges and charge the capacitor with the direction as shown in Figure 3. imultaneously, current i flows through the load, which is sustained by the inductor.urrentsi,, andi decrease during switch-off period. In steady state, the average inductor voltages over a period are zero. Thus V = V. () The inductor current i increases in the switch-on period and decreases in the switch-off period. The corresponding voltages across are,andv -OFF. Therefore, kt = ( k) TV -OFF, [ k () V -OFF =. k
Modelling and imulation in Engineering 3 imilarly, -OFF = k V -OFF = k,. During switch-on period, the voltage across capacitor is equal to the source voltage plus the voltage across. ince we assume that and are sufficiently large, during switch-on period, (3) i D D V 3 D 3 i 3 3 D V 4 4 D 4 i D 3 V D V D D V i i R V = V. (4) Therefore, from switch-off period equivalent circuit, V = V -OFF = V -OFF -OFF V -OFF V V 3, ( ) ( ) ( ) k k k V =, k k k V = 3k k, V = V, [ 3 V =. k (5) The voltage transfer gain of continuous conduction mode (M) is M = V = 3 k. (6) The output voltage, current, and the voltage transfer gain are summarized as follows: Averagevoltagesare Averagecurrentsare [ 3 V = i = k [ k 3 M = 3 k.,, [ k V =, k V = V, i = i, V = V 3 =. = i = i = [ i. k (7) (8) (9) Figure 4: Topology-II of D-D boost converter..3. Topology-II Topology-II of the D-D boost converter is derived from topology-i. Topology-II is the same as topology-i circuit with the additional voltage lift components, that is, capacitor and inductors in addition to that of the topology-i circuit. The output voltage and current of this converter are smooth. The output voltage of this converter is four times that of the input source voltage. It consists of a static switch, diodes D, D, D, D 3, D 4, D, D, D,andD 3, inductors,,,,and 3 capacitors,,, 3,and 4, and the output capacitor. It can be seen that there are one capacitor 4, one inductor 3, and two diodes D 4 and D 3 added into the circuit. apacitors,, 3,and 4 perform characteristics to lift the capacitor voltage Vc by four times that of source voltage V. The directions of all voltages and currents are defined and shown in the Figure 4. It is assumed that all the components are ideal and the capacitors are large enough. It is also assumed that the circuits operate in continuous conduction mode. The output voltage and current are V and I, while the input voltage and current are V I and I. Topology-II performs a positiveto-positive D-D step-up voltage conversion with high efficiency, high power density and cheap topology in a simple structure..4. Analysis of Topology-II When switch is turned ON, the equivalent circuit is shown in Figure 5. The source instantaneous current is equal to i i i i 3 i i 4 i 3. The load current flows from the addition of two voltages, That is, the source voltage and the voltage across the capacitor during switch-on period. Also the capacitors, 3,and 4 are charged to the input voltage under switch-on condition. All the inductor current rises during switch-on period. When switch turned OFF, source current is equal to zero and equivalent circuit is shown in Figure 6. The stored energy in the inductors,, 3,andand the capacitors, 3,and 4 discharges and charges the capacitor with the direction as shown in Figure 6. imultaneously, current i flows through the load, which is sustained by the inductor
4 Modelling and imulation in Engineering i i 3 i V 4 4 V 3 3 3 V V i i D V R imilarly, for,,and 3, -OFF = k V -OFF = k V 3-OFF = k,,. (4) From switch-off period equivalent circuit, Figure 5: Topology-II (switch-on equivalent circuit). i V 4 4 i 3 V 3 i 3 3 V V V i i Figure 6: Topology-II (switch-off equivalent circuit). R. All the inductor currents decrease during the switch-off period. Under steady state, the average inductor voltages over a period are zero. Thus During switch-on period, Also V = V. () V = V 3 = V 4 =. () V = V = V. () The inductor current I increases in the switch-on period and decreases in the switch-off period. The corresponding voltages across are and V -OFF. Therefore, kt = ( k)tv -OFF, [ k V -OFF =. k (3) V = V -OFF = V -OFF -OFF V -OFF V 3-OFF V V 3 V 4, V = 4k k 3, (5) V = V, [ 4k V =. k The output voltage, current, and voltage transfer gain are summarized below [ 4 V =, Averagevoltagesare Averagecurrentsare i = k [ k 4 M = 4 k., [ 3k V =, k V = V, V = V 3 = V 4 =. i = i, [ k i = i, k = i = i 3 = i i = [ i. k (6) (7) (8) Table illustrates the comparison between the analyzed D-D converters with the classical boost converter. From the table, it is clear that the proposed converter topology produces higher output D voltage. 3. losed-oop ontroller for Proposed Boost onverter losed-loop control scheme for the proposed D-D boost converter topology is shown in Figures 7 and 8. The control
Modelling and imulation in Engineering 5 Table : Performance comparison of the proposed D-D boost converter with classical boost converter. D-D converters Output voltage (V ) (volts) Output current (i ) (amps) lassical boost converter V = [k/( k) i = [( k)/k Boost converter topology-i V = [3/( k) i = [( k)/3 Boost converter topology-ii V = [4/( k) i = [( k)/4 i D V D D V 3 3 D3 D V i i D D V R D D D i 3 D V 4 i 4 V 3 3 D 3 3 i D 3 V D V D D V i i R >= aturation PI controller 9 V ref Figure 7: losed-loop controller for topology-i D-D boost converter. scheme essentially consists of only one voltage sensor with simple control structure when compared with classical D-D boost converter which requires both voltage and current sensors. D voltage of the load is fed back and compared with V dc reference voltage and the error is given to the PI controller to stabilize the error and the signal obtained from the controller is the modulating signal for the PWM scheme. ignal from the PI controller is compared with high frequency ramp signal to produce required pulse for the N- channel MOFET switch to obtain the reference D voltage at the load. In this paper, for the above model of the converter [, 3 using the Ziegler-Nichols method is (-shaped curve technique) applied to design the PI controller. tep input is applied to the plant model and the response is the shaped curve. By drawing the tangent to the - shaped curve at its inflection point with reference to X- axis, the time delay and time constant Tare calculated. Using [ Ziegler-Nichols chart, the value of the K p and T i is calculated. The PI controller designed by the above method is tested under different disturbance conditions and results are provided for the feasibility. losed control schemes for both topologies are the same and tuning parametersk p and K i are different. 4. imulation Results imulation results of the proposed D-D boost converter topologies with simplified controller scheme are presented >= aturation PI controller V ref Figure 8: losed-loop controller for topology-ii D-D boost converter. 9 8 7 6 5 4 3 Figure 9: Output voltage at rated condition for topology-i. and discussed further. Design of inductance and capacitance is based on 5% ripple at the output [4 and the values are the same for both load and lift part of the circuit. imulation parameters taken for analysis are Input voltage = volts, Inductance = μh, apacitance = 5 μf, oad resistance = 44 ohms, Duty ratio k =.6666, witching frequency = 5 KHz. PI controller transfer function: Topology-I: G(s) =.65684(55.), Topology-II: G(s) =.65(9) (9).
6 Modelling and imulation in Engineering Table : omparison of simulation result of the proposed converters with classical converter at steady state condition for rated load. Duty ratio (k) Output voltage (V ) classical converter Output voltage (V ) proposed topology-i.. 33.33 44.44..5 37.5 5.3 4.8 4.85 57.4.4 6.66 5 66.66.5 6 8.6 5 75.7 3.33 33.33.8 4 5.9 9 3 4 Output voltage (V ) proposed topology-ii urrent (A).5.5.5 9 8 7 ine disturbance oad disturbance 6 5 4 3 Figure : Output current at rated condition for topology-i. Figure 3: Output voltage of the topology-i for line and load disturbances. Resistance (ohms).4. 9.8 9.6 9.4 9. 9 8.8 Figure : ine disturbance at.3 second for the topology-i. 48 44 Figure : oad disturbance at.6 second for the topology-i. urrent (A).5 oad disturbance.5 ine disturbance.5 Figure 4: Output current of the topology-i under line and load disturbances. 4 8 6 4 Figure 5: Output voltage at rated condition for topology-ii. Figure 9 depicts the output voltage of the converter at rated condition, maintaining 9 volts at 44 ohms load resistance, and the corresponding output current of.45 amperes is shown in Figure. Figure shows the line voltage variation applied to topology-i, initially volts is maintained and introduced a change to 9 volts at.3 second, for analyzing the line disturbance performance. Figure shows the load resistance variation applied to topology-i, initially 48 ohms are maintained and introduced a change to 44 ohms at.5 second, for analyzing the load disturbance performance. Figure 3 illustrates the output voltage for topology-i under both line and load disturbances,
Modelling and imulation in Engineering 7 urrent (A) Resistance (ohms) 3.5.5.5.5 Figure 6: Output current at rated condition for topology-ii..4. 9.8 9.6 9.4 9. 9 8.8 Figure 7: ine disturbance at. second for topology-ii. 48 44 Figure 8: oad disturbance at.4 second for topology-ii. the output voltage stabilized in.5 second for both distortion conditions by the closed-loop controller. Figure 4 illustrates the output current for topology-i under line and load disturbances, as load resistance decreases from 48 ohms to 44 ohms at.5 second the load current increases from.875 amperes to.45 amperes. Figure 5 depicts the output voltage of the converter at rated condition, maintaining volts at 44 ohms load resistance and the corresponding output current of.77 amperes is shown in Figure 6. Figure 7 shows the line voltage variation applied to topology-i, initially volts are maintained and introduced a change to 9 volts at. second, for analyzing the line disturbance performance. Figure 8 shows the load resistance variation applied to topology-i, initially 48 ohms are maintained and introduced a change to 44 ohms at.4 second, for analyzing the load disturbance performance. Figure 9 illustrates the output voltage for topology-i under both line and load disturbances, the output voltage stabilized in.5 second for both distortion conditions by the closed-loop controller. Figure illustrates the output current for topology-i under line and load disturbances, as load resistance decreases from 48 ohms 4 8 6 ine disturbance oad disturbance 4 Figure 9: Output voltage of the topology-ii for line and load disturbances. urrent (A) 3.5 oad disturbance.5 ine disturbance.5.5 Figure : Output current of topology-ii under line and load disturbances. to 44 ohms at.5 second the load current increases from.5 amperes to.77 amperes. 5. Effectiveness of the Proposed onverter The effectiveness of the proposed converter topologies is shown in Table by comparing the simulation results with classical boost converter. It is seen from Table that the output voltage varies from 33.33 volts to 3 volts for topology- I and 44.44 volts to 4 volts for topology-ii, respectively, for a duty ratio of. to.9. However, the classical converter produces only a maximum of 9 volts. This shows that the proposed converter provides higher output voltage. 6. onclusions A new series of D-D boost converter topologies are proposed. The topologies use voltage lift technique to obtain higher output voltage than the classical boost converter for the same duty ratio. The technique also overcomes the effect of parasitic elements and minimizes the ripple in the output voltage. A simplified controller with one sensor is designed to maintain the output voltage at the required level for the load and line disturbances. imulation results validate the theoretical analysis. The proposed converter topologies find application in computer peripheral circuits, medical equipments, and industrial applications which require higher D voltages. References [ K. Prabakaran, P. Pavani, I. Ramadevi, J. Kumaravel, and P. anjeevikumar, D-D boost converter topologies for high voltage applications, in Proceedings of the National onference on Trends in Instruments and ystem Design Automation, Karunya University, oimbatore, India, 7.
8 Modelling and imulation in Engineering [ F.. uo and H. Ye, Positive output super-lift converters, IEEE Transactions on Power Electronics, vol. 8, no., pp. 5 3, 3. [3 Y. He and F.. uo, Analysis of uo converters with voltagelift circuit, IEE Proceedings: Electric Power Applications, vol. 5, no. 5, pp. 39 5, 5. [4 Y. He and F.. uo, tudy of slide mode controller for D- D converter, in Proceedings of the International onference on Power ystem Technology (POWERON 4), ingapore, November 4. [5 F.. uo and H. Ye, Ultra-lift uo-converter, in Proceedings of the International onference on Power ystem Technology (POWERON 4), vol., pp. 8 86, ingapore, November 4. [6 X. hen, F.. uo, and H. Ye, Modified positive output uo converters, in Proceedings of the 3rd IEEE International onference on Power Electronics and Drive ystems (PED 99), vol., pp. 45 455, Kowloon, Hong Kong, July 999. [7 F.. uo, uo-converters, a series of new D-D stepup (Boost) conversion circuits, in Proceedings of the nd IEEE International onference on Power Electronics and Drive ystems (PED 97), vol., pp. 88 888, ingapore, May 997. [8 F.. uo and X. F. hen, elf-lift D-D converters, in Proceedings of the nd IEEE International onference on Power Electronics Drives and Energy ystems for Industrial Growth (PEDE 98), vol., pp. 44 446, Perth, Australia, November- December 998. [9 F.. uo, uo-converters, voltage lift technique, in Proceedings of the 9th IEEE Annual Power Electronics pecialists onference (PE 98), vol., pp. 783 789, Fukuoka, Japan, May 998. [ F.. uo, Re-lift converter: design, test, simulation and stability analysis, IEE Proceedings: Electric Power Applications, vol. 45, no. 4, pp. 35 35, 998. [ F.. uo, Re-lift circuit: a new D-D step-up (Boost) converter, Electronics etters, vol. 33, no., pp. 5 7, 997. [ K. Ogata, Modern ontrol Engineering, Prentice-Hall, New Delhi, India, nd edition, 996. [3 K. M. medley and. uk, Dynamics of one-cycle controlled uk converters, IEEE Transactions on Power Electronics, vol., no. 6, pp. 634 639, 995. [4 M. H. Rashid, Power Electronics: ircuits, Devices and Applications, Prentice-Hall, Englewood liffs, NJ, UA, nd edition, 993.
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