TESTING OF AN 8-BIT SIGMA DELTA ADC BASED ON CODE WIDTH TECHNIQUE USING 45nm TECHNOLOGY

2016 International Conference on Micro-Electronics and Telecommunication Engineering TESTING OF AN 8-BIT SIGMA DELTA ADC BASED ON CODE WIDTH TECHNIQUE USING 45nm TECHNOLOGY Yogita Tembhre ME Research Scholar SSTC, SSGI (FET) Bhilai C.G, India yogitatembhre10@gmail.com Anil Kumar Sahu Assistant Professor SSTC, SSGI (FET) Bhilai C.G, India anilsahu82@gmail.com Abstract- A novel design is exhibited in the paper presented here for an analog-to-digital converter (ADC) built-in self test (BIST) scheme using code-width technique. An 8-bit sigma-delta ADC BIST scheme is introduced. The 8 bit sigma-delta ADC with arbitrary faults is simulated in the given BIST scheme designed in CMOS 45nm technology. Different parametric faults have been detected here such as Differential Non Linearity (DNL), monotonicity fault and missing code fault. This architecture of ADC BIST is achieved by Tanner EDA tool v15.0 using 45nm BSIM4 CMOS technology. The power dissipation of the BIST circuit is 18mW for the power supply of 1V. Index Terms BSIM4, Code-width, DNL, Monotonicity, Parametric faults, Sigma-delta ADC BIST. I. INTRODUCTION Built-in self-test (BIST) does not require external equipment for test application and testing can be performed not only at the manufacturing stage but also at every power-up or even during normal operation. -Modulators are popular in ADCs due to the high accuracy obtainable in low-cost standard CMOS technology. -ADCs are however difficult to test efficiently due to their requirement for high-resolution teststimulus. And due to their oversampling implementation they do not have a direct input to output relationship. Conventionally, test approaches for analog and mixed-signal blocks mainly target on functionality, which are both extravagant and tedious [10, 11]. High-resolution ADCs having high sampling rates are used in wide area of high performing applications, such as high-grade imaging systems, wireless communications, and radar. To deliver ADCs satisfying the requirements of the applications, it is obligatory that they are tested as less time as possible, but without negotiating the quality of the test. The analog to digital converter is the standard of the mixed circuit and this circuit is the most exclusive to test due both to the ADCs standard tests being quite long and to the high price of mixed signal testers and other test instruments. The use of BIST techniques relieves the dependency on costly test equipment and allows delivering low-cost devices [1]. ADC testing is can be classified into dynamic and static testing. The dynamic testing measures these parameters such as signal-to-noise ratios (SNR), harmonic distortion, inter modulation distortion and frequency response. The proposed BIST scheme is based on code-width measurement. Code- Width is defined as the width of the analog input signal which is correlated to 1-LSB digital output. The static testing includes these parameters measurement such as integral nonlinearity (INL), differential nonlinearity (DNL), gain, offset, missing code error, monotonicity fault, etc [5]. II. PREVIOUS WORK A Ramp Generation scheme is used previously is developed in order to conquer the slope variations in a simple and slow slope ramp generator due to technique alterations. The adaptive scheme exhibits satisfactory performance with view to ramp linearity and precise slope although maintaining a low area overhead [2, 8]. An on-chip analog ramp generator for ADC BIST based on modulator is described which uses the over-sampling and noise shaping to generate the on-chip accurate analog ramp with the accurate control of a calibrated ramp slope [3]. A numerical simulation is performed by applying the generated linear ramp to ADC and DAC with known DNL and INL values. The on-chip formation of linear ramp signals as test stimuli, and propose various techniques for calculating the DNL and INL of the converters are discussed [5,6]. A pipelined ADC employs analog pre-processing to divide the range of input signal into sub-intervals and amplification of an extra signal for further processing in the consecutive levels. To provide test time improvements an alternative method to histogram based analysis techniques is used here which is code width technique [7]. III. ADC BIST SCHEME The analog ramp signal is enforced to sigma-delta ADC as input, the ADC generates digital code as output corresponding to the input signal. With the digital code as response the error detector concludes whether the ADC has any arbitrary fault or not. The ramp signal generator should have higher linearity than the sigma-delta ADC under test [4]. The ramp test signal fluctuates within dynamic range of ADC for proper operation. Different types of static ADC errors and faults are defined in Fig. 1. The monotonocity fault is defined when the ADC output decreases though the test input signal is monotonically increasing. It is expressed as x (n) x (n-1) < 0. The missing 978-1-5090-3411-6/16 $31.00 2016 IEEE DOI 10.1109/ICMETE.2016.27 418 416

code fault is defined as the difference between the current ADC output response and the previous output exceeds 1 LSB when the slope of the ramp input is sufficiently low. All bits are ORed except the LSB of the subtractor output can detect the missing code fault. If the output of subtractor is larger than 1, then the code transition is larger than 1 LSB and it corresponds to missing code fault. It is expressed as: x (n) - x (n-1) > 2 LSB. Then the DNL error is defined by the difference between the measured code width and the ideal code width. It is expressed as: DNL (n) = (x (n) - xideal) / xideal [12]. Digital Response Max code Faultless DNL INL Faulty Fig 1: Different ADC faults and error TABLE I. ERRORS AND THEIR DEFINITIONS Missing Code Fault Monotonocity Fault V max Analog input other fault is differential nonlinearity error (DNL) can be detected by measuring the code width in the form of clock count with the help of the synchronous counter. DNL is tested by measuring the code width corresponding to each sample. If any difference in the count is present then it shows the DNL error. IV. PROPOSED CIRCUIT The proposed circuit of BIST comprises a ramp generator, register, subtractor, synchronous counter and other digital circuitry. The ramp generator, subtractor, counter is to be reset at the start. An 8 bit register is used to store the sigma-delta ADC output for one sample period. Then the subtractor calculates the variation between the current ADC output and the previous output which is reserved in the 8 bit register. By ORing the 8 bits of the subtractor output a transition of the ADC output is occurred. This difference indicates the missing code fault and monotonic behavior. The negative difference represents monotonic behavior whereas if the difference is greater than 1, indicates missing code fault which shows that the code transition exceeds 1-LSB. Digital output 1 at the output of the comparator indicates the missing code fault. The synchronous counter counts the number of clocks until the code transition occurs. When the transition is detected the synchronous counter count corresponds to the code width for the specific code. Once code width is observed the counter is reset for the next code width measurement and the present count is reserved in the register. A subtractor is used to assess the difference in the code width of the two successive codes. If subtractor indicates the difference at its output, DNL error is detected. Table I indicates the different types of static errors of ADC and their definitions. Sr. Parameters and Definition Detection method No. detected faults and errors 1. Transition - OR(B 0,...,B n-2) 2. Code width (Cw) - Clock counting until transition 3. Missing code error X i-x i-1>1 OR(B 1,...,B n-2) 4. Monotonocity fault X i-x i-1<0 Sign (B) 5. Code width fault Cw max>2cw min Sign(Cw max-shift left (Cw min)) The BIST scheme proposed in this paper is based on code width measurement. The two faults which include missing code error, monotonic behavior fault can be detected by measuring the inequality between the digital output of the current sample and the previous sample. If this difference is negative under any stage then it is the indication of the monotonic conduct of the sigma-delta ADC and this can be detected. If this difference is more than 1-LSB then this is the indication of missing code error and it can be detected. The Fig 2: Block diagram of proposed BIST 419 417

A. Sigma-Delta ADC Basically, the output of sigma-delta modulator is the result of repeated measurement of difference between the analog input and the output response which considered as feedback. The figure represents the schematic of first order sigma-delta ADC which includes difference amplifier; a comparator, an integrator, and a feedback loop accommodate 1-bit DAC [9]. The 1-bit output from the modulator will then be fed to the digital decimation filter to continue the process to get the final output of the ADC. In this paper first order sigma delta ADC is used as CUT (circuit under test). It includes first order modulator and second stage CIC filter for decimation filter. The performance parameters are given in the table II. TABLE II. PARAMETERS OF 8-BIT SIGMA-DELTA ADC PARAMETERS VALUE Technology 45nm Order of Modulator 1 Order of decimation filter 2 Supply voltage 1V Resolution 8 bit Average power consumed 6.7mW Fig 4: Output response of the Σ-Δ ADC 1) Modulator : The sigma delta ADC comprises of mainly a sigma delta modulator and decimation filter. Here in this paper single stage sigma delta modulator and second stage CIC filter is used for decimation filter. The modulator comprises of a comparator, an integrator, a 1-bit DAC with the feedback loop and an op-amp. The schematic and input and output response of the modulator is shown in the figures below. a) Op-Amp: Op-amp in the paper is two-stage CMOS opamp whose parameters and waveforms are given below. The first phase of the op-amp is used as differential input while the second stage is used for additional voltage gain. Fig 3: Schematic of first order Σ-Δ ADC Fig 5: Schematic of the two stage CMOS OP-AMP 420 418

B. Ramp Generator A ramp generator is designed according to the frequency required for the purpose of work and has a device with linear response to a constant excitation current, which is capacitor in this work. The length (L) and width (W) of transistors in ramp generator were decided by the selection of some parameters of the circuit such as operating frequency and maximum voltage. The maximum voltage value is 1 volt. It occurs due to technology and fabrication process. The capacitance of 0.8 pf was chosen for this topology, which in the progress of circuit assimilation represents an appreciable size of the capacitor [2]. Fig 6: Frequency response characteristic of the two stage CMOS OPAMP TABLE III. PARAMETERS OF OPAMP PARAMETERS VALUES Gain 25dB Gain bandwidth product 34.4279X Phase margin 266 Average Power consumed 2.54uW Fig 9: Schematic of Ramp generator Fig 7: Schematic of 1 st order sigma-delta modulator Fig 8: Input and output waveform of modulator Fig 10: Output Response of Ramp Generator 421 419

V. SIMULATION RESULTS AND DISCUSSION The proposed BIST circuit is verified using an 8-bit sigmadelta ADC with arbitrary faults such as open or short or some parametric variation. The error detector is designed with Tanner EDA tool v15.0 using 45nm BSIM4 CMOS technology. In practice, the fault coverage may be lower than the ideal simulation result because the test circuits do not cover all possible cases. The faults are also analyzed by varying the width to length ratio of the transistors of the operational amplifiers of the sigma-delta ADC. The waveforms are shown in below in fig 11 and fig 12. Figure 11 shows the waveform for input and output of OR gate represented as F. Whereas fig 12 shows the response waveforms for the faults namely missing code fault, montonocity fault and code width fault also known as DNL fault. Power consumed in the proposed BIST circuit is 18mW for the given power supply of 1V. As shown in the graph below it is observed that as the circuit is error free the value of the output response is zero. Fig 11: Input And Output Response of Proposed BIST circuit Fig 12: Waveform Showing the Absence of Errors in the Given BIST circuit VI. CONCLUSION Here, in this paper a BIST scheme for an 8 bit sigma-delta ADC has been presented. An 8 bit sigma-delta ADC is designed in 45 nm technology using Tanner EDA tool. The proposed scheme is based on code width testing. This scheme detects most of the catastrophic faults and parametric faults. The fault coverage of the scheme is trying to attain its maximum value. The transistor level design of the circuit is completed. The chip level design of the testing circuit has to be done. The paper proposes a new sigma-delta ADC BIST technique based on code width testing without a slopecalibrated ramp signal. Due to noise or any other uncertainty in the real circuit, the test can be performed several times, and in case if the fault detection is repeated, the BIST controller will finally decide that the ADC is faulty. ACKNOWLEDGMENT The authors would like to thank the management, SSTC SSGI institute for providing Tanner EDA Tool v15.0. REFERENCES [1] G. Evans, "ADC built-in-self-test based on a pseudorandom uniform noise generator," Design of Circuits and Integrated Circuits (DCIS), 2014 Conference on, Madrid, 2014, pp. 1-5. [2] Winkeler, Bruno, and Raimundo Freire. "Ramp Generator for ADC Built-In-Self Test." SForum, 2012. [3] W. Yong-Sheng, W. Jin-Xiang, L. Feng-Chang, Y. Yi-Zheng, Modulation Based On-Chip Ramp Generator for ADC BIST, WSEAS Int. Conf. on DYNAMICAL SYSTEMS and CONTROL, Venice, Italy, November 2-4, 2005, pp. 512-516. [4] Dongmyung Lee, Kwisung Yoo, Kicheol Kim, G. Han and Sungho Kang, "Code-width testing-based compact ADC BIST circuit," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, no. 11, Nov. 2004, pp. 603-606. [5] Jiun-Lang Huang, Chee-Kian Ong and Kwang-Ting Cheng, "A BIST scheme for on-chip ADC and DAC testing," Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings, Paris, 2000, pp. 216-220. [6] Anil Kumar Sahu, Vivek Kumar Chandra, G.R. Sinha, "System Level Behavioral Modeling of CORDIC Based ORA of Builtin-Self-Test for Sigma-Delta Analog-to-Digital Converter." International Journal of Signal and Image Processing Issues Vol. 2015, no. 1, pp. 37-44. [7] A. Barua, Md.Tausiff, A Code Width Built-In-Self Test Circuit For 8-bit Pipelined ADC, 21st International Conference on Systems Engineering, 2011, pp. 287-291. [8] J. Ramesh & K. Gunavathi, A Novel Linear Ramp Generator for Analog and Mixed Signal Built-In-Self-Test Applications, I J E E S R, 3(1) June 2013, pp. 21-32. [9] Anil Kumar Sahu, Vivek Kumar Chandra, G.R. Sinha, Improved SNR and ENOB of Sigma-Delta Modulator for Post Simulation and High Level Modeling of Built-in-Self-Test Scheme. International Journal of Computer Applications, 2014, pp. 11-14. [10] Lala, P. K., Morgan Kaufmann (2001). Self-checking and faulttolerant digital design. [11] Johns, D. A., & Martin, K. (2008). Analog integrated circuit design. John Wiley & Sons. [12] Keshk, Arabi. "Software-based BIST for analog to digital converters in SoC." 2nd International IEEE Workshop in Design and Test, 2007, pp. 189-192. 422 420