Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families

1 Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1. Introduction 2. Metal Oxide Semiconductor (MOS) logic 2.1. Enhancement and depletion mode 2.2. NMOS and PMOS inverter 2.3. CMOS logic 3. Emitter Coupled Logic (ECL) 3.1. ECL AND/NAND gate 3.2. ECL OR/NOR gate 3.3. ECL subfamilies 4. Interfacing with MOS and ECL devices 5. Summary Learning Objectives: 1. To understand CMOS and ECL logic 2. To understand working of basic logic gates of MOS logic and ECL 3. To get familiar with different subfamilies of MOS and ECL 4. To study characteristics and performance parameters 5. To understand how to interface ECL and MOS gates with other devices

2 1 Introduction: MOSFETs have become very popular for logic circuits due to a high density of fabrication and low power dissipation. When MOS devices are used in logic circuits, there can be circuits in which either only p- or only n-channel devices are used. Such circuits are referred to as PMOS and NMOS logic respectively. It is also possible to fabricate enhancement mode p-channel and n-channel MOS devices on the same chip. Such devices are referred to as complementary MOSFETs and logic based on these devices is known as CMOS logic. The power dissipation is extremely small for CMOS and hence, CMOS logic has become very popular. ECL is a high speed logic family based on bipolar junction transistor. It basically operates on current mode of operation. In this logic family, transistors are not allowed to go into deep saturation, which eliminates the storage delays. Transistors are driven either in cut-off or in active region. In this module, the focus is on understanding principle, construction, working and classification MOS and ECL families. 2. Metal Oxide Semiconductor (MOS) logic The MOS logic family is based on Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. As compared to bipolar logic families, the MOS families are simpler and low power devices. A field effect transistor is made by growing a very thin layer of SiO 2 over a semiconductor material. A metal such as aluminum is deposited over the dielectric layer of SiO 2 to obtain MOS device. 2.1 Enhancement and Depletion mode There are two types of MOSFETs a. Enhancement type MOSFET b. Depletion type MOSFET Just Similar to junction field effect transistors, there are n-channel as well as p-channel MOSFETs. N-channel devices are more popular than p-channel devices because of their higher speed. Basic principle of operation of p-channel and n-channel MOSFETs is the same. P-channel

3 MOSFETs are considered as obsolete for independent or individual devices but are found to be useful in complementary MOS (CMOS) technology. a. Enhancement MOSFET: Enhancement type MOSFETs are the popular switching devices in most MOS families. The basic structure of n-channel enhancement type MOSFET is shown in Figure 1. Source Gate Drain Source Gate Drain SiO 2 Metal n+ n+ P substrate Vgs n+ n+ P substrate Figure 1: n-channel MOSFET Source and drain are formed by two n-type regions which are diffused into a p-type substrate. A thin layer of silicon dioxide is grown over this and by masking, etching and metallization processes, metallic contacts are taken from the source and the drain. A metal gate is formed above the dielectric layer. Initially, without bias condition, has no channel between the source and the drain. A positive voltage greater than threshold voltage V T is applied at the gate. Due to this field from the gate, the electronics (minority charge carriers) from the substrate are attracted towards the gate between the source and the drain regions. In the process, they form an n channel by making the region between the source and the drain n type. This channel makes it possible for the electrons to flow from the source to the drain, when a positive voltage is applied at the drain. Since the application of a positive voltage at the gate enhances the channel width, this device is referred

4 to as an enhancement mode device or an enhancement MOSFET. An increase in the drain voltage increases the drain current thereby producing resistor type operation for small voltages similar to JFET. A pinch-off occurs, when the drain to source voltage is sufficiently large, which reduces the field near the drain to zero and makes the drain current relatively constant. These devices are normally OFF when Vgs=0 and can be turned ON by making Vgs greater than source voltage for n-mos or lesser than the source voltage for p-mos. b. Depletion MOSFET: Depletion MOS device is fabricated by diffusing n type of impurity between the two n-type regions, which acts as a channel between the source and the drain. In this device, current flows between drain and source even in the absence of a positive voltage at the gate. This causes depletion of the channel and hence it is called depletion MOSFET. The circuit symbol for n channel and p channel MOSFETs are shown in Figure 2.The depletion-mode MOSFETs are normally ON at zero gate-source voltage. Such devices are used as load resistors in logic circuits. D D G G S S (a) (b) Figure 2 Circuit Symbols of MOSFETs (a) Enhancement type n channel MOSFET (b) Enhancement type p channel MOSFET 2.2 NMOS and PMOS Inverter MOS logic family is simplest to fabricate and consumes less power because it requires only one basic element NMOS or PMOS FETs. IT does not require other devices like resistors or diodes. Due to ease of fabrication and low power dissipation, MOS family is most suited for VLSI applications.

5 NMOS iverter The basic NMOS gate is an inverter in Figure 3 in which T1 is an enhancement MOSFET which acts as driver and T2 is either an enhancement or depletion MOSFET which acts as a load. Instead of fabricating diffusion resistor for load, which usually occupies an area about 20 times that of a MOS device, MOSFET itself is used as the load. This enables a high density of fabrication, making large scale integration possible with the use of MOS logic. +Vdd T1 Y= Fig. 3 NMOS inverter T2 A When input is logic 1 i.e. +Vdd, T2 is ON and T1 is OFF and Y= logic 0 appears at the output. When input is logic 0, T2 is cut off and T1 is ON thus making output Y equal to Vdd i.e. logic 1. PMOS Inverter -Vdd T1 Y= T2 A Figure 4 PMOS Inverter

6 The PMOS logic family uses P-channel enhancement mode MOSFETS. An inverter circuit using PMOS logic is as shown in Figure 4. P channel MOSFET T1 acts as an active load for the MOSFET T2. Here, GND represents a logic 1 and VDD represent a logic 0 for a positive logic system. When the input is grounded (i.e. logic 1 ), T2 remains in a cut-off mode and VDD appears at the output through the conducting T1. When the input is at VDD or near VDD, T2 gets into the conducting mode, and the output goes to near-zero potential (i.e. at logic 1 ). 2.3 CMOS Logic The CMOS (Complementary Metal Oxide Semiconductor) logic family uses both N-type and Ptype enhancement type MOSFETs to realize different logic functions. These two MOSFETs are designed to have matching characteristics. The main advantage of the CMOS logic family over the bipolar logic families is an extremely low power dissipation. This is because, CMOS devices draw power only when they are switching. This allows integration of a much larger number of CMOS gates on a chip, than would have been possible with bipolar or NMOS technology. CMOS technology today is the dominant semiconductor technology used for making microprocessors, memory devices and application-specific integrated circuits (ASICs). CMOS Inverter +Vdd T1 Y= A T2 Figure 5 CMOS Inverter

7 CMOS inverter is the basic building block of CMOS logic. It consists of a pair of N-channel and P-channel MOSFETs connected in cascade configuration as shown in Figure 5. When the input is in the HIGH state (logic 1 ), P-channel MOSFET T1 is in the cut-off state or switched OFF, while the N-channel MOSFET T2 is conducting i.e. switched ON. The conducting MOSFET provides a path from ground to output and the output is LOW (logic 0 ). When the input is in the LOW state (logic 0 ), Q1 is in conduction while T2 is in cut-off. The conducting P-channel device provides a path for VDD to appear at the output, so that the output is in HIGH or logic 1 state. It is observee that, there is no conduction path between VDD and ground in either of the input conditions the logic 1 or 0 state.. Hence, there is practically zero power dissipation in static conditions. CMOS logic has different output configurations: a. CMOS with open drain output b. CMOS with tri-state output The outputs of conventional CMOS gates should not be shorted together. If the input conditions are such that the output of one inverter is HIGH and that of the other is LOW, the output circuit is like a voltage divider network with two identical resistors equal to the ON-resistance of a conducting MOSFET. At this point, the output is approximately equal to VDD/2, which lies in the indeterminate range and is therefore unacceptable. Similar to tristate TTL, CMOS devices are also available with tristate outputs. The operation of tristate CMOS devices is similar to that of tristate TTL. Unused inputs of CMOS devices should never be left floating or unconnected. A floating input is highly susceptible to picking up noise and accumulating static charge. This can often lead to simultaneous conduction of P-channel and N-channel devices on the chip, which causes increased power dissipation and overheating. Unused inputs of CMOS gates should either be connected to ground, or VDD or shorted to another input. CMOS ICs CMOS series 4000 was the first version of the family. It is now referred as 4000A-series. 4000B is improved version of the 4000A series and has higher current capabilities. In addition, 74C series is a pin to pin compatible with TTL series is also available.

8 BiCMOS Logic In BiCMOS logic family bipolar and CMOS devices are integrated on a single chip. It provides the advantages present in bipolar and CMOS logic families. The bipolar logic families such as TTL and ECL have the advantages of a faster switching speed and a larger output drive current capability and CMOS logic has the advantage of a lower power dissipation, a higher noise margin, and a larger packing density. BiCMOS logic attempts to get the best of both logic families. 3. Emitter coupled logic (ECL) ECL is a high speed logic family based on bipolar junction transistor. It basically operates on current mode of operation. In this logic family, transistors are not allowed to go into deep saturation, which eliminates the storage delays. Transistors are driven either in cut-off or in active region. The difference in the voltage levels corresponding to logic LOW and HIGH states, is kept small (typically 0.85 V), with the result that the output capacitance needs to be charged and discharged, by a relatively much smaller voltage. It is the fastest of all the logic families. Propagation delays are less than 1ns per gate. 3.1 ECL AND/NAND gate: Figure 6 shows internal schematic of ECL logic gate. It is divided into three sections viz. input stage, differential amplifier and output stage. These are referred to as emitter-coupled because, differential amplifier configuration has emitters of two transistors coupled together. As shown in the Figure, the circuit is divided into three parts: 1. Differential amplifier: It performs the logic operation. 2. Emitter followers: DC shifting of the inputs and outputs is performed so that, logic 0 voltage and logic 1 voltage will be same for inputs and outputs. 3. Output transistors are used in parallel with Q1 to get the required fan in.

9 R1 R2 Y=AB Y=AB+B=AB A Q1 I1 Q2 I2 B Q3 I3 Q4 I4 Iconst=I3+I4 Vref A B AND NAND -VEE Figure 6: Internal schematic of ECL AND/NAND logic gate In ECL, the positive end of the supply is connected to the ground and the other end to the negative of the supply. This is done to minimize the effect of noise induced in the power supply, as well as any accidental short protection developed between the output and ground. Due to this configuration, the voltage generated for logic 0 and logic 1 is negative. As seen in Figure, emitters of Q1(PNP) and Q2(PNP) are connected together and sum of currents I1 and I2 forms the collector current of transistor Q3(PNP) i.e. I3=I1+I2. The emitters of Q3 and Q3 are connected to constant current source Iconst=I3+I4. The base of transistors Q3 and Q4(PNP) are connected to fixed reference voltage Vref. Consider logic 0 as more negative voltage and logic 1 as less negative voltage which is nearly equal to 0V. Conditions for inputs A and B are tabulated as follows:

10 A B Y(AND) 0 (-ve) 0(-ve) 0(-ve) 0(-ve) 1(0V) 0(-ve) 1(0V) 0(-ve) 0(-ve) 1(0V) 1(0v) 1(0V) Consider A=0 and B=0 i.e. logic 0. Both the transistors Q1 and Q3 are ON, carrying more current. One can observe that I4 is constant and I3=I1+I2. Thus, in order make I const as constant I3 has to be adjusted so that Q3 would be more conducting or less conducting. This in turn makes Q2 more or less conducting and hence accordingly output would be more negative or less negative. This is true for all cases of A and B. 3.2 ECL OR/NOR gate: +Vcc Q8 Q6 Q7 OR NOR Q1 Q2 Q3 Q4 Q5 O/P O/P Y R EE A B C D A B C D Figure 7: ECL OR/NOR OR NOR

11 Figure 7 shows a typical internal schematic of an OR/NOR gate. The circuit comprises of a differential amplifier input circuit with one side of the differential pair, having multiple transistors depending upon the number of inputs to the gate, a voltage- and temperaturecompensated bias network and emitter follower outputs. Typical values of power supply voltages are VCC= 0 and VEE= 5.2 V. The nominal logic levels are logic LOW=logic 0 = 1.75 V and logic HIGH = logic 1 = 0.9 V, assuming a positive logic system. The bias network configured around transistor Q6 produces a voltage of typically 1.29V at its emitter terminal. This leads to a voltage of 2.09V at the junction of all emitter terminals of various transistors in the differential amplifier, assuming 0.8V to be the required forward-biased P N junction voltage. Now, let us assume that all inputs are in a logic 0 state, that is, the voltage at the base terminals of various input transistors is 1.75 V. This means that, the transistors Q1, Q2, Q3 and Q4 will remain in cut-off state since their base-emitter junctions are not forward biased by the required voltage. This leads us to infer that the transistor Q7 is conducting, producing a logic 0 output, and transistor Q8 is in cut-off, producing a logic 1 output. If any one or all of the inputs are driven to logic 1 status, that is, a nominal voltage of 0.9V is applied to the inputs, The base-emitter voltage differential of transistors, (Q1 Q4) exceeds the required forward-biasing threshold, with the result that these transistors start conducting. This leads to a rise in voltage at the common-emitter terminal, which now becomes approximately 1.7V, since the common-emitter terminal is now 0.8V more negative than the base terminal voltage. With rise in the common-emitter terminal voltage, the base-emitter differential voltage of Q5 becomes 0.31 V, driving Q5 to cut-off. The Q7 and Q8 emitter terminals respectively go to logic 1 and logic 0. This explains how the basic schematic functions as an OR/NOR gate. It should be noted that the differential action of the switching transistors (where one section is ON while the other is OFF) leads to a simultaneous availability of complementary signals at the output. 3.3 ECL Subfamilies There are many ECL subfamilies. They differ in characteristics like propagation delay, power dissipation per gate and speed. First ECL series i.e. MECL-I was marketed by Motorola.

Different subfamilies of ECL logic include MECL-II, MECL-III, MECL 10K, MECL 10H and MECL 10E were launched so far. 12 4. Interfacing In designing many complex digital applications it is necessary to connect signals from different ICs together. Interfacing means connecting outputs of one circuit or system to the inputs of another system with different electrical characteristics. In this section, the focus on inter converter circuits used to interface different logic families. ECL to TTL and TTL to ECL TTL-to-ECL and ECL-to-TTL interface connections are not simple because their power supply requirements differ widely. ECL devices have differential inputs and differential outputs. The special chips are available that address all these aspects. These are known as level translators. MC10124 is one such quad of TTL-to-ECL level translator. It consists of four independent single-input and complementary-output translators inside the chip as shown in Figure 8 MC10125 is a level translator for ECL-to-TTL interfaces. Input TTL ECL Output TTL to ECL Translator MC 10124 (a)

13 Input ECL ECL to TTL Translator TTL Output MC 10125 (b) Figure 8 Interfacing TTL to ECL and ECL to TTL CMOS and TTL are the two most popular and widely used logic families. Although ICs of the same logic family have no special interface requirements, which means that, one can directly connect the output of one to the input of the other, the same is not true if digital ICs belonging to different logic families are to be interconnected. Incompatibility of ICs belonging to different families mainly arises from different voltage levels and current requirements associated with LOW and HIGH logic states at the inputs and outputs. +5V Input Output CMOS LS TTL Figure 9 CMOS to LS TTL Interface

14 TTL-to-CMOS Interface In the TTL-to-CMOS interface, current compatibility is always present. The voltage level compatibility in the two states is a problem. VOH (min.) of TTL devices is too low as regards the VIH (min.) requirement of CMOS devices. When the two devices are operating on the same power supply voltage( 5 V), a pull-up resistor of 10 kῼ achieves compatibility. +5V 10K Input Output TTL CMOS Summary: Figure 10 Interfacing TTL to CMOS In this module, the CMOS and ECL logic families are discussed in details. Enhancement and depletion type are the basics modes of the MOS logic and PMOS and NMOS are two basic types of MOS devices. Out of these, NMOS is the most popularly used. However, use of complementary MOS is popular in order to reduce the circuit complexity and improve performance. Various basic CMOS logic gates such as inverter, NAND and NOR are discussed. ECL is a high speed logic family based on bipolar junction transistor. It basically operates on current mode of operation. In this family, the logic 1 is the voltage near 0V whereas the logic 0 is some negative voltage. There are number of subfamilies available to cater to the need of propagation delay and power dissipation. Interfacing the CMOS, ECL and TTL are discussed next and different interfacing circuits are presented. It is observed that interfacing ECL and CMOS is the most difficult due to different power requirements.