Department of Signal Theory and Communications UNIVERSITAT POLITÈCNICA DE CATALUNYA ALOE Framework and Tools Vuk Marojevic Ismael Gomez Antoni Gelonch ALOE Webinar. May 24th 212. http://flexnets.upc.edu/
ALOE Webinar. May 24th 212. http://flexnets.upc.edu/ LTE? SDR Application 2 (Waveform 2) SDR Application N (Waveform N) ARM μproc DSP ARM DSP DSP Core1 Core2 DSP core1 core2 Core1 Core2 DSP DSP Core3 Core4 DSP core3 core4 Core3 Core4 SDR Execution SDR Execution Environment Environment
ALOE Webinar. May 24th 212. http://flexnets.upc.edu/ Flexible Low Overhead Pipelined Execution + Online Mapping Simplified Scheduling Flexible Multiprocessing ALOE
ALOE Webinar. May 24th 212. http://flexnets.upc.edu/ Outline 1. ALOE Framework 2. Computing Resource Management 3. ALOE Tools 4. Waveform Development 5. Summary
ALOE Webinar. May 24th 212. http://flexnets.upc.edu/ 1.1 Lightweight Framework How to design a low-overhead framework? Language Standard C Memory Static (or custom pool) Scheduling Static, non-preemptive
1.2 ALOE Layers Abstract Application Layer Real Application Layer 1 2 3 m ALOE Layer Hardware Layer ALOE VIRTUAL PLATFORM ALOE ALOE ALOE PE1 PE2 PE2 PE: Processing Element
ALOE Webinar. May 24th 212. http://flexnets.upc.edu/ 1.3 ALOE Architecture ALOE Software Daemons MODULE API FRONT END SW LOAD STATS EXEC CTRL CMD MAN SW MAN SYNC MAST SW MAP ALOE Software Lib (service to modules) SYNC BRIDGE STATS MAN API ALOE Hardware Library (service to upper ALOE layers) API HARDWARE Operating System (optional)
ADC Rate Conv. ALOE Webinar. May 24th 212. http://flexnets.upc.edu/ 1.4 ALOE Time Management Time slots synchronized to ADC/DAC Relaxed synchronization Cooperative, static scheduling Deterministic latency Stage Stage 1 Stage 2 Stage 3 m1 m2 m4 m5 m3 Module mapped to processor 1 Module mapped to processor 2 ALOE daemons Processor 1 timeslot x-1 timeslot x timeslot x+1 m1 m2 m1 m2 m1 m2 Internal Link External Link f s f s ' Processor 2 m3 m4 m5 m3 m4 m5 m3 m4 m5
2. Computing Resource Management MANAGEMENT MODELING
2.1 SDR Platform Modeling Processing resources and requirements Inter-processor bandwidth resources and requirements Example: SDR Platform Model P 1 P 2 C 1 C 2 C 3 C 2 B P 3 C 3 MOPTS Million operations per time slot MBPTS Mega-bits per time slot C = (C 1, C 2, C 3 ) MOPTS B B B = B B MBPTS B B processor-internal bandwidths Abstraction layers provide computing resources & requirements in above units Availability of software modules for each processor type
4 4 MOPS Maximum Search 15.36 MOPS 15 MOPS 1 MOPS 2.2 Waveform: UMTS Downlink Receiver 13 MOPS DDS f s = 65 MHz 492 MOPS Sampling Rate 245 MOPS Matched 4 Filter 492 MOPS 245 MOPS Sampling Matched Rate Filter 4 f s = 15.36 MHz f s = 3.84 MHz 7.68 Mbps 46 MOPS Interpolator Decimator 3.84 MHz 12 MOPS Frequency Adjust Chip Sync f s = 61.44 MHz Ray Sync1 Search Sync2 1 MOPS Sync3 f = 1 KHz Sync1 Sync4.384 Mbps 1.15 Mbps 16 MOPS 4-Finger RAKE MRC Channel Estimation 92 MOPS DPCH Physical Channel De- Mapping 2 nd Deinterleaving CRC TrBk Concat./ CodeBk Deseg. Turbo Decoding Rate Matching 1 st Deinterleaving Radio Frame Desegmentation Physical Channel Desegmentation.2 MOPS 11.7 MOPS 342 MOPS 141 MOPS 116 MOPS 62.9 MOPS 1 MOPS
2.3 SDR Application Modeling 289 1-3 1.44 f 2 f 4 f 6 2.35 Time slot:.6 ms 2.35.578 76.5 1-3 9.4 1 27 1-3 7.6 1 94.1 1 MBPTS f -3-3 -3 7 72 1-3 72 1 f 2.35-3 1 f 1 f 11 f 13 f 15 f 3 289 1-3 MOPTS.578 f 8 9.4 1 f -6 5 2.35 1.44 36 1-3.145 f 9 9.4 1 f -6 12 f 14 588 1-6 54.1 1-3 5.88 1-3 f 16 f 24 226 1-6 226 1-6 677 1-6 677 1-6 f 23 f 22 f 21 f 2 677 1-6 f 19 4.5 1-3 f 18 4.5 1-3 f 17 118 1-6 6.88 1-3 21 1-3 82.9 1-3 (a) 68.2 1-3 37 1-3 5.88 1-3 61.8 1-3 Function model: c = (.76,.289,.289, 1.44, 1.44, 2.35, 2.35, ) MOPTS c T = 13.675 MOPTS.612.612.578.578 Dataflow model: b =.145 MBPTS con =.12.145 Stage model: s = (1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 6, 6, 7, 7, 8, 9, 1, 11, 12, 13, 14, 15, 16, 17)
2.4 The t w -mapping & Cost Function Dynamic programming Parameter w controls algorithm complexity Cost function independent control different resources define different optimization goals Two-term cost function: Cost = processing requirement available processing power + bandwidth requirement available bandwidth balance processing load minimize data flows V. Marojevic, Computing Resource Management in Software-Defined and Cognitive Radios, doctoral dissertation, Dept. Signal Theory and Communications, UPC, 29. ALOE Webinar. May 24th 212. http://flexnets.upc.edu/
Processors ALOE Webinar. May 24th 212. http://flexnets.upc.edu/ 2.4 The t w -mapping & Cost Function P 1 Waveform modules f i 1 f i f i +1 f i + w 2 f i+ w 1 P 2 P 3 origin reference window size w decision {P 1, f i } represents the mapping of waveform component f i to processor 17 P 1
ALOE Webinar. May 24th 212. http://flexnets.upc.edu/ 2.4 The t w -mapping & Cost Function Path costs f 1 f 3 f 4 P 1.5.7 f 2 Decision f 1 f 2 f 3 f 4 P 1.5 1.2.8 P 2.6 P 2.6 w = 1 f 1 f 2 f 3 f 4 P 1.5 1.2 2 2.7 f 1, f 2, f 4 P 1 P 2.6 1.5 1.7 f 3 P 2
3. ALOE Tools Development and Debugging Tools ALOE lab sessions Source code templates Automatic code generation tools (Simulink Target) Graphical user interface
3.1 Graphical User Interface (I) Execution control Execution time statistics Parameter time evolution Loaded modules Schedule Module Output Parameter modification
3.1 Graphical User Interface (II) Computing platform Processor loads Task schedule
4. Waveform Development Data Source Three bit streams CRC attachment Turbo encoder Interleaving Rate matching Mapping OFDM modulator DUC Cyclic ifft Pilot Depilot & equalization OFDM demodulator FFT DeCyclic Sync DDC LTE-128 points. 1 MHz 3 bit-streams Turbo decoder Soft demapper Rate matching Interleaving DEMUX Turbo decoder MUX CRC dettachment Sink Turbo decoder
4.1 Processing Platforms DAC/ADC DAC/ADC RF RF P1 P2 P1 P2 GbE P5 P6 P3 P4 P7 P8 P3 P4 GbE GbE i7 Quad-Core, 2,6 GHz ADC/DAC board: Innovative Integration X5-4 Sampling Rate: 61,44 MHz Time-slot: 2 ms. E2E-latency: 4 ms. P9 P11 P1 P12
4.2 Signal Captures DA output (time and frequency domain) Sync module output: Correlation with Zhou sequence OK NOK DDC output Samples
ALOE Webinar. May 24th 212. http://flexnets.upc.edu/ 5. Summary ALOE Project Open source framework for SDR Non-commercial research version Tested: GPPs under Linux (x86 and ARM7) DSPs under RTOS-BIOS (TMS C64xx) UMTS bit-level, LTE (1 MHz) Documentation and downloads at http://flexnets.upc.edu/