ELEN 610 Data Converters

Spring 2014 S. Hoyos-ECEN-610 1 ELEN 610 Data Converters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group

Folding Spring 2014 S. Hoyos-ECEN-610 2

Spring 2014 S. Hoyos-ECEN-610 3 Inefficiency of Flash ADC V FS V i Strobe 2 N -1 f s Encoder D o D o 2 N -1 comparators 0 V FS V i Only comparators in the vicinity of V in are active at a time low efficiency.

Spring 2014 S. Hoyos-ECEN-610 4 Segmented Quantization 2 N -1 V FS D o 0 1 2 3 4 5 6 7 8 Segment indicator (M bits) V i Analog pre-processing divides V in into 2 M uniformly-spaced segments. Fine quantization (N-M) bits

Spring 2014 S. Hoyos-ECEN-610 5 Signal Folding 2 N -1 V FS D o Analog pre-processing folding amplifier Folding factor (F) is equal to the number of folded segments. 0 1 2 3 4 5 6 7 8 V i Fine quantization N-log 2 (F) bits Segment indicator (log 2 (F) bits)

Spring 2014 S. Hoyos-ECEN-610 6 Folding ADC Architecture V R V i Reference Ladder Fine ADC Coarse ADC MSB s F = 8 5 bits LSB s 3 bits Digital Logic 8 bits D out The fine ADC performs amplitude quantization on the folded signal. The coarse ADC differentiates which segment V in resides in.

Spring 2014 S. Hoyos-ECEN-610 7 Folding Amplifier R L R L V o + V o - F = 3 M 1 M 2 M 3 M 4 M 5 M 6 I S V R 1 I S V R 2 I S V R 3 V i V o I S R L 0 V i -I S R L V R /6 V R /2 5V R /6

Spring 2014 S. Hoyos-ECEN-610 8 Signal Folding Pros Folding reduces the comparator number by the folding factor F, and also reduces the number of preamplifiers by F but adds F folder amplifiers. Cons Multiple differential pairs in the folder increases the output loading. Frequency multiplication at the folder output.

Spring 2014 S. Hoyos-ECEN-610 9 Frequency Multiplication f max fin sin 1 (2 ) F

Spring 2014 S. Hoyos-ECEN-610 10 Folding Amplifier R L R L V o + V o - F = 3 M 1 M 2 M 3 M 4 M 5 M 6 V i I S V R 1 I S V R 2 I S V R 3 Zero-crossings are still precise! V o I S R L 0 V i -I S R L V R /6 V R /2 5V R /6

Spring 2014 S. Hoyos-ECEN-610 11 Zero-Crossing Detection V o 0 V i F = 3, P = 4 Only detect zero-crossings instead of fine amplitude quantization insensitive to folder nonlinearities. P parallel folding amplifiers are required.

Spring 2014 S. Hoyos-ECEN-610 12 Offset Parallel Folding V R V i F = 3, P = 4 Folder 1 V 1 c 0 V i Reference Ladder Folder 2 V 2 Folder 3 V 3 c c 0 0 V i V i Folder 4 V 4 c 0 V i Total # of zero-crossings = Total # of preamps = P*F Parallel folding saves the # of comparators, but not the # of preamps still large C in.

Spring 2014 S. Hoyos-ECEN-610 13 Folding + Interpolation V i Cross-connect P & N sides at the endpoints c V i

Spring 2014 S. Hoyos-ECEN-610 14 Rounding Problem V o 0 V i F = 3 2 2(V gs -V th ) V o 0 V i F = 9 2 2(V gs -V th ) Large F results in signal rounding, causing gain and swing loss. Max. folding factor is limited by V ov of folder and supply voltage.

Spring 2014 S. Hoyos-ECEN-610 15 Folding vs. Interpolation/Averaging Folding Folding works better with non-overlapped active regions between adjacent folders. Large V ov (for high speed) of folders and low supply voltage limit the max. achievable F. Interpolation/Averaging Work better with closely spaced overlapped active region between adjacent folding signals. Observation Small F and large P (parallel folders) will help both folding and interpolation/averaging, but introduces large C in. What else can we do?

Spring 2014 S. Hoyos-ECEN-610 16 Cascaded Folding V o 0 V i F = 3 c V o 0 V i F = 9 Ideal: A large folding factor F can be developed successively. Small F in the 1 st -stage folder large V ov, less capacitive loading, and less frequency multiplication effect.

Spring 2014 S. Hoyos-ECEN-610 17 Cascaded Folder Architecture (I) F =? Gilbert four-quadrant multiplier based folding amplifier Only works with even P, requires a lot of headroom

Spring 2014 S. Hoyos-ECEN-610 18 Cascaded Folder Architecture (II) F =? V o + V o - V i Simple differential pair-based folding amplifiers Only works with odd P, compatible with low supply voltage.

Spring 2014 S. Hoyos-ECEN-610 19 Mechanical Model of Cascaded Folding Bult (JSSC 97)

Spring 2014 S. Hoyos-ECEN-610 20 Distributed Preamplification Comparators Interpolation and Averaging Interpolation and 2 nd -stage Folding 1 st -stage Folding and Averaging c c c Gain Input and Reference Ladder c Large signal gain developed gradually along the signal path from soft to hard decision

Spring 2014 S. Hoyos-ECEN-610 21 Cascaded Offset Bit Alignment V R V i Reference Ladder 1 st -stage Folders (P*F1) 2 nd -stage Folders (F2) Fine Comparators LSB s Digital Logic D out F1 Cmp s P Cmp s Bit Alignment MSB s Two-step offset bit alignment large offset tolerance on F 1 coarse comparators and medium tolerance on P comparators.

Spring 2014 S. Hoyos-ECEN-610 22 Useful Formulas Assuming a two-stage cascaded folding & interpolating ADC, F 1 = 1 st -stage folding factor, F 2 = 2 nd -stage folding factor, P = # of offset parallel folders (P>F 2 ), I = total interpolation factor, then total # of decision level = P*F 1 *I, ADC Resolution = Log 2 (P*F 1 *I), total # of preamps in 1 st folder = P*F 1, total # of preamps in 2 nd folder = P, total # of fine comparators = P*I/F 2, total # of coarse comparators = F 1 *F 2, F 1 +F 2, or F 1 +P?

Spring 2014 S. Hoyos-ECEN-610 23 Cascaded Offset Bit Alignment V i A B C D V FS 0 D C B A 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Margin A OF UF 5 4 3 2 1 F 1 coarse comparators at input and P coarse comparators at 1 st -stage folder outputs resolve F 1 *P (>F 1 *F 2 ) folds. One fine comparator output is utilized to perform offset bit alignment.

Spring 2014 S. Hoyos-ECEN-610 24 References 1. R. J. van De Plassche et al., JSSC, vol. 14, pp. 938, issue 6, 1979. 2. R. E. J. van De Grift et al., JSSC, vol. 19, pp. 374-378, issue 3, 1984. 3. R. E. J. van De Grift et al., JSSC, vol. 22, pp. 944-953, issue 6, 1987. 4. R. J. van de Plassche et al., JSSC, vol. 23, pp. 1334-1344, issue 6, 1988. 5. J. van Valburg et al., JSSC, vol. 27, pp. 1662-1666, issue 12, 1992. 6. B. Nauta et al., JSSC, vol. 30, pp. 1302-1308, issue 12, 1995. 7. A. G. W. Venes et al., JSSC, vol. 31, pp. 1846-1853, issue 12, 1996. 8. M. P. Flynn et al., JSSC, vol. 31, pp. 1248-1257, issue 9, 1996. 9. P. Vorenkamp et al., JSSC, vol. 32, pp. 1876-1886, issue 12, 1997. 10. K. Bult et al., JSSC, vol. 32, pp. 1887-1895, issue 12, 1997. 11. M. P. Flynn et al., JSSC, vol. 33, pp. 1932-1938, issue 12, 1998. 12. M.-J. Choe et al., VLSI, 1999, pp. 81-82. 13. R. C. Taft et al., JSSC, vol. 39, pp. 2107, issue 12, 2004.

Nyquist-Rate ADC s Word-at-a-time (1 step) Flash Folding Interleaving Level-at-a-time (2 N steps) Integrating (Serial) Bit-at-a-time (N steps) Successive approximation Algorithmic (Cyclic) Partial word-at-a-time (1<M N steps) Subranging Pipeline the number in the parentheses is the latency of conversion, not throughput. Spring 2014 S. Hoyos-ECEN-610 25

Spring 2014 S. Hoyos-ECEN-610 26 Resolution-Conversion Speed Tradeoff Resolution [Bits] 20 Integrating 1 level/t clk 1 word/osr*tclk 1 bit/t clk 15 Oversampling Partial word/t clk 10 5 Nyquist Oversampling Successive Approximation Algorithmic Subranging Pipeline 1 word/t clk Flash Folding & Interpolating Interleaving 0 1k 10k 100k 1M 10M 100M 1G 10G Sample Rate [Hz]

Integrating ADC Spring 2014 S. Hoyos-ECEN-610 27

Spring 2014 S. Hoyos-ECEN-610 28 Single-Slope Integrating ADC V i V Y V X f clk Control Counter D o I C Counter keeps counting until comparator output toggles. Simple, inherently monotonic, but very slow (2 N *T clk /sample).

Spring 2014 S. Hoyos-ECEN-610 29 Single-Slope Integrating ADC V X slope=i/c V Y t V i I C D o t 1 1, Do Tclk C I T clk t V. i t 1 start stop t INL depends on the linearity of the ramp signal. Precision capacitor (C) and current source (I) are required. Comparator must handle large common-mode input.

Spring 2014 S. Hoyos-ECEN-610 30 Dual-Slope Integrating ADC C V i -V R R V X Control Counter D o f clk CT RC integrator replaces the current integrator. Input and reference voltages experience the same signal path. Comparator only detects zero-crossing (constant input CM).

Spring 2014 S. Hoyos-ECEN-610 31 Dual-Slope Integrating ADC V X V os V m t 1 t 2 1 2 t V m Vin RC D o t 1 N N 2 1 VR t2 RC t2 V t V 1 in R. Exact values of R, C, and T clk are not required. Comparator offset doesn t matter. Op-amp offset introduces gain error and offset. Op-amp nonlinearity introduces INL error.

Spring 2014 S. Hoyos-ECEN-610 32 Subranging Dual-Slope ADC SHA V t V i C 1 C S V X C 2 f clk Control Logic Cnt 1 (8 bits) Carry Cnt 2 (8 bits) MSB s LSB s I I 256 Much faster conversion speed. Two matched current sources and two comparators are required.

Spring 2014 S. Hoyos-ECEN-610 33 Subranging Dual-Slope ADC V X V t 1 2 t 1 t 2 t dvx dt dvx dt D o 1 2 N I, C I. 256C W 1 N 2 Precise V t is not required if carry is propagated. Matching between the current sources is critical if I 1 = I, I 2 = (1+δ) I/256, then δ 0.5/256.

Spring 2014 S. Hoyos-ECEN-610 34 Subranging Multi-Slope ADC SHA V i C S V X Cnt 1 4 Bits f clk Control Logic Cnt 2 4 Bits I I 16 I 256 Cnt 3 4 Bits Ref: J.-G. Chern and A. A. Abidi, "An 11 bit, 50 ksample/s CMOS A/D converter cell using a multislope integration technique," in Proceedings of IEEE Custom Integrated Circuits Conference, 1989, pp. 6.2/1-6.2/4.

Spring 2014 S. Hoyos-ECEN-610 35 Subranging Multi-Slope ADC V X 1 2 3 t dvx dt dvx dt dvx dt 1 2 3 I, C I, 16C I. 256C t 1 t 3 t 2 D o N1 W1 N2 W2 N3 Single comparator detects zero-crossing. Comparator response time is greatly relaxed. Matching between the current sources is still critical.

Spring 2014 S. Hoyos-ECEN-610 36 Successive Approximation ADC

Spring 2014 S. Hoyos-ECEN-610 37 Successive Approximation ADC V i V X V DAC b 1 DAC...... D o b N Shift Register Binary search algorithm N*T clk to complete N bits. Conversion speed is limited by comparator, DAC, and SAR (successive approximation register)

Spring 2014 S. Hoyos-ECEN-610 38 Binary Search V DAC V i V FS V FS 2 0 1 0 0 1 1 0 MSB T clk LSB t DAC output gradually approaches the input voltage. Comparator differential input gradually approaches zero.

Spring 2014 S. Hoyos-ECEN-610 39 Charge Redistribution SA ADC Φ 1e V X 8C 4C 2C C C SAR D o V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 4-bit binary-weighted capacitor array DAC. Capacitor array samples input when Φ 1 is asserted (bottom-plate).

Spring 2014 S. Hoyos-ECEN-610 40 Charge Redistribution (MSB) SAR D o Φ 1e V X 2C C C 8C 4C V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 i R j j j j i R X j j X X R j j i V V C C V C V V C V C V V C V 2 4 0 4 0 4 3 0 4 4 0

Spring 2014 S. Hoyos-ECEN-610 41 Comparison (MSB) V X 1 0 t Sample 1 MSB MSB TEST : V X V 2 R V i If V X < 0, then V i > V R /2, and MSB = 1, C 4 remains connected to V R. If V X > 0, then V i < V R /2, and MSB = 0, C 4 is switched to ground.

Spring 2014 S. Hoyos-ECEN-610 42 Charge Redistribution (MSB-1) Φ 1e V X 8C 4C 2C C C SAR D o V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 V i 16C V R VX 12C VX 4C VX V R 12C Vi 16C 16C VR Vi 3 4

Spring 2014 S. Hoyos-ECEN-610 43 Comparison (MSB-1) V X 1 2 0 t Sample 1 0 MSB MSB TEST : V X 3 V 4 R V i If V X < 0, then V i > 3V R /4, and MSB-1 = 1, C 3 remains connected to V R. If V X > 0, then V i < 3V R /4, and MSB-1 = 0, C 3 is switched to ground.

Spring 2014 S. Hoyos-ECEN-610 44 Charge Redistribution (Other Bits) Φ 1e V X 8C 4C 2C C C SAR D o V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 Test completes when all four bits are determined w/ four charge redistributions and comparisons.

Spring 2014 S. Hoyos-ECEN-610 45 After Four Clock Cycles V X 1 2 3 4 0 t Sample 1 0 0 1 MSB LSB Usually, half T clk is allocated for charge redistribution and half for comparison + digital logic. V X always converges to 0 (V os if comparator has nonzero offset).

Spring 2014 S. Hoyos-ECEN-610 46 Bottom-Plate Parasitics Φ 1e C P 8C 4C 2C C C V os SAR D o V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 If V os = 0, C P has no effect; otherwise, C P attenuates V X. AZ can be applied to the comparator to reduce offset.

Spring 2014 S. Hoyos-ECEN-610 47 Summary on SA ADC Power efficiency only comparator consumes DC power. DAC nonlinearity limits the INL and DNL of the SA ADC N-bit precision requires N-bit matching from the cap array. Calibration can be performed to remove mismatch errors (Lee, JSSC 84). If C P =0, comparator offset V os introduces an input-referred offset V os ; for nonzero C P, input-referred offset is larger than V os (δ~c P /ΣC j ). If V os =0, CP has no effect (V X 0 at the end of search); otherwise, charge sharing occurs at summing node (V X is attenuated). Binary search is sensitive to intermediate errors made during search DAC must settle into ½ LSB within the time allowed. Comparator offset must be constant (no hysteresis). Nonbinary search can be used (Kuttner, ISSCC, 2002).

Spring 2014 S. Hoyos-ECEN-610 48 References 1. R. E. Suarez, P. R. Gray, and D. A. Hodges, JSSC, pp. 379-385, issue 6, 1975. 2. J. L. McCreary and P. R. Gray, JSSC, pp. 371-379, issue 6, 1975. 3. H.-S. Lee, D. A. Hodges, and P. R. Gray, JSSC, pp. 813-819, issue 6, 1984. 4. M. de Wit, K.-S. Tan, and R. K. Hester, JSSC, pp. 455-461, issue 4, 1993. 5. C. M. Hammerschmied and H. Qiuting, JSSC, pp. 1148-1157, issue 8, 1998. 6. S. Mortezapour and E. K. F. Lee, JSSC, pp. 642-646, issue 4, 2000. 7. G. Promitzer, JSSC, pp. 1138-1143, issue 7, 2001. 8. F. Kuttner, ISSCC, 2002, pp. 176-177.

Algorithmic ADC Spring 2014 S. Hoyos-ECEN-610 49

Spring 2014 S. Hoyos-ECEN-610 50 Algorithmic (Cyclic) ADC V i SHA V X 2X V o Sample mode 1-b V FS /2 V FS /2 DAC 0 b j Input is sampled first, then circulates in the loop for N clock cycles. Conversion takes N cycles with one bit resolved in each T clk.

Spring 2014 S. Hoyos-ECEN-610 51 Modified Binary Search Algorithm V i SHA V X 2X V o Conversion mode 1-b V FS /2 V FS /2 DAC 0 b j If V X < V FS /2, then b j = 0, and V o = 2*V X. If V X > V FS /2, then b j = 1, and V o = 2*(V X -V FS /2).

Spring 2014 S. Hoyos-ECEN-610 52 Modified Binary Search Algorithm V X 1 X2 2 X2 3 X2 4 X2 5 X2 6 V FS V i V FS 2 0 1 0 0 1 1 0 MSB LSB T clk Constant threshold (V FS /2) is used for each comparison. 2X gain is provisioned each time residue circulates around the loop.

Spring 2014 S. Hoyos-ECEN-610 53 Loop Transfer Function V o V i SHA V X 2X V o c V FS b j =0 b j =1 1-b V FS /2 V FS /2 DAC 0 b j 0 V FS /2 V FS V i If V X < V FS /2, then b j = 0, and V o = 2*V X. If V X > V FS /2, then b j = 1, and V o = 2*(V X -V FS /2).

Spring 2014 S. Hoyos-ECEN-610 54 Offset Errors Ideal RA offset CMP offset V o V o V o V FS b=0 b=1 V FS b=0 b=1 V os V FS b=0 b=1 V os 0 V FS /2 V FS V i 0 V FS /2 V FS V i 0 V FS /2 V FS V i D o D o D o 0 V FS /2 V FS V i V FS /2 V i 0 V FS 0 V FS /2 V FS V i V o = 2*(V i - b j *V FS /2) V i = b j *V FS /2 + V o /2

Spring 2014 S. Hoyos-ECEN-610 55 The Multiplier DAC (MDAC) Φ 2 V i Φ 1 C 1 -V R /4 Φ 1 C 2 A V o V R /4 Φ 1e -V R 0 V R Decoder Φ 2 2X gain + 3-level DAC + subtraction all integrated. A 3-level DAC is perfectly linear w/ fully-differential signals.

Spring 2014 S. Hoyos-ECEN-610 56 The 1.5-Bit Architecture V R V R /2 -V R /2 -V R b=0 b=1 b=2 V o 0 00 01 10 -V R /4 V R /4 V R V i 3 decision levels ENOB = log 2 3 = 1.58. Max tolerance on comparator offset is ±V R /4. An implementation of the Sweeny-Robertson-Tocher (SRT) division principle. The conversion accuracy solely relies on the loopgain error, i.e., the gain error and nonlinearity. A 3-level DAC is required. Architecture can be generalized to n.5-b per conversion.

Spring 2014 S. Hoyos-ECEN-610 57 Error Mechanisms of RA Φ 1 C 1 Φ 2 V o C1 C C 1 2 V i C C 2 b 1 VR 1 V i -V R /4 V R /4 Φ 1 C 2 Φ 1e A V o Capacitor mismatch Op-amp finite-gain error and nonlinearity -V R 0 V R Decoder Φ 2 Charge injection and clock feedthrough Finite circuit bandwidth V o t C C V b 1 2 C 1 i 1 C C1 C2 A V o 2 V R ΔV V i

Spring 2014 S. Hoyos-ECEN-610 58 RA Gain Error and Nonlinearity V R V R /2 b=0 b=1 b=2 V o D o 0 V i -V R /2 -V R -V R /4 V R /4 V R 0 -V R V i V R Raw accuracy is usually limited to 10-12 bits w/o error correction.

Spring 2014 S. Hoyos-ECEN-610 59 1 N 1 N 2 1 1 0 N 2 b 2 b 2 b b 2 1 Do 1 N 1 N 2 1 1 0 N 3 b 3 b 3 b b 3 2 Do 1 bit and 1.5-b with Offset Tolerance 1.5-b without Offset Tolerance

Effect of Offset Spring 2014 S. Hoyos-ECEN-610 60

Effect of Offset Spring 2014 S. Hoyos-ECEN-610 61

Spring 2014 S. Hoyos-ECEN-610 62 References 1. P. W. Li, et al., JSSC, vol. 19, pp. 828-836, issue 6, 1984. 2. C. Shih, et al., JSSC, vol. 21, pp. 544-554, issue 4, 1986. 3. H. Ohara, et al., JSSC, vol. 22, pp. 930-938, issue 6, 1987. 4. H. Onodera, et al., JSSC, vol. 23, pp. 152-158, issue 1, 1988. 5. B.-S. Song, et al., JSSC, vol. 23, pp. 1324-1333, issue 6, 1988. 6. B. Ginetti, et al., JSSC, vol. 27, pp. 957-964, issue 7, 1992. 7. S. H. Lewis, et al., JSSC, vol. 27, pp. 351-358, issue 3, 1992. 8. A. N. Karanicolas, et al., JSSC, vol. 28, pp. 1207-1215, issue 12, 1993. 9. H.-S. Lee, JSSC, vol. 29, pp. 509-515, issue 4, 1994. 10.S.-Y. Chin et al., JSSC, vol. 31, pp. 1201-1207, issue 8, 1996. 11.O. E. Erdogan, et al., JSSC, vol. 34, pp. 1812-1820, issue 12, 1999.

Spring 2014 S. Hoyos-ECEN-610 63 Algorithmic ADC Hardware-efficient, but relatively low conversion speed. Binary search algorithm. Loopgain (2X) requires the use of a residue amplifier, but greatly simplifies the DAC 1-bit, inherently linear. Residue gets amplified each time it circulates the loop; the gain makes the later conversion steps (the LSB s) insensitive to circuit noise and distortion. Conversion errors (residue error due to loopgain nonidealities and comparator offset) made in the earlier conversion cycles also get amplified again and again overall accuracy is usually limited by the MSB resolving and residue generation step. Digital redundancy is often used to treat comparator/loop offsets. Trimming/calibration/ratio-independent techniques are often used to treat loopgain error.

Precision Techniques Spring 2014 S. Hoyos-ECEN-610 64

Spring 2014 S. Hoyos-ECEN-610 65 Ratio-Independent Multiply-By-N Circuit (1) (2) (3) C 2 C 2 C 1 C 1 C 1 C 2 V i A V o (1) V o (2) A A V o (3) Sampling Charge transfer C 1 -C 2 exchanged Steps (1) and (2) are repeated for N times. C 2 functions as a temporary charge storage.

RA Gain Trimming V i + C 1 C 2 Trim array V X + V X - A V o + V o - C 1 /C 2 = 2 nominally V i - C 1 C 2 Precise gain-of-two is achieved by adjustment of the trim array. Finite-gain error of op-amp is also compensated (not nonlinearity). Spring 2014 S. Hoyos-ECEN-610 66

Spring 2014 S. Hoyos-ECEN-610 67 Split-Array Trimming DAC V i + 1.2C 2C V X + C 2C 4C 8C C 2C 4C 8C 8-bit gain setting + sign C 2C 4C 8C C 2C 4C 8C V i - 1.2C 2C V X - Successive approximation is performed to find the correct gain setting. Coupling cap is slightly increased to ensure segment overlap.

Spring 2014 S. Hoyos-ECEN-610 68 Digital Calibration V R MSB=0 V o MSB=1 D o S 1 S 2 MSB=1 0 V i MSB=0 S 1 S 2 0 -V R V R -V R V i V R RA gain is set lower than 2X, forcing missing codes but NOT missing decision levels. Calibration is performed by measuring distance between S 1 and S 2 ; (S 2 -S 1 ) is later subtracted from D o (gain error and offset remain).

Spring 2014 S. Hoyos-ECEN-610 69 Digital Calibration Φ 1e Φ 2 C 3 Φ 2 Φ 1 C 2 Φ 1e C 1 = C 2 V i -V R V R Decoder Φ 1 C 1 Φ 2 Residue Amplifier A V o V o C 3 = βc 1 AZ SC amplifier C C V 2b 1 2 C 2 C 2Vi 2b1 V 1 β i R 3 1 C V 1 R

Capacitor Error-Averaging Φ 1 Φ 2 Φ 3 C 1 C 1 C 2 C 2 C 2 C 1 V i V R V x1 V R V x2 A 1 A 1 A 1 V x 1 1 δ C, C2 1 +Δ -Δ 2V i -V R V x1 C 1 C2 Vi C 1 C 2 V R 2V i V R δv V, i R Φ 1 Φ 2 V x 2 C C Φ 3 V x2 1 Vi C 2 2 C V 1 R 2V i V R δv V. i R Inherently linear capacitor error-averaging techniques for pipelined A/D conversion Yun Chiu;Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 47, Issue 3, March 2000 Page(s):229-232 Spring 2014 S. Hoyos-ECEN-610 70

Spring 2014 S. Hoyos-ECEN-610 71 Capacitor Error-Averaging Φ 2 Φ 3 C 3 C 3 C 4-1 C 4 V x1-1 V x2 V o A 2 A 2 V o C 3 2C4, 2V i -V R C C V C V C, Vx1 3 4 o 3 x2 4 Φ 1 Φ 2 Φ 3 V o V x1 V 2 x2 2V i V R,

Spring 2014 S. Hoyos-ECEN-610 72 Capacitor Error-Averaging C C1 C C1 1 δ 1 2 δ 2 C 2C1 C C1 3 δ 3 4 δ 4 Assume,,, δ, are zero mean Gaussian with variance. δ1 δ δ 2 3 4 2 Find an expression for Vo and comment on the effectiveness of the capacitor error-averaging technique.

Spring 2014 S. Hoyos-ECEN-610 73 References 1. P. W. Li, et al., JSSC, vol. 19, pp. 828-836, issue 6, 1984. 2. C. Shih, et al., JSSC, vol. 21, pp. 544-554, issue 4, 1986. 3. H. Ohara, et al., JSSC, vol. 22, pp. 930-938, issue 6, 1987. 4. H. Onodera, et al., JSSC, vol. 23, pp. 152-158, issue 1, 1988. 5. B.-S. Song, et al., JSSC, vol. 23, pp. 1324-1333, issue 6, 1988. 6. B. Ginetti, et al., JSSC, vol. 27, pp. 957-964, issue 7, 1992. 7. S. H. Lewis, et al., JSSC, vol. 27, pp. 351-358, issue 3, 1992. 8. A. N. Karanicolas, et al., JSSC, vol. 28, pp. 1207-1215, issue 12, 1993. 9. H.-S. Lee, JSSC, vol. 29, pp. 509-515, issue 4, 1994. 10.S.-Y. Chin et al., JSSC, vol. 31, pp. 1201-1207, issue 8, 1996. 11.O. E. Erdogan, et al., JSSC, vol. 34, pp. 1812-1820, issue 12, 1999.

Subranging ADC Spring 2014 S. Hoyos-ECEN-610 74

Spring 2014 S. Hoyos-ECEN-610 75 Subranging ADC Architecture V RT V RB Coarse Encoder MSB s V i Fine Flash Coarse Flash Fine Encoder LSB s

Spring 2014 S. Hoyos-ECEN-610 76 Subranging ADC Pros Reduced complexity 2*(2 N/2-1) comparators Reduced C in, area, and power consumption No residue amplifier required Cons Typically 3 clock phases per conversion Sample Coarse comparison Fine comparison THA required (two-stage S/H if the front-end SHA only holds for one phase) Offset tolerance on fine comparators is at N-bit level. Offset tolerance on coarse comparators is also at N-bit level without digital redundancy.

Spring 2014 S. Hoyos-ECEN-610 77 Example Block Diagram V RT V i Reference Ladder MUX SHA SHA Coarse ADC Fine ADC MSB s 4 bits LSB s 5 bits Encoder 8 bits D o V RB Redundancy in fine ADC provided by over- and under-range comparators

Spring 2014 S. Hoyos-ECEN-610 78 Digital Redundancy of Fine ADC V R 1 V R 2 To Coarse CMP s V i Extra CMP s Fine Encoder + Error Correction Extra CMP s Search range of the fine ADC is extended on both sides.

Spring 2014 S. Hoyos-ECEN-610 79 Two-Step ADC V i SHA SHA 2 n 1 Fine ADC LSB s RA Coarse ADC D/A V R MSB s V R Coarse-fine two-step subranging architecture Conversion residue is produced instead of switching reference taps. A DAC and a subtraction circuit are required. Residue gain can be provisioned to relax offset tolerance in fine ADC.

Spring 2014 S. Hoyos-ECEN-610 80 Timing Diagram Sample V i Coarse ADC DAC + RA Fine ADC Four conversion steps can be pipelined. Usually DAC + RA settling takes the longest time. RA is often omitted (residue gain of one) to speed up conversion.

Spring 2014 S. Hoyos-ECEN-610 81 References 1. A. G. F. Dingwall et al., JSSC, vol. 20, pp. 1138-1143, issue 6, 1985. 2. J. Doernberg et al., JSSC, vol. 24, pp. 241-249, issue 2, 1989. 3. B.-S. Song et al., JSSC, vol. 25, pp. 1328-1338, issue 6, 1990. 4. T. Matsuura et al., CICC, 1990, pp. 6.4/1-6.4/4. 5. B. Razavi et al., JSSC, vol. 27, pp. 1667-1678, issue 12, 1992. 6. C. Mangelsdorf et al., ISSCC, 1993, pp. 64-65. 7. W. T. Colleran et al., JSSC, vol. 28, pp. 1187-1199, issue 12, 1993. 8. K. Kusumoto et al., JSSC, vol. 28, pp. 1200-1206, issue 12, 1993. 9. K. Sone et al., ISSCC, 1993, pp. 66-67, 264. 10.R. Jewett et al., ISSCC, 1997, pp. 138-139, 443. 11.B. P. Brandt et al., JSSC, vol. 34, pp. 1788-1795, issue 12, 1999. 12.H. Pan et al., JSSC, vol. 35, pp. 1769-1780, issue 12, 2000. 13.R. C. Taft et al., JSSC, vol. 36, pp. 331, issue 3, 2001. 14.H. van der Ploeg et al., JSSC, vol. 36, pp. 1859-1867, issue 12, 2001. 15.J. Mulder et al., JSSC, vol. 39, pp. 2116-2125, issue 12, 2004.

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Pipeline ADC Architecture n 1 bits n 2 bits n 3 bits n k bits V in Stage V 1 Stage V 2 Stage V 3 V k-1... 1 2 3 Stage k V 1 S/H 2 n 2 V 2 A/D n 2 bits D/A Residue amp A multi-stage subranging ADC with inter-stage gain An unrolled algorithmic ADC Spring 2014 S. Hoyos-ECEN-610 83

Spring 2014 S. Hoyos-ECEN-610 84 Pipeline Timing Diagram Φ 1 S1 samples S1 samples S2 DAC+RA S3 samples Φ 2 S1 DAC+RA S2 samples S1 DAC+RA S2 samples S3 DAC+RA S1 CMP S2 CMP S1 CMP S3 CMP Two-phase nonoverlapping clock is typically used, with the coarse ADC s operating within the nonoverlapping times. All pipeline stages operate simultaneously, increasing throughput (at the cost of latency).

Spring 2014 S. Hoyos-ECEN-610 85 1.5-b/s Residue Amplifier Φ 2 V i Φ 1 C 1 -V R /4 Φ 1 C 2 A V o V R /4 Φ 1e -V R 0 V R Decoder Φ 2 Inter-stage digital redundancy relaxes the tolerance on CMP offset. 2X gain + 3-level DAC + subtraction all integrated.

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Spring 2014 S. Hoyos-ECEN-610 93 2.5-b/s Residue Amplifier Φ 2 V i Φ 1 C 1 Φ 1 C 2 V R 1 V R 6... Φ 1 C 3 6 CMP s Φ 1 C 4 A V o -V R Φ 2 Φ 1e 0 V R Decoder Φ 2 Φ 2

Spring 2014 S. Hoyos-ECEN-610 94 2.5-b/s RA Transfer Characteristic V R V o b=0 b=1 b=2 b=3 b=4 b=5 b=6 V R /2 0 V i -V R /2 -V R -5V R /8-3V R /8 -V R /8 V R /8 3V R /8 5V R /8 V R 6 comparators + 7-level DAC are required. Max tolerance on comparator offset is ±V R /8.

Spring 2014 S. Hoyos-ECEN-610 95 2.5-b/s RA Transfer Characteristic HW: - Plot the transfer functions of the 2.5-b stage with redundancy and without redundancy. Also plot the plain 2-b transfer function. - Use a tone test input signal and introduce a V R /8 Offset in the comparators. Plot Vo and the SNR in each case.

Spring 2014 S. Hoyos-ECEN-610 96 RA Gain Error and Nonlinearity V R V R /2 b=0 b=1 b=2 V o D o 0 V i -V R /2 -V R -V R /4 V R /4 V R 0 -V R V i V R Raw accuracy is usually limited to 10-12 bits w/o error correction. Similar correction techniques applied to algorithmic ADC can be used.

Spring 2014 S. Hoyos-ECEN-610 97 Front-End Clock Skew bits/stage 1.5 2.5 3.5 err.-corr. ±V FS ±V FS ±V FS range 4 8 16 # of cmps 2 6 14 Digital redundancy allows tolerance on sampling clock skew. Dedicated front-end SHA can be used to eliminate the problem, but introduces power and area overhead.

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Spring 2014 S. Hoyos-ECEN-610 99 Pipeline ADC Pros Architecture complexity is proportional to the resolution N = Σn j. Small C in, area, and power consumption Throughput is greatly improved with pipelining. Comparator offset tolerance is greatly relaxed with inter-stage gain and digital redundancy. Inter-stage gain enables the stage scaling to further save power. Cons Typically 3 conversion operations involved (slower than flash) Sample Coarse comparison DAC and residue generation High-gain op-amps are required to generate accurate residue signals, which limits the conversion speed. Long latency may be problematic for certain applications.

Stage Scaling of Pipeline ADC Stage size, power, area... stage 1 stage 2 stage 3 stage k-1 stage k S 1 Input-referred kt/c noise... Same C for all the stages. Assume 1.5 b/s architecure, the total noise is : N Total 1 1 1 KT... C 4C 16C All stages are identically sized same capacitors, op-amps, comparators. Later stages are obviously oversized due to inter-stage gains. Spring 2014 S. Hoyos-ECEN-610 100

Spring 2014 S. Hoyos-ECEN-610 101 Stage Scaling of Pipeline ADC Stage size, power, area... stage 1 stage 2 stage 3 stage k-1 stage k S n 2 2 j Input-referred kt/c noise... C is scaled by the squared of the gain for all the stages. Assume 1.5 b/s architecure, the total noise is : 1 1 1 N Total KT... k KT / C C C C 4 16 4 16 Stages are sized such that the input-referred noises are the same. Later stages are overly sized optimum scaling factor S 2 n j.

Spring 2014 S. Hoyos-ECEN-610 102 Stage Scaling of Pipeline ADC If C is scaled by the gain for all the stages and assuming 1.5 b/s architecure, the total noise is : N Total Optimum scaling will be somewhere from scaling by the gain squared and scaling by just the gain. 1 1 1 KT... C C C 4 16 2 4 Need to take into account other sources of noise in the overall expression. Example: for 6 stages of 2.5b/s, if we assume scaling by interstage gain of 16 to get equal noise contribution from each stage. Total noise will be: 1 1 1 NTotal KT... 6n f KT / C C C C 4 16 4 16 Vpp SNR 6KT C C in in 2.5pF 2 /8 2 12 V pp 2V

Spring 2014 S. Hoyos-ECEN-610 103 OTA Design Single path At 500MHz, settling time 1ns For 13b, output should settle to 0.01% accuracy, nearly 9*ζ 2.5b stage feedback factor is ¼ GBW 5.73GHz

Spring 2014 S. Hoyos-ECEN-610 104 OTA Design Dual path Time interleaving At 250MHz, settling time 2ns For 13b, output should settle to 0.01% accuracy, nearly 9*ζ 1.5b stage feedback factor is 1/2 GBW 1.43GHz

Spring 2014 S. Hoyos-ECEN-610 105 Possible Topologies Reverse Nested Miller Compensated for high gain Single stage will have the best settling behavior With calibration, DC gain can be reduced to increase GBW Folded Cascode

Spring 2014 S. Hoyos-ECEN-610 106 References D. W. Cline and P. R. Gray, "A power optimized 13-b 5-Msamples/s pipelined analog-to-digital converter in 1.2-μm CMOS," IEEE Journal of Solid-State Circuits, vol. 31, no. 3, pp. 294-303, Mar. 1996. kt/c Constrained Optimization of Power in Pipeline ADCs - Yu Lin, Vipul Katyal, Randall Geiger Dept. Electrical and Computer Engineering, Iowa State University Ames, IA, 50010, USA Mark Schlarmann Freescale Semiconductor, Inc. Kwok, P.T. F. and Luong, Howard C, Power Optimization for Pipeline Analog-to-Digital Converters, IEEE transactions on circuits and systems II: Analog and digital signal processing, Vol. 46, No. 5, May 1999, pp. 549-553 Background Digital Error Correction Technique For Pipelined Analog-digital Converters Sameer R. Sonkusale and Jan Van der Spiegel Digital Background Calibration Technique for Pipeline ADCs with Multi-bit Stages Antonio J. Ginés, Eduardo J. Peralías and Adoración Rueda

Spring 2014 S. Hoyos-ECEN-610 107 Pipeline Calibration Methods Foreground Calibration Background Calibration Interruption of ADC signal Cannot correct for environmental changes and variations with time E.g. Radix based Works without interruption of normal operation E.g. - LMS based

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Spring 2014 S. Hoyos-ECEN-610 111 LMS based calibration n Ref. ADC Analog Input ADC x(n) Adaptive Dig. Filter y(n) n d(n) e(n) Channel Adaptive Equalizer

Spring 2014 S. Hoyos-ECEN-610 112 Single Stage Calibration Calibration of a single stage at a time Different variations of LMS to reduce computational complexity

Spring 2014 S. Hoyos-ECEN-610 113 Simultaneous Multistage Calibration

Spring 2014 S. Hoyos-ECEN-610 114 Matlab Simulations Amplitude 100 50 0-50 -100-150 -200-250 -300 DFT plot before calibration -350 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 frequency SNR 45.74dB Amplitude 80 60 40 20 0-20 -40-60 -80-100 DFT plot after calibration -120 0 200 400 600 800 1000 1200 1400 Frequency SNR 77.26dB Without offset and finite gain

Spring 2014 S. Hoyos-ECEN-610 115 Matlab Simulations 0.01 Error between filter output and expected output 0.265 Weights 0.008 0.26 Error 0.006 0.004 0.002 0-0.002 Weight value 0.255 0.25 0.245-0.004-0.006 0.24-0.008-0.01 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 Iteration 0.235 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 Iteration Final Weights - 0.2479 0.2612 0.2368 0.2635 0.2483 0.2488 Non-ideal Weights - 0.2564 0.2424 0.2597 0.2469 0.2532 0.2632

Spring 2014 S. Hoyos-ECEN-610 116 Matlab Simulations 100 DFT plot before calibration 100 DFT plot after calibration 50 0 50 Amplitude -50-100 -150-200 Amplitude 0-50 -250-300 -100-350 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 frequency SNR 33.93 db -150 0 0.5 1 1.5 2 2.5 Frequency x 10 8 SNR 56.38 db With offset and finite gain errors

Spring 2014 S. Hoyos-ECEN-610 117 Matlab Simulations 0.08 Error between filter output and expected output 0.06 0.04 Error 0.02 0-0.02 0 500 1000 1500 2000 2500 3000 3500 4000 Iteration

Spring 2014 S. Hoyos-ECEN-610 118 Matlab Simulations 0.35 Alpha 1.4 Beta 0.3 1.2 0.25 1 Value 0.2 0.15 Value 0.8 0.6 0.1 0.4 0.05 0.2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Iteration x 10 4 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Iteration x 10 4 Weights Alpha and Beta

Spring 2014 S. Hoyos-ECEN-610 119 Code-Domain Adaptive Equalization n Ref. ADC Analog Input ADC x(n) Adaptive Dig. Filter y(n) n d(n) e(n) Channel Adaptive Equalizer Speed and Accuracy decoupled Simple analog circuits can be used for high speed Precision shifted from analog domain to digital domain

Spring 2014 S. Hoyos-ECEN-610 120 Multi-Stage ADC Gain Error 1-bit/stage Ideal ADC ADC with gain error D o D o 1 1 1 1 D1 D2 D3 D 2 4 8 1 1 1 1 D1 D2 D3 D a a a a a a 1 1 2 4 1 2 3 4 Accumulated Gain Mismatch

Spring 2014 S. Hoyos-ECEN-610 121 ADC Calibration: Filtering Approach Ref. Path Analog Input ADC x(n) Digital Correction y(n) d(n) e(n)

Spring 2014 S. Hoyos-ECEN-610 122 ADC Calibration: Filtering Approach Ref. Path Wiener Filter Analog Input ADC x(n) Digital Correction y(n) d(n) e(n) Unknown System System Inversion System inversion is a well known filtering problem Also known as Equalization in digital communication

Spring 2014 S. Hoyos-ECEN-610 123 Code-Domain Adaptive Equalization n Ref. ADC Analog Input ADC x(n) Adaptive Dig. Filter y(n) n d(n) e(n) Channel Adaptive Equalizer Speed and Accuracy decoupled Simple analog circuits can be used for high speed Precision shifted from analog domain to digital domain

LMS Digital Filter Architecture Pipelined ADC S 1 S 2 S 3 S 4 S 5 S 6 S 7 2 3 3 3 3 3 3 D i d D o D out n Reference ADC + error Nonlinear LMS Filter Linear LMS Filter Digital Error Correction 1.5b/s, 2.5/s Calibrate from LSB to MSB stage Last two stages are not calibrated Spring 2014 S. Hoyos-ECEN-610 124

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Spring 2014 S. Hoyos-ECEN-610 147 References 1. S. H. Lewis et al., JSSC, vol. 27, pp. 351-358, issue 3, 1992. 2. S. Sutarja et al., JSSC, vol. 23, pp. 1316-1323, issue 6, 1988. 3. B.-S. Song et al., JSSC, vol. 23, pp. 1324-1333, issue 6, 1988. 4. Y.-M. Lin et al., JSSC, vol. 26, pp. 628-636, issue 4, 1991. 5. A. N. Karanicolas et al., JSSC, vol. 28, pp. 1207-1215, issue 12, 1993. 6. K. Sone et al., JSSC, vol. 28, pp. 1180-1186, issue 12, 1993. 7. J. Wu et al., ISCAS, 1994, pp. 461-464 vol.5. 8. T.-H. Shu et al., JSSC, vol. 30, pp. 443-452, issue 4, 1995. 9. T. B. Cho et al., JSSC, vol. 30, pp. 166-172, issue 3, 1995. 10.P. C. Yu et al., JSSC, vol. 31, pp. 1854-1861, issue 12, 1996. 11.D. W. Cline et al., JSSC, vol. 31, pp. 294-303, issue 3, 1996. 12.L. A. Singer et al., VLSI, 1996, pp. 94-95. 13.S.-U. Kwak et al., JSSC, vol. 32, pp. 1866-1875, issue 12, 1997. 14.K. Y. Kim et al., JSSC, vol. 32, pp. 302-311, issue 3, 1997. 15.J. M. Ingino et al., JSSC, vol. 33, pp. 1920-1931, issue 12, 1998.

Spring 2014 S. Hoyos-ECEN-610 148 References 16.I. E. Opris et al., JSSC, vol. 33, pp. 1898-1903, issue 12, 1998. 17.I. Mehr et al., JSSC, vol. 35, pp. 318-325, issue 3, 2000. 18.D. Miyazaki et al., ISSCC, 2002, pp. 174-175, 458. 19.B.-M. Min et al., JSSC, vol. 38, pp. 2031-2039, issue 12, 2003. 20.B. Murmann et al., JSSC, vol. 38, pp. 2040-2050, issue 12, 2003. 21.X. Wang et al., CICC, 2003, pp. 409-412. 22.J. Li et al., CICC, 2003, pp. 413-416. 23.Y. Chiu et al., JSSC, vol. 39, pp. 2139-2151, issue 12, 2004. 24.E. Siragusa et al., JSSC, vol. 39, pp. 2126-2138, issue 12, 2004. 25.C. R. Grace et al., ISSCC, 2004, pp. 460-461, 539.