PT6 Series Amp Adjustable Positive Step-down Integrated Sw itching Regulators SLTSB (Revised 9//) 9% Efficiency Adjustable Output Voltage Internal Short Circuit Protection Over-Temperature Protection On/Off Control (Ground Off) Small SIP Footprint Wide Input Range The PT6 Series is a line of High-Performance Amp, -Pin SIP (Single In-line Package) Integrated Switching Regulators (ISRs) designed to meet the on-board power conversion needs of battery powered or other equipment requiring high efficiency and small size. This high performance ISR family offers a unique combination of features combining 9% typical efficiency with open-collector on/off control and adjustable output voltage. Quiescent current in the shutdown mode is typically less than µa. Standard Application V O ADJ V IN INH C,,4 Q Specifications PT6 5,6,7,8 9,, C C = Optional µf ceramic C = Required µf electrolytic () Q = NFET + V OUT Pin-Out Information Pin Function V in V in Inhibit (V max) 4 V in 5 GND 6 GND 7 GND 8 GND 9 V out V out V out V out Adj (5) Ordering Information PT6 = +5 Volts PT6 = +. Volts PT64 = + Volts PT64 = +.5Volts Pkg Style PT Series Suffix (PT4X) Case/Pin Configuration Vertical Through-Hole N Horizontal Through-Hole A Horizontal Surface Mount C Characteristics PT6 SERIES (T a =5 C unless noted) Symbols Conditions Min Typ Max Units Output Current I o Over V in range. (). A Short Circuit Current I sc V in = V o + 5V 5. Apk Input Voltage Range V in. I o. A V o = V 6 /8 () (Note: inhibit function cannot be used above V.) V o = 5.V V o =.V 9 9 /8 () 6 V V o =.5V 9. 7 Output Voltage Tolerance V o Over V in Range, I o =. A T a = C to +6 C ±. ±. %Vo Line Regulation Reg line Over V in range ±.5 ±.5 %V o Load Regulation Reg load. I o. A ±.5 ±.5 %V o V o Ripple/Noise V n V in = V in min, I o =. A ± %V o Transient Response t tr 5% load change µsec with C o = µf V os V o over/undershoot 5. %V o Efficiency η V in=6v, I o =.5 A, V o = V 9 V in =9V, I o =.5 A, V in =9V, I o =.5 A, V o = 5.V V o =.V 89 84 % V in=9v, I o =.5A, V o =.5V 7 Switching Frequency ƒ o Over V in and I o ranges, V o = V 6 75 9 V o =.V/5V 4 5 6 khz V o =.5V 5 45 55 Shutdown Current I sc V in = 5V µa Quiescent Current I nl I o = A, V in =V ma Absolute Maximum T a Over V in range -4 +85 (4) C Operating Temperature Range Thermal Resistance θ ja Free Air Convection (4-6LFM) C/W Storage Temperature T s -4 +5 C Mechanical Shock Per Mil-STD-88D, Method., msec, Half Sine, mounted to a fixture 5 G s Mechanical Vibration Per Mil-STD-88D, Method 7., - Hz,Soldered in a PC board G s Weight 6.5 grams Notes: () The PT6 Series requires a µf electrolytic or tantalum output capacitor for proper operation in all applications. () The ISR will operate to no load with reduced specifications. () Input voltage cannot exceed V when the inhibit function is used. (4) See Thermal Derating charts. (5) Consult the related application note for guidance on adjusting the output voltage.
PT6 Series Typical Characteristics Amp Adjustable Positive Step-down Integrated Sw itching Regulators PT6,. VDC (See Note A) PT6, 5. VDC (See Note A) PT64,. VDC (See Note A) Efficiency vs Output Current Efficiency vs Output Current Efficiency vs Output Current Efficiency - % 9 8 7 6 5 9.V.V 5.V.V 6.V Efficiency - % 9 8 7 6 9.V.V 5.V 4.V.V 8.V Efficiency - % 9 8 7 6 6.V.V 4.V.V 8.V 4 5 5.5.5.5 4.5.5.5 4.5.5.5 Ripple vs Output Current Ripple vs Output Current Ripple vs Output Current 6 8 5 4 6 Ripple-(mV) 8 6 V 6.V.V 5.V.V 9.V Ripple-(mV) 4 8 6 8.V.V 4.V 5.V.V 9.V Ripple-(mV) 5 5 8.V.V 4.V.V 6.V 4 4 5.5.5.5.5.5.5.5.5.5 Thermal Derating (T a) (See Note B) 6 C 7 C.5 85 C.5 Thermal Derating (T a ) (See Note B) Thermal Derating (T a ) (See Note B) 5 C 6 C.5 7 C 85 C.5 4 C.5 5 C 6 C 7 C.5.5.5.5 9 5 7 9 5 7 -(Volts) 9 7 5 9 7 -(Volts) 6 9 5 8 4 7 -(Volts) Power Dissipation vs Output Current Power Dissipation vs Output Current Power Dissipation vs Output Current.5.5 4.5 4 PD-(Watts).5.5 6.V.V 5.V.V 9.V PD-(Watts).5.5 8.V.V 4.V 5.V.V 9.V PD-(Watts).5.5.5 8.V.V 4.V.V 6.V.5.5.5.5.5.5.5.5.5.5.5.5 Note A: Characteristic data listed in the above graphs has been developed from actual products tested at 5 C. This data is considered typical data for the ISR Note B: Thermal derating graphs are developed in free air convection cooling of 4-6 LFM. (See Thermal Application note.)
Application Notes PT6/6/6 Series Adjusting the Output Voltage of Power Trends Wide Input Range Bus ISRs The output voltage of the Power Trends Wide Input Range Series ISRs may be adjusted higher or lower than the factory trimmed pre-set voltage with the addition of a single external resistor. Table accordingly gives the allowable adjustment range for each model for either series as V a (min) and V a (max). Adjust Up: An increase in the output voltage is obtained by adding a resistor R, between pin (V o adjust) and pins 5-8 (GND). Adjust Down: Add a resistor (R), between pin (V o adjust) and pins 9-(V out ). Figure C µf Ceramic (Optional),,4 PT6/6/6 GND 5,6,7,8 Vo(adj) Vo R Adjust Up 9,, (R) Adj Down C µf (Req'd) + Vo Notes:. Use only a single % resistor in either the (R) or R location. Place the resistor as close to the ISR as possible.. Never connect capacitors from V o adjust to either GND or V out. Any capacitance added to the V o adjust pin will affect the stability of the ISR.. Adjustments to the output voltage may place additional limits on the maximum and minimum input voltage for the part. The revised maximum and minimum input voltage limits must comply with the following requirements. The limits are model dependant. PT66/PT64: V in (max) = ( x V a )V or 7V, whichever is less. V in (min) = 9.V All other models: V in (max) = (8 x V a )V or as specified. V in (min) = (V a + 4)V or 9V, whichever is greater. The values of (R) [adjust down], and R [adjust up], can also be calculated using the following formulas. Refer to Figure and Table for both the placement and value of the required resistor; either (R) or R as appropriate. (R) = R o (V a.5) V o V a kω R =.5 R o kω V a V o Where: V o = Original output voltage V a = Adjusted output voltage R o = The resistance value fromtable Table ISR ADJUSTMENT RANGE AND FORMULA PARAMETERS Adc Rated PT6 PT6 PT6 Adc Rated PT66 PT6 PT6 PT64 Adc Rated PT64 PT6 PT6 PT64 Vo (nom).5. 5. 5.. Va (min)..8.88.8.4 Va (max).9 6.7.5 8.5. Ro (kω) 8.5 66.5 5. 9.9 4.
Application Notes continued PT6/6/6 Series Table ISR ADJUSTMENT RESISTOR VALUES Adc Rated PT6 PT6 PT6 Adc Rated PT66 PT6 PT6 PT64 Adc Rated PT64 PT6 PT6 PT64 V o (nom).5. 5. 5.. V a (req.d). (.kω).4 (.4kΩ).5.6.kΩ.7 5.6kΩ.8 4.4kΩ (4.4)kΩ.9 5.8kΩ (.9)kΩ (.5)kΩ. (8.4)kΩ (7.5)kΩ. (47.)kΩ (44.)kΩ. (57.4)kΩ (5.9)kΩ (.8)kΩ. (69.8)kΩ (58.)kΩ (5.4)kΩ.4 (85.)kΩ (66.)kΩ (4.)kΩ.5 (4.)kΩ (75.)kΩ (45.5)kΩ (.)kω.6 (8.)kΩ (84.4)kΩ (5.)kΩ (4.9)kΩ.7 (6.)kΩ (94.6)kΩ (57.)kΩ (7.9)kΩ.8 (6.)kΩ (6.)kΩ (64.)kΩ (4.9)kΩ.9 (74.kΩ (8.)kΩ (7.4)kΩ (44.)kΩ. (88.)kΩ (.)kω (79.5)kΩ (47.)kΩ. (65.)kΩ (46.)kΩ (88.5)kΩ (5.5)kΩ. (.)kω (6.)kΩ (98.5)kΩ (5.8)kΩ. (8.)kΩ (.)kω (57.)kΩ.4 8.kΩ (.)kω (.)kω (6.8)kΩ.5 46.kΩ (5.)kΩ (6.)kΩ (64.)kΩ.6 7.kΩ (5.)kΩ (5.)kΩ (68.)kΩ.7 8.kΩ (8.)kΩ (7.)kΩ (7.7)kΩ.8 66.kΩ (9.)kΩ (9.)kΩ (75.6)kΩ.9 9.kΩ (6.)kΩ (9.)kΩ (79.5)kΩ 4. 9.kΩ (4.)kΩ (5.)kΩ (8.5)kΩ 4. 4.kΩ (475.)kΩ (88.)kΩ (87.7)kΩ 4. 9.4kΩ (5.)kΩ (5.)kΩ (9.9)kΩ 4. 8.kΩ (654.)kΩ (96.)kΩ (96.)kΩ 4.4 75.6kΩ (788.)kΩ (477.)kΩ (.)kω 4.5 69.kΩ (975.)kΩ (59.)kΩ (5.)kΩ 4.6 6.9kΩ (6.)kΩ (76.)kΩ (.)kω 4.7 59.4kΩ (7.)kΩ (5.)kΩ (5.)kΩ 4.8 55.4kΩ (6.)kΩ (.)kω 4.9 5.kΩ (5.)kΩ 5. 48.9kΩ (.)kω 5. 46.kΩ 88.kΩ 4.kΩ (6.)kΩ 5. 4.8kΩ 97.kΩ 568.kΩ (4.)kΩ 5. 4.6kΩ 65.kΩ 79.kΩ (47.)kΩ 5.4 9.6kΩ 469.kΩ 84.kΩ (5.)kΩ 5.5 7.8kΩ 75.kΩ 7.kΩ (59.)kΩ 5.6 6.kΩ.kΩ 89.kΩ (65.)kΩ 5.7 4.6kΩ 68.kΩ 6.kΩ (7.)kΩ 5.8.kΩ 4.kΩ 4.kΩ (78.)kΩ 5.9.kΩ 8.kΩ 6.kΩ (85.)kΩ 6..8kΩ 88.kΩ 4.kΩ (9.)kΩ ISR ADJUSTMENT RESISTOR VALUES (Cont) Adc Rated PT6 PT6 Adc Rated PT6 PT64 Adc Rated PT6 PT64 V o (nom) 5. 5.. V a (req.d) 6. 56.kΩ 94.7kΩ (7.)kΩ 6.4 4.kΩ 8.kΩ (.)kω 6.6 7.kΩ 7.kΩ (4.)kΩ 6.8 4.kΩ 6.kΩ (59.)kΩ 7. 9.8kΩ 56.8kΩ (79.)kΩ 7. 85.kΩ 5.6kΩ (.)kω 7.4 78.kΩ 47.kΩ (5.)kΩ 7.6 7.kΩ 4.7kΩ (5.)kΩ 7.8 67.kΩ 4.6kΩ (79.)kΩ 8. 6.5kΩ 7.9kΩ (4.)kΩ 8. 58.6kΩ 5.5kΩ (444.)kΩ 8.4 55.kΩ.4kΩ (48.)kΩ 8.6 5.kΩ (55.)kΩ 8.8 49.kΩ (57.)kΩ 9. 46.9kΩ (68.)kΩ 9.5 4.7kΩ (8.)kΩ. 7.5kΩ (6.)kΩ.5 4.kΩ (5.)kΩ..kΩ.5..5 68.kΩ. 4.kΩ.5.kΩ 4. 5.kΩ 4.5.kΩ 5..kΩ 5.5 86.8kΩ 6. 75.9kΩ 6.5 67.5kΩ 7. 6.8kΩ 7.5 55.kΩ 8. 5.6kΩ 8.5 46.7kΩ 9. 4.4kΩ 9.5 4.5kΩ. 8.kΩ.5 5.7kΩ.5.8kΩ.5.kΩ..4kΩ R = (Blue) R = Black
Application Notes PT6/6/6 Series Using the Inhibit Function on Power Trends Wide Input Range Bus ISRs For applications requiring output voltage On/Off control, the pin ISR products incorporate an inhibit function. The function has uses in areas such as battery conservation, power-up sequencing, or any other application where the regulated output from the module is required to be switched off. The On/Off function is provided by the Pin (Inhibit) control. The ISR functions normally with Pin open-circuit, providing a regulated output whenever a valid source voltage is applied to V in, (pins,, & 4). When a lowlevel ground signal is applied to Pin, the regulator output will be disabled. Figure V in Inh C, µf (Optional) PT6/6/6,,4 9,, Vo Inh* GND Vo(adj) 5,6,7,8 Q BSS8 C µf + V out Figure shows an application schematic, which details the typical use of the Inhibit function. Note the discrete transistor (Q). The Inhibit control has its own internal pull-up with a maximum open-circuit voltage of 8.VDC. Only devices with a true open-collector or open-drain output can be used to control this pin. A discrete bipolar transistor or MOSFET is recommended. Equation may be used to determine the approximate current drawn by Q when the inhibit is active. Equation I stby =V in 55kΩ ± % Notes:. The Inhibit control logic is similar for all Power Trends modules, but the flexibility and threshold tolerances will be different. For specific information on the inhibit function of other ISR models, consult the applicable application note.. Use only a true open-collector device (preferably a discrete transistor) for the Inhibit input. Do Not use a pull-up resistor, or drive the input directly from the output of a TTL or other logic gate. To disable the output voltage, the control pin should be pulled low to less than +.5VDC.. When the Inhibit control pin is active, i.e. pulled low, the maximum allowed input voltage is limited to +Vdc. 4. Do not control the Inhibit input with an external DC voltage. This will lead to erratic operation of the ISR and may over-stress the regulator. 5. Avoid capacitance greater than 5pF at the Inhibit control pin. Excessive capacitance at this pin will cause the ISR to produce a pulse on the output voltage bus at turn-on. 6. Keep the On/Off transition to less than µs. This prevents erratic operation of the ISR, which can cause a momentary high output voltage. Turn-On Time: The output of the ISR is enabled automatically when external power is applied to the input. The Inhibit control pin is pulled high by its internal pull-up resistor. The ISR produces a fully regulated output voltage within -msec of either the release of the Inhibit control pin, or the application of power. The actual turn-on time will vary with the input voltage, output load, and the total amount of capacitance connected to the output Using the circuit of Figure, Figure shows the typical rise in output voltage for the PT6 following the turn-off of Q at time t =. The waveform was measured with a 9Vdc input voltage, and 5-Ohm resistive load. Figure Vo (Vdc) 6 5 4 -...4.6.8 t (milli-secs)
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