A Compact, Low-Power Low- Jitter Digital PLL Amr Fahim Qualcomm, Inc. 1
Outline Introduction & Motivation Digital PLL Architectures Proposed DPLL Architecture Analysis of DPLL DPLL Adaptive Algorithm DPLL Circuit Implementation Measurement Results Conclusions 2
Introduction & Motivation I REF TCXO PFD I P K v2i K ico /s F out R I P C /N 3
Introduction & Motivation Classical 2 nd order analysis: H ( s) where: K I KRs + K C = s 2 + Rs + p K N K v2i K K NC ico Amplitude (db) ω n = K NC frequency (Hz) ζ = 1 2 R K NC 4
Introduction & Motivation Sensitivity Analysis: Assumptions: I p = ± 20%, R= ± 20%, C=±10% Loop Dynamics Variation: ζ [-41%, +59%] ω n [-48%, +33%] Effect on Lock Time: Assumption: cycle slipping time is minimal T L [-25%, +92%] Effect on phase noise: Mostly due to BW variation Neglecting 1/f noise Jitter variation is 25% 5
Introduction & Motivation TCXO Noise coupling to loop filter: I P I P Noise injected /N F out Reduce effect of noise coupling on jitter by: Reducing K v Increasing guard ring spacing Expected to worsen as processor complexity grows 6
Alternative Paradigm Digitize Loop Filter Less analog circuitry faster design time Less susceptible to ground bounces Better stability over process, temperature, and voltage LOOP FILTER [ F(z) ] I P Fin PFD & logic INC DEC SHIFT K I I P logic K R /N 1/N pllout ICO idac 7
Outline Introduction & Motivation Digital PLL Architectures Proposed DPLL Architecture Analysis of DPLL DPLL Adaptive Algorithm DPLL Circuit Implementation Measurement Results Conclusions 8
Digital PLL Architecture Can classify DPLL architecture by method by which phase & frequency error is determined Method A: Direct phase error digitization Method B: Frequency comparison & Reset 9
Digital PLL Architecture Method A: Direct phase error quantization: REF PD FD sampler REF shifter idac Count number of VCO cycles per reference cycle Max phase error is: T θ, max = REF N 1 θ, max REF N Inherent trade-off between quantization jitter and ICO jitter = T T VCO N 1 10
Digital PLL Architecture Method B: Frequency compare & reset REF /2 sampler φ 2 CNT φ 2 shifter idac Avoid quantization jitter bottleneck by using frequency locked loop and reset VCO every compare period Quantization jitter reduced to how well can estimate frequency and how fast can reset VCO Requiring VCO to be reset can limit upper frequency and VCO topology 11
Digital PLL Architecture Method B: Frequency compare & reset REF /2 sampler φ 2 CNT shifter φ 2 idac REF φ 1 φ 2 VCO 12
Outline Introduction & Motivation Digital PLL Architectures Proposed DPLL Architecture Analysis of DPLL DPLL Adaptive Algorithm DPLL Circuit Implementation Measurement Results Conclusions 13
Proposed DPLL Architecture Fin PFD & logic 1/N INC DEC SHIFT logic ICO pllout LOOP FILTER [ F(z) ] K I K R idac Reduce PFD to 1-bit output, which is weighted dynamically Small cycle-to-cycle phase error when locked, therefore DPLL behaves as a linear system Filter is composed of accumulator (integrator term) and a multiplier (proportional term) 14
Proposed DPLL Architecture DEC DEC Initial 3 1 4 0 DEC (shift right) INC (shift right) DEC (shift right) INC (shift right) 2 INC INC DEC Fast binary phase locking algorithm Reduce weight by half for every phase error sign change INC 15
Proposed DPLL Architecture PFD Diagram: R DFF Q D Reset Reset T Reset D V Q DFF Restart D UP Q LATCH CKout LATCH DN Q D Asynchronous Timing mechanism: PFD Generates a clock token which is used to drive the digital filter When filter value is updated a completion signal is sent back to PFD 16
Outline Introduction & Motivation Digital PLL Architectures Proposed DPLL Architecture Analysis of DPLL DPLL Adaptive Algorithm DPLL Circuit Implementation Measurement Results Conclusions 17
18 DPLL Linear Analysis Assume cycle-to-cycle phase error is small Discrete-time model: OUT IN 1/N F(z) ZOH K idac ICO K s ( ) + + + + = R K N K 1 Z N I K R K K 2 2 Z I K R K R K Z ) I K R (K K H(z) Closed loop expression:
DPLL Linear Analysis Case of K I =K R =1 Imaginary Axis 1 0.8 0.6 0.4 0.2 0 0.2 0.4 Root Locus System is unconditionally stable As open loop dc gain increases, poles migrate towards the origin 0.6 0.8 1 1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1 Real Axis 19
DPLL Linear Analysis Imaginary Axis 1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 K I =1, K R K R increasing k=2 Root Locus k=1.33 k=0.78 1 1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1 Real Axis As K R increases, radius of circle shrinks (i.e. less damping) Can be used to effectively control the damping factor of closed loop system K R has little affect on loop bandwidth 20
DPLL Linear Analysis Imaginary Axis 1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 K R =1, K I k=3.18 k=2.67 k=2 Root Locus K I increasing 1 1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1 Real Axis K I affects both damping factor and loop bandwidth As K I is increased, radius of circle increases; i.e. poles move faster and more oscillatory 21
Outline Introduction & Motivation Digital PLL Architectures Proposed DPLL Architecture Analysis of DPLL DPLL Adaptive Algorithm DPLL Circuit Implementation Measurement Results Conclusions 22
DPLL Adaptive Algorithm Sense number of consecutive UP or DN pulses, N err : If so, then increase size of error by factor of 2, then gradually decrease Sense if have a number of consecutive overflows, N cerr, or if can t get back to error size of 1 If so, then increase value of K R to ride out the deterministic jitter Values of N err and N cerr are determined empirically and depend on how much noise is expected to be injected into DPLL (can set by software) Value of K I greatly affects loop bandwidth and is adjusted to reduce ICO jitter, which can be determined at time of design 23
Outline Introduction & Motivation Digital PLL Architectures Proposed DPLL Architecture Analysis of DPLL DPLL Adaptive Algorithm DPLL Circuit Implementation Measurement Results Conclusions 24
DPLL Circuit Implementation D[9:4] 10-bit Current DAC: 6 4 OUT MSB OUT D[3:0] OUT 5 MSB, 5 LSB LSB D D D D OUT Iout MSB is single-ended switches zero current when off LSB is current steering switches minimum glitch energy when swtiching All Isrc are cascoded, thermally decoded and common centroid for best resolution at low currents 25
DPLL Circuit Implementation Corner cases: If LSB word is 00000 2 or 11111 2 or near these 2 words, an MSB can toggle Case 1: If LSB > 11000 2, subtract 1000 2 and turn on a special ½MSB PMOS current source Case 2: If LSB < 01000 2, add 1000 2 and turn off another special ½MSB PMOS current source that is normally always turned on Both special current sources have current steering switches 26
DPLL Circuit Implementation ICO: Three stage ring oscillator with Maneatis symmetric loads Current Source: Constant-gm current source matched to the ICO delay cell Digital Filter: CLA adders implemented for minimum phase margin degradation due to loop filter delay K I and K R restricted to powers of 2 Fast logic elsewhere 27
DPLL Circuit Implementation Steady state error (in LSBs) Effect of Loop Filter delay on jitter: 350 300 250 200 150 100 50 0 Increased jitter due to: Reduced phase margin Missing of edges at PFD due to delay of completion signal 0.01 0.03 0.05 0.07 0.09 0.11 0.12 0.14 0.16 0.18 0.2 0.22 0.24 Tdelay/Tref 28
Outline Introduction & Motivation Digital PLL Architectures Proposed DPLL Architecture Analysis of DPLL DPLL Adaptive Algorithm DPLL Circuit Implementation Measurement Results Conclusions 29
Experimental Results Phase Noise: -87dBc/Hz Closed loop BW ~ 2MHz 30
Experimental Results Jitter Histogram Plot: Peak-to-peak jitter is 270ps at 144MHz Distribution is fairly Gaussian indicating low quantization phase errors Very stable performance over temperature 31
Experimental Results Summary of Performance: Technology Power Supply Power Conumption VCO Range Peak-to-Peak Jitter Rms Jitter Cycle Jitter (T avg -T min ) 0.25um CMOS 2.6V 3.12mW @ 144MHz 40MHz 160MHz 270ps @ 144MHz 60ps @ 144MHz 130ps @ 144MHz 32
Figure-of-Merit: Area Jitter FOM Comparison with State-of-the- Proposed 1 1 1 [1] FOM 2.79 1.52 Art = 182.3 area(mm 2 ) ( tech / 0.25) [2] 1.113 3.324 518.8 2 mw MHz 3.43 Pwr 1 9.23 12.11 2.30 5.77 T L 1 0.61 0.085 3.33 2.40 1.22 APLL 17.74 1.5 [ ] jitter(ps) mw 2 [6] 0.64 1.03 9.46 33
Conclusions A fast-lock, low-jitter Digital PLL has been proposed Jitter is reduced by using an adaptive bandwidth algorithm, high-resolution idac Low-power achieved by elimination of extra overhead circuitry such as voltage-to-current (V2I) converter and charge pump and well partitioned idac Area has been reduced by digitizing the loop filter Proposed Digital PLL has very stable performance over corners due to elimination of much of analog circuitry 34