SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS

Similar documents
SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS

SN54LS06, SN74LS06, SN74LS16 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS

SN54LS07, SN74LS07, SN74LS17 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.

SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

description 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND V CC 2G/2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1Y1 2A4 1Y2 2A3 1Y3 1A2 2Y3 1A3 2Y2 1A4 2A2 2G/2G 2Y1

SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS

These devices contain four independent 2-input NAND gates. The devices perform the Boolean function Y = A B or Y = A + B in positive logic.

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

description/ordering information

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS

description/ordering information

SN54LVC14A, SN74LVC14A HEX SCHMITT-TRIGGER INVERTERS

SN5406, SN5416, SN7406, SN7416 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS031A DECEMBER 1983 REVISED DECEMBER 2001

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS032A DECEMBER 1983 REVISED NOVEMBER 1997

SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT


SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

AM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER

SN54221, SN54LS221, SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS

SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS

SN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54ALS08, SN54AS08, SN74ALS08, SN74AS08 QUADRUPLE 2-INPUT POSITIVE-AND GATES

ORDERING INFORMATION PACKAGE


MC3486 QUADRUPLE DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS

SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS

1OE 3B V GND ORDERING INFORMATION. TOP-SIDE MARKING QFN RGY Tape and reel SN74CBTLV3126RGYR CL126 PACKAGE

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54AHCT74, SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET


CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES

SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS147B DECEMBER 1982 REVISED MAY 1997

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B DECEMBER 1982 REVISED MAY 1997

SN54HC365, SN74HC365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN75158 DUAL DIFFERENTIAL LINE DRIVER

MC3487 QUADRUPLE DIFFERENTIAL LINE DRIVER

description/ordering information

ORDERING INFORMATION PACKAGE

ORDERING INFORMATION PACKAGE

ORDERING INFORMATION PACKAGE

SN5406, SN5416, SN7406, SN7416 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

SN74ALVCH V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

SN54ALS1035, SN74ALS1035 HEX NONINVERTING BUFFERS WITH OPEN-COLLECTOR OUTPUTS

SN74S ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS

SN54ALS688, SN74ALS688 8-BIT IDENTITY COMPARATORS

SN75150 DUAL LINE DRIVER

CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS

SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS

SN54ALS86, SN54AS86A, SN74ALS86, SN74AS86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SN54HC175, SN74HC175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS

SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995

SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES

74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54HC377, SN74HC377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995

SN74ALVCH BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS

description V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND

SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS

PRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description

SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

CD54ACT74, CD74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SN54HC541, SN74HC541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A APRIL 1982 REVISED DECEMBER 1994

SN75174 QUADRUPLE DIFFERENTIAL LINE DRIVER

These devices contain four independent 2-input NAND gates. The devices perform the Boolean function Y = A B or Y = A + B in positive logic.

SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS

SN75150 DUAL LINE DRIVER

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SN QUADRUPLE HALF-H DRIVER

SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

description/ordering information

SN74ALVCHR BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

These devices contain four independent 2-input NAND gates. The devices perform the Boolean function Y = A B or Y = A + B in positive logic.

SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

These devices contain four independent 2-input NAND gates. The devices perform the Boolean function Y = A B or Y = A + B in positive logic.

ORDERING INFORMATION PACKAGE SOT (SC-70) DCK

74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

SN74AHC1G04 SINGLE INVERTER GATE

PCA8550 NONVOLATILE 5-BIT REGISTER WITH I 2 C INTERFACE

description/ordering information

SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

Transcription:

Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN5414, SN54LS14...J OR W PACKAGE SN7414... D, N, OR NS PACKAGE SN74LS14... D, DB, OR N PACKAGE (TOP VIEW) description Each circuit functions as an inverter, but because of the Schmitt action, it has different input threshold levels for positive-going (V T+ ) and negative-going (V T ) signals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean, jitter-free output signals. 1A 1Y 2A 2Y 3A 3Y GND 1 2 3 4 5 6 7 14 13 12 11 1 9 8 V CC 6A 6Y 5A 5Y 4A 4Y SN54LS14... FK PACKAGE (TOP VIEW) 2A NC 2Y NC 3A 1Y 1A NC 3 4 2 1 2 19 18 5 6 7 17 16 15 8 14 9 1 11 12 13 3Y GND NC 4Y 4A 6A 6Y NC 5A NC 5Y TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP N Tube SN7414N SN7414N Tube SN74LS14N SN74LS14N C to7 C SOIC D Tube SN7414D Tape and reel SN7414DR 7414 Tube SN74LS14D Tape and reel SN74LS14DR LS14 SOP NS Tape and reel SN7414NSR SN7414 SSOP DB Tape and reel SN74LS14DBR LS14 Tube SN5414J SN5414J CDIP J Tube SNJ5414J SNJ5414J Tube SN54LS14J SN54LS14J 55 C to 125 C Tube SNJ54LS14J SNJ54LS14J CFP W NC No internal connection Tube SNJ5414W SNJ5414W Tube SNJ54LS14W SNJ54LS14W LCCC FK Tube SNJ54LS14FK SNJ54LS14FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 22, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 65533 DALLAS, TEXAS 75265 1

logic diagram (positive logic) 1A 1 2 1Y 2A 3 4 2Y 3A 5 6 3Y 4A 9 8 4Y 5A 11 1 5Y 6A 13 12 6Y Y = A Pin numbers shown are for the D, DB, J, N, NS, and W packages. 2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265

schematic 14 6 kω 1 Ω A Y GND LS14 2 kω A Y Resistor values shown are nominal. GND POST OFFICE BOX 65533 DALLAS, TEXAS 75265 3

absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, V CC (see Note 1)............................................................. 7 V voltage: 14......................................................................... 5.5 V LS14......................................................................... 7 V Package thermal impedance, θ JA (see Note 2):D package................................... 86 C/W DB package.................................. 96 C/W N package................................... 8 C/W NS package.................................. 76 C/W Storage temperaturerange, T stg................................................... 65 C to 15 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package termal impedance is calculated in accordance with JESD 51-7 recommended operating conditions SN5414 SN7414 UNIT MIN NOM MAX MIN NOM MAX Supply voltage 4.5 5 5.5 4.75 5 5.25 V IOH High-level output current.8.8 ma IOL Low-level output current 16 16 ma TA Operating free-air temperature 55 125 7 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN5414 SN7414 MIN TYP MAX VT+ 1.5 1.7 2 V VT.6.9 1.1 V Hysteresis (VT+ VT ).4.8 V VIK = MIN, II = 12 ma 1.5 V VOH = MIN, VI =.6 V, IOH =.8 ma 2.4 3.4 V VOL = MIN, VI = 2 V, IOL = 16 ma.2.4 V IT+, VI = VT+.43 ma IT, VI = VT.56 ma II = MAX, VI = 5.5 V 1 ma IIH = MAX, VIH = 2.4 V 4 µa IIL = MAX, VIL =.4 V.8 1.2 ma IOS = MAX 18 55 ma ICCH = MAX 22 36 ma ICCL = MAX 39 6 ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at,. Not more than one output should be shorted at a time. UNIT 4 POST OFFICE BOX 65533 DALLAS, TEXAS 75265

switching characteristics, V CC = 5 V, T A = 25 C (see Figure 1) SN5414, SN54LS14, PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS SN5414 SN7414 MIN TYP MAX UNIT tplh tphl A Y RL = 4 Ω, CL =15pF 15 22 15 22 ns recommended operating conditions SN54LS14 SN74LS14 MIN NOM MAX MIN NOM MAX UNIT Supply voltage 4.5 5 5.5 4.75 5 5.25 V IOH High-level output current.4.4 ma IOL Low-level output current 4 8 ma TA Operating free-air temperature 55 125 7 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54LS14 SN74LS14 MIN TYP MAX MIN TYP MAX VT+ 1.4 1.6 1.9 1.4 1.6 1.9 V VT.5.8 1.5.8 1 V Hysteresis (VT+ VT ).4.8.4.8 V VIK = MIN, II = 18 ma 1.5 1.5 V VOH = MIN, VI =.5 V, IOH =.4 ma 2.5 3.4 2.7 3.4 V VOL = MIN, VI = 1.9 19V IOL= 4 ma.25.4.25.4 IOL = 8 ma.35.5 IT+, VI = VT+.14.14 ma IT, VI = VT.18.18 ma II = MAX, VI = 7 V.1.1 ma IIH = MAX, VIH = 2.7 V 2 2 µa IIL = MAX, VIL =.4 V.4.4 ma IOS = MAX 2 1 2 1 ma ICCH = MAX 8.6 16 8.6 16 ma ICCL = MAX 12 21 12 21 ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at,. Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. switching characteristics, V CC = 5 V, T A = 25 C (see Figure 2) UNIT V PARAMETER tplh tphl FROM TO TEST CONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) 15 22 A Y RL =2kΩ kω, CL =15pF ns 15 22 POST OFFICE BOX 65533 DALLAS, TEXAS 75265 5

From Under Test Test Point CL (see Note A) RL PARAMETER MEASUREMENT INFORMATION SERIES 54/74 DEVICES (see Note B) From Under Test CL (see Note A) RL Test Point From Under Test CL (see Note A) Test Point RL 1 kω S1 (see Note B) S2 LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 3-STATE OUTPUTS High-Level Pulse Low-Level Pulse tw PULSE DURATIONS Timing Data tsu 1.5 V th SETUP AND HOLD TIMES Control (low-level enabling) tpzl tplz In-Phase (see Note D) Out-of-Phase (see Note D) tplh tphl PROPAGATION DELAY TIMES tphl tplh VOH VOL VOH VOL Waveform 1 (see Notes C and D) Waveform 2 (see Notes C and D) tpzh 1.5 V 1.5 V VOL +.5 V VOL tphz 1.5 V VOH VOH.5 V 1.5 V ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N364 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tplh, tphl, tphz, and tplz; S1 is open and S2 is closed for tpzh; S1 is closed and S2 is open for tpzl. E. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 5 Ω; tr and tf 7 ns for Series 54/74 devices and tr and tf 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 65533 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES SN5414, SN54LS14, From Under Test Test Point CL (see Note A) RL (see Note B) From Under Test CL (see Note A) RL Test Point From Under Test CL (see Note A) Test Point RL 5 kω S1 (see Note B) S2 LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 3-STATE OUTPUTS High-Level Pulse Low-Level Pulse 1. 1. tw 1. 1. PULSE DURATIONS Timing Data tsu 1. th 1. 1. SETUP AND HOLD TIMES 1. 1. Control (low-level enabling) tpzl 1. 1. tplz In-Phase (see Note D) Out-of-Phase (see Note D) tplh tphl PROPAGATION DELAY TIMES tphl 1. 1. tplh 1. 1. VOH VOL VOH VOL Waveform 1 (see Notes C and D) Waveform 2 (see Notes C and D) NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N364 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tplh, tphl, tphz, and tplz; S1 is open and S2 is closed for tpzh; S1 is closed and S2 is open for tpzl. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 5 Ω, tr 1.5 ns, tf 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement. tpzh 1. Figure 2. Load Circuits and Voltage Waveforms 1. VOL +.5 V VOL tphz 1.5 V VOH VOH.5 V 1.5 V ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS POST OFFICE BOX 65533 DALLAS, TEXAS 75265 7

TYPICAL CHARACTERISTICS OF 14 CIRCUITS Positive-Going Threshold Voltage V 1.7 1.69 1.68 1.67 1.66 1.65 1.64 1.63 1.62 POSITIVE-GOING THRESHOLD VOLTAGE FREE-AIR TEMPERATURE Negative-Going Threshold Voltage V.9.89.88.87.86.85.84.83.82 NEGATIVE-GOING THRESHOLD VOLTAGE FREE-AIR TEMPERATURE T+ V 1.61 T V.81 1.6 75 5 25 25 5 75 1 125.8 75 5 25 25 5 75 1 125 TA Free-Air Temperature C TA Free-Air Temperature C Figure 3 Figure 4 85 84 HYSTERESIS FREE-AIR TEMPERATURE 83 V T+ VT Hysteresis mv 82 81 8 79 78 77 76 75 75 5 25 25 5 75 1 125 TA Free-Air Temperature C Figure 5 Data for temperatures below C and above 7 C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only. 8 POST OFFICE BOX 65533 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS OF 14 CIRCUITS SN5414, SN54LS14, DISTRIBUTION OF UNITS FOR HYSTERESIS 2. 1.8 THRESHOLD VOLTAGES SUPPLY VOLTAGE Relative Frequency of Occurence Threshold Voltage - V 1.6 1.4 1.2 1..8.6.4 Positive-Going Threshold Voltage, VT+ Negative-Going Threshold Voltage, VT.2 74 76 78 8 82 84 86 88 9 4.5 4.75 5 5.25 5.5 VT+ VT Hysteresis mv VT+ VT Hysteresis mv Figure 6 Figure 7 2. 1.8 HYSTERESIS SUPPLY VOLTAGE 4 OUTPUT VOLTAGE INPUT VOLTAGE VT VT+ V T+ V T Hysteresis V 1.6 1.4 1.2 1..8.6.4 O Voltage V V 3 2 1.2 4.5 4.75 5 5.25 5.5.4.8 1.2 1.6 2 Supply Voltage V Supply Voltage V Figure 8 Figure 9 Data for temperatures below C and above 7 C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only. POST OFFICE BOX 65533 DALLAS, TEXAS 75265 9

TYPICAL CHARACTERISTICS OF LS14 CIRCUITS Positive-Going Threshold Voltage V V T+ 1.7 1.69 1.68 1.67 1.66 1.65 1.64 1.63 1.62 1.61 POSITIVE-GOING THRESHOLD VOLTAGE FREE-AIR TEMPERATURE Negative-Going Threshold Voltage V VT.9.89.88.87.86.85.84.83.82.81 NEGATIVE-GOING THRESHOLD VOLTAGE FREE-AIR TEMPERATURE 1.6 75 5 25 25 5 75 1 125 TA Free-Air Temperature C Figure 1.8 75 5 25 25 5 75 1 125 TA Free-Air Temperature C Figure 11 85 84 HYSTERESIS FREE-AIR TEMPERATURE DISTRIBUTION OF UNITS FOR HYSTERESIS V T+ V T Hysteresis V 83 82 81 8 79 78 77 Relative Frequency of Occurence 99% ARE ABOVE 735 mv 76 75 75 5 25 25 5 75 1 125 TA Free-Air Temperature C Figure 12 72 74 76 78 8 82 84 86 88 VT+ VT Hysteresis mv Figure 13 Data for temperatures below C and above 7 C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only. 1 POST OFFICE BOX 65533 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS OF LS14 CIRCUITS SN5414, SN54LS14, Threshold Voltage V 2. 1.8 1.6 1.4 1.2 1..8.6.4 THRESHOLD VOLTAGES AND HYSTERESIS SUPPLY VOLTAGE Positive-Going Threshold Voltage, VT+ Negative-Going Threshold Voltage, VT Hysteresis, VT+ VT VO Voltage V 4 3 2 1 OUTPUT VOLTAGE INPUT VOLTAGE VT VT+.2 4.5 4.75 5 5.25 5.5 Supply Voltage V Figure 14.4.8 1.2 1.6 2 VI Voltage V Figure 15 Data for temperatures below C and above 7 C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only. POST OFFICE BOX 65533 DALLAS, TEXAS 75265 11

TYPICAL APPLICATION DATA CMOS TTL System VT+ VT Sine-Wave Oscillator TTL System Interface for Slow Waveforms Pulse Shaper 33 Ω.1 Hz to 1 MHz VT+ VT Multivibrator Threshold Detector Open-Collector A Point A VT+ Pulse Stretcher 12 POST OFFICE BOX 65533 DALLAS, TEXAS 75265