hapter 6. Single-stage integrated-circuit amplifier ntroduction 6. design philosophy 6. omparison of the MSFET and the BJT 6.3 biasing-current - sources, mirrors and steering circuits 6.4 High-frequency response-general consideration 6.5 The common-source and common-emitter amplifiers with active loads 6.6 High-frequency response of the S and E amplifiers 6.7 The common-gate and common-base amplifiers with active loads 6.8 The cascode amplifier 6.9 The S and E amplifiers with source (emitter) 6.0 The source and emitter followers 6. Some useful transistor pairings 6. ircuit-mirror circuits with improved 6.3 The SPE MSFET model
담당교수 (instructor) 연도 (year) 학기 (semester) 교과목번호 (course number) 교과목명 (course name) 분반 (section) 권혁숭 0 B7899 전자회로 () 담당교수메일또는연락처 :hskwon@pusan.ac.kr, 055-350-54, 00-9384-37 상담가능시간 : 수 :3:00~5:00. 교수목표및강의개요 (ourse objectives & Description) ) 교수목표. 차동증폭기, 다단증폭기,P-mp. 의동작특성과주파수응답특성등을분석, 설계할수있는능력을배양시킨다.. Feedback, ctive filter, Tuned amplifier 및신호발생기 ( 발진기 ) 전력증폭기등다양한응용분야를학습한다. 3. P-Spice simulation 을이용하여회로의동작과특성을분석하고설계하는능력을키운다. ) 강의개요. BJT, MSFET 와같은개별소자를이용한여러가지응용회로와귀환, 발진, 필터회로등을학습하고, 주파수특성에따른응답을확인한다.. P-mp.(74, MS ) 의기본적인구조와특성을 D 해석과소신호해석을통해파악한다. 또한이를이용한다양한회로와응용분야를학습한다. 3. 전자회로시스템의주요분야중하나인 ctive filter 와 tuned 증폭기, 신호발생기, 함수발생기, 전력증폭기등의동작특성과이론을학습한다.. 주교재 (Required textbook) 교재 : :Microelectronics ircuits" 5th Ed. 교재 : 저자 : del S. Sedra Kenneth. Smith 출판사 : "xford University Press 004" 3. 평가방법 (Requirements & Grading) 중간고사 : 30% 기말고사 : 30% Quiz: 0% Homework: 0% 출석 : 0% (subject to change if necessary)
4. 주별강의계획 (Schedule) 주별강의및실험 실기내용과제및기타참고사항 제 주 제 주 제 3 주 제 4 주 ch. 6 Single-stage ntergrated-ircuit mp.[ 표절등학술적부정행위예방교육실시 ] ch. 6 Single-stage ntergrated-ircuit mp.[ 표절등학술적부정행위예방교육실시 ] ch. 6 Single-stage ntergrated-ircuit mp. ch. 7 Differential and multistage mp. 제 5 주 ch. 7 Differential and multistage mp. Homework 제 6 주 제 7 주 제 8 주 제 9 주 ch.. 9 p-mp. and Data converter circuits ch.. 9 p-mp. and Data converter circuits ch.. 9 p-mp. and Data converter circuits Mid Exam. ch. 8 Feedback 제 0 주 ch. 8 Feedback Homework 제 주 제 주 제 3 주 제 4 주 제 5 주 제 6 주 ch. Filter and tuned amp. ch. Filter and tuned amp. Quiz ch. 3 Signal genterators and waveform shaping circuit. ch. 3 Signal genterators and waveform shaping circuit. ch. 4. Power mp. ch. 4. Power mp. Final Exam. 5. 참고문헌 (References) 교재명 :" 전자회로 ": 저자 :Boylestad, 김수원외, 출판사 : 사이텍미디어
6. design philosophy * nalogrf design hexagon Noise Power Linearity Frequency Supply voltage Gain * lmost any two of the six parameters tradeoff with each other to some extent
6. design philosophy * Semiconductor technologies for wireless communication RF section ntenna TR Duplexer ModulatorDemodulator LNPFilters Frequency synthesizer Gas MESFET Gas HBT SiGe BJT MS DSP section oding Multiplexer ccess ontrol EchoFade Power control MS section Battery management Display oice nterface MS Technology choice -. Performance, ost, Time-to-market three critical factors -. Level of integration, form factor, prior (successful integration) experience -. urrent technologies (MS BiMS Gas etc)
6. design philosophy design constraints -. avoid large resistors -. the number of -. realize as and capacitors to reduce the chip area external capacitors is also minimized to reduce the chip terminals many of the functions required as possible using MS transistor and small MS capacitor only design freedom -. the size of -. array of -. packing a MS transistors, their width and length, can be selected for design requirements transistors can be matched with a desired size ratio large number of devices on the same chip -. below 0. m minimum channel length, 007(0.3m : popular, 90nm process) -. -. urrent technology f DD T -. high - -. on printed - circuit currents -. high - 40GHz, usual od for 08. μm NMS, quality P - amp. output currents 0. 80GHz -. high reliability under severe environmental for 03. μm BJT is still better than MSFET in stand - alone performance conditions
6. omparison of the MSFET and the BJT. Typical values of MSFET parameters 0.8µm 0.5 µm 0.5 µm 0.8 µm Parameter NMS PMS NMS PMS NMS PMS NMS PMS t ox (nm) 5 5 9 9 6 6 4 4 ox (ffµm ).3.3 3.8 3.8 5.8 5.8 8.6 8.6 µ(cm s) 550 50 500 80 460 60 450 00 µ ox (µ ) 7 58 90 68 67 93 387 86 t0 () 0.7-0.7 0.7-0.8 0.43-0.6 0.48-0.45 DD () 5 5 3.3 3.3.5.5.8.8 (µm) 5 0 0 0 5 6 5 6 oυ (ffµm) 0. 0. 0.4 0.4 0.3 0.3 0.37 0.33 Extra area 0 0.69 0.943 0.98 Base on reversed times. times 6.5 times 5.6 times 0.3 0.057 0.09 0.8µm 0.5µm 0.5µm 0.8µm
Ex.) ntel computer : PU development 4004 processor 8086 processor 86 processor 386 processor 486 processor clock speed: 08KHz Transistor:,300 technology: 0μm clock speed: 5MHz Transistor: 9,000 technology: 3μm clock speed: 6MHz Transistor: 34,000 technology:.5μm clock speed: 6MHz Transistor: 75,000 technology:.5μm clock speed: 5MHz Transistor:,00,000 technology: μm 97 979 98 985 989 pentium processor pentium pro processor pentium processor pentium 4 processor pentium M processor clock speed: 66MHz Transistor: 3,00,000 technology: 0.8μm clock speed: 00MHz Transistor: 5,500,000 technology: 0.6μm clock speed: 300MHz Transistor: 7,500,000 technology: 0.5μm clock speed:.5ghz Transistor: 4,000,000 technology: 0.8μm clock speed:.7ghz Transistor: 55,000,000 technology: 90nm 993 995 997 000 00 pentium Dual core processor pentium D processor Quad core ore i7(nehalem) ore i..(sandy Bridge) clock speed: 3.GHz Transistor: 9,000,000 technology: 65nm clock speed: 3.GHz above Transistor: 80,000,000 technology: 45nm clock speed: 3.GHz above Transistor:,60,000,000 above technology: 3nm clock speed: 3.GHz above Transistor:,900,000,000 above technology:nm 005 007 009 0
. Typical values of BJTs Standard High-oltage Process dvanced Low-oltage Process Parameter npn Lateral pnp npn Lateral pnp E (µm ) 500 900 S () 5 0-5 0-5 6 0-8 6 0-8 β 0 () 00 50 00 50 () 30 50 35 30 E0 () 50 60 8 8 τ F 0.35ns 30ns 0ps 650ps je0 pf 0.3pF 5fF 4fF µ0 0.3pF pf 5fF 5fF r x (Ω) 00 300 400 00
3. omparison of important characteristics NMS npn ircuit Symbol To perate in the ctive Mode, Two onditions Have To Be Satisfied () nduce a channel : υ GS t, t = 0.5-0.7 Let υ GS = t + υ () Pinch-off channel at drain : υ GD < t or equivalently, υ DS, = 0. - 0.3 () Forward-bias EBJ : υ on, on 0.5 () Reverse-bias BJ : υ B < Bon, Bon 0.4 or equivalently, υ E 0.3
omparison of the MSFET and BJT (ontinued) NMS npn urrent-oltage haracteristics in the ctive Region W id nox GS t L i G W nox L 0 DS DS i i B i e c S T E Low-Frequency Hybrid-π Model
omparison of the MSFET and BJT (ontinued) NMS npn Low-Frequency T Model Transconductance g m g m D W g L m n ox W g L m n ox D g m T
omparison of the MSFET and BJT (ontinued) NMS npn utput Resistance r o L r r ' o D D o ntrinsic Gain 0 g m r o 0 0 0 ' L WL ' n ox D 0 T nput Resistance with Source (Emitter) Grounded r= g m
omparison of the MSFET and BJT (ontinued) NMS npn high- Frequency Model
6. omparison of MSFET and BJT BJT has the advantage over MSFET of a much higher transconductance g m at same value of D current. much higher gain per stage MSFET has infinite high input resistance at gate. MSFET provides an excellent implementation of switch. MSFET doesn t have the thermal run-away. MSFET has very high packing density. BiMS is a technology that combining high quality BJT and high density MS on the same chip.
6.3 Biasing urrent Sources, urrent Mirrors and urrent-steering ircuits constant D current (reference current) is generated at one location and is replicated at various other locations for biasing (current steering) 6.3. The basic MSFET current source urrent Mirror ' W D kn ( GS tn) L DD GS D R :current source (, R are outside of DD Q ) : ' W D kn ( L output current of GS tn ) current source Q o 와 관계는 ( W L) ( W L) Tr. 결합구조에따른다 : current mirror if Q Q urrent Transfer Ratio
in saturation for : Q t GS Early effect of : Q r R o ) ( ) ( ) ( ) ( ) ( ) ( GS DS DS L W L W L W L W ) ( ) ( DS DS DS DS DS DS DS DS Effect of o on o ) drain resistance(r : Effect of Drain short, Gate - : 0 Q Q
6.3. MS current-steering circuits Q, together with R determine the reference current Transistors Q, Q and Q 3 form a two output current mirror GS GS GS3 ( W L) ( W L), 3 ( W L) ( W L) 3 GD G D D G th th th PMS To ensureoperation in thesaturation or D, D D3, D3 SS SS GS tn, region urrent sink (pull) from load GS 4 4 D5 3, GS 5 DD 5 4 5 ( W ( W L) L) 5 4 urrent source (push) to load ( ) GS G S
6.3.3 BJT ircuits ssume Q Q S S S,, & ) ( S E S B B e e T T 0 & ) ( B B S S e e T T,
BJT ircuits & 3) (,,, B E S B E S e e T T E E E E E E E E E E E E E E E B B ) ( ) (
,, S m S m: current transfer ratio ( ) & ( ) ( 3) & & m ( m ) m ( m )
Simple urrent Source R o r o R urrent Steering 3 4 3 EE R EB
& N BN B B B N N N N ) (