Input-Series w-stage DC-DC Cnverter with Inductr Cupling ing Qian Wei Sng Brad Lehman Nrtheastern University Dept. Electrical & Cmputer Engineering Bstn MA 0 USA Abstract: his paper presents an input-series inductrcupled tw-stage scheme t DC-DC cnverter. Discussins f the circuit in Discntinuus Cnductin Mde (DCM) are prvided bth when inversely cupled interleaving when directly cupled withut phase shift. Accrding t detailed analysis inverse cupling is mre beneficial fr current ripple reductin when the windings are nt s tightly cupled. he reasn t avid tight cupling is that current spikes resnance due t vltage mismatch can be suppressed since the tw cupled windings have a large leakage inductance. A prttype with 00-700V input V/0A utput is built. Experimental results verify the principle perfrmance f the prpsed apprach. I. INRODUCION Fr lw utput vltage high utput current applicatins the pwer lss f the synchrnus rectifiers (SRs) n the secndary side can significantly influence the entire pwer cnversin efficiency f a DC-DC cnverter. Hwever the efficiency f the secndary SRs is usually pr in single stage cnverters when the input vltage has a wide range variatin. w-stage [-] structure DC-DC cnverters seem t be a suitable slutin fr this issue. An bvius advantage f the tw-stage [-] cncept is that fixed duty peratin f the secnd stage helps t imprve the perfrmance f the SRs. he vltage current stress f the SRs are reduced when the input vltage range is wide. his leads t the utilizatin f MOSFEs with lwer n-resistance. ypically a traditinal tw-stage lw vltage cnverter utilizes a buck circuit in the first stage t regulate the utput. he secnd stage uses an islated tplgy as a DC transfrmer [] t drp the utput vltage f the buck. he secnd stage perates with a fixed duty rati (such as 0% fr half-bridge). Fr example utputinductrless half-bridge with 0% duty can be utilized in the secnd stage t minimize the utput inductr fasten the respnse speed []. he bvius disadvantage f tw-stage cnverters is their higher part cunt. hle especially high input vltage a new self-balanced input-series tw-stage cncept [7] has recently been prpsed. he apprach maintains the benefits f traditinal tw-stage cnverters yet has sme additinal interesting features. Series cnnectin is applied fr the first stage t reduce vltage stress. By chsing suitable tplgy the secnd stage is capable f regulating the charge balance f the first stage as well as imprving the perfrmance f the SRs. Similar as many typical tw-stage cnverters the new apprach utilizes utputinductrless half-bridge fr the secnd stage. he tw stages are synchrnized perate at the same frequency. Vltage ripple acrss the intermediate capacitrs can be reduced in rder t suppress the current ripple f the utput-inductrless secnd stage. Accrding t the analysis discntinuus mde peratin f the first stage is capable f achieving lwer vltage ripple. V in M L L Fig. Prpsed input-series inductr cupled tw-stage scheme A disadvantage f the new self-balanced input Series cncept [7] is that relatively mre cmpnents are used fr input-series tw-stage when cmpared with single stage tplgies. deal with this prblem this paper presents a new input-series inductr-cupled tw-stage scheme which is shwn in Fig. t reduce the size amunt f the magnetic cmpnents. Unlike typical multi-phase buck circuits with cupled inductr input-series tw-stage tplgy prefers discntinuus cnductin mde (DCM) [7]. herefre we present discussins f the circuit in DCM bth when inversely cupled interleaving when directly cupled withut phase shift. Inverse cupling is mre beneficial fr current ripple reductin when the windings are nt s tightly cupled. When the cupling is nt s tight current spikes resnance caused by the vltage mismatch f the tw windings can be suppressed. Detailed analysis including the specific cnsideratin fr DCM is prvided in Sectin III. In fact fr a certain current ripple dem the inductrs can be integrated int ne magnetic cre size is significantly reduced by means f suitable inductr cupling design fr this specific applicatin. II. OPERAION PRINCIPLE Fig. shws the prpsed input-series tw-stage cnverter with inductr cupling Fig. represents the related V ut --0-/07/$0.00 007 IEEE
wavefrms. V gs V gs V gs V are the driving signals gs fr the switches n the primary side. As can be seen in the figure the first stage includes dual interleaved buck cnverters with cupled inductr. he upper buck cnsists f D L. he lwer buck cnsists f D L. As shwn in Fig. Fig. I L I are inductr currents. L I is the current flwing thrugh the primary winding f the transfrmer n the secnd stage. Each buck circuit shares half f the vltage stress. In this paper an E magnetic cre is used. Each inductr ( L r L ) utilizes ne uter leg f the E cre fr windings. Assume bth inductrs have an inductance value f L. (In practical circuits there might be a minr difference between the tw inductrs.) M is the cupling inductance between the tw inductrs. In Fig. the inductrs are inversely cupled the tw buck circuits are interleaved which can be seen in Fig.. he secnd stage uses an utputinductrless half-bridge which cnsists f S L with fixed peratin (0% duty cycle). k L k can be an external small inductr r just the leakage inductance f the transfrmer. V in C C S S D D M L L I L C C I L I S S L k S S C R0 Fig. Prpsed input-series tw-stage cnverter with inductr cupling Vut he first stage has tw interleaved buck circuits. During t 0 -t S is turned n. he upper buck circuit transfers energy frm C t C thrugh L. he charging current i L which is shwn in Fig. increases linearly. At the same time the current f the lwer buck circuit which is i L flws thrugh the freewheeling dide D charges C. he current decreases linearly. During t -t S is turned ff. herefre current i ges thrugh the freewheeling dide L D starts t decrease linearly. i L decreases until zer. During t -t the cnditin f the upper buck is the same as interval t -t but i L has already been zer. During t -t S is turned n. he lwer buck circuit transfers energy frm C t C thrugh L. he charging current i L increases linearly. In the mean time the current f the upper buck circuit which is i L flws thrugh C. he current the freewheeling dide D charges decreases linearly. During t -t S is turned ff. Current i L ges thrugh the freewheeling dide D starts t decrease linearly. i decreases until zer. During t L -t the cnditin f the upper buck is the same as interval t -t but i has already L been zer. he secnd stage perates with a 0% duty cycle. he secnd stage transfers energy frm C t the lad thrugh the transfrmer during t0 t. he transfrmer current i flws thrugh S. he intermediate capacitr C transfers energy t the lad thrugh the transfrmer. Als C transfers energy t the lad thrugh the transfrmer S during t t. V gs V gs V gs V gs I L I L In this case the changing rates f the current thrugh inductrs are reduced during t0 t t t due t cupling f the inductrs. Similarly the changing rates increase during t t t t. Since the buck circuits perate at discntinuus mde there is n effect during t t t t. t0 t is defined as ne duty cycle. he length f t0 t t are defined as D which represents the duty rati. t I III. ANALYSIS OF WO DIFFEREN COUPLING MEHODS IN t t 0 t t t t t Fig. Wavefrms f the prpsed tplgy Fr the purpse f reducing the vltage ripple acrss the intermediate capacitrs the first stage perates at discntinuus mde [7]. Fr the cnvenience f descriptin the shrt transitin time f the secnd stage is nt included. Obviusly ZVS fr S S can be fulfilled during the transitin time just as traditinal circuits [-]. DISCONINUOUS MODE CONDIION Inductr cupling has been a ppular technlgy fr paralleled interleaving buck circuits in VRMs [8]. his research extends the idea t specific cnditins in the prpsed input-series tw-stage cnverter which has tw DCM buck circuits with BALanced Output-series Operatin. Using the derived equatins belw ptimized design can be achieved fr cnverters accrding t their specific requirement. Specifically a cmprmise between ripple reductin current spike suppressin shuld be btained. 7
A. Directly Cupled Operatin withut Phase Shift Fr tw directly cupled inductrs the fllwing typical relatins can be btained [89] di di v L M () di di v M L () In the abve case let M M. v v are the vltages L L applied n the tw crrespnding windings. M is the cupling inductance. When the tw inductrs are directly cupled withut phase shift v is equal t v. Accrding t () () the equatins related with the calculatin f current ripple during rising falling intervals are derived. dil dil L L () dil dil L L () V i V are the input vltage utput vltage f each buck circuit. V i is half f the input vltage V in in the prpsed tplgy. he effect f direct cupling relies heavily n the cupling inductance. Accrding t equatin () () a higher value f results in a lwer current ripple when there is n phase shift. Hwever fr practical circuits especially fr this high vltage applicatin switches cannt perate exactly simultaneusly. Minr mismatch can lead t high current spikes resnance when the tw inductrs have gd cupling small leakage inductance ( has a high value clse t.). herefre the cupling between the tw inductr windings has t be weakened in rder t reduce the current spikes resnance. he effect f vltage mismatch is suppressed by a bigger leakage inductance. Hwever the change rate f the current increases with the decrease f accrding t equatin () (). B. Inversely Cupled Interleaved Operatin Fr tw inversely cupled inductrs the fllwing typical relatins can be btained [89] di di v L M () di di v L M () Inverse cupling is mre flexible t achieve a cmprmise between ripple reductin current spike suppressin. he reasn t avid tight cupling is that current spikes resnance due t vltage mismatch can be suppressed since the leakage inductance has a big value. When the tw bucks have inversely cupled inductrs with interleaved peratin in DCM the fllwing equatins are derived. cmpletely take the advantage f inductance cupling steady state duty cycle shuld be chsen s that each inductr current starts t decrease befre the ther inductr current drps t zer as shwn in Fig.. During Interval t 0 t V V are applied t the tw inductrs. Similarly the change rate f the inductr currents during all intervals can be derived accrding t () (). t 0 t : dil ( ) L dil ( ) L (7) t t : dil dil L L (8) t t : dil L V dil L 0 (9) t t : dil ( ) L dil ( ) L (0) t t : dil dil L L () t t : dil L 0 dil L V () As shwn in Fig. the current ripple is determined by ( ) il il D () ( ) L Suppse using same inductance value L L L when n cupling is utilized. hen the current ripple is determined by ( V ) D il il. herefre when cupling is utilized L equatin () yields that ( ) V shuld be satisfied in rder t achieve a reduced current ripple. In ther wrds smaller inductance value can be used t satisfy identical current ripple requirement when V. V (Remember V is the utput f the buck circuit is nt the same as V ut f the secnd stage.) In additin t the value f the rati f V i V als affects the current ripple reductin f inverse cupling. IV. EXPERIMENAL RESULS verify the principle f the prpsed tplgy a prttype is built. he specificatin is: 00-700V input V/0A utput 00kHz switching frequency. SDNK0Z (00V.A DPAK) is used fr the first stage switches ( S S ). IRF000PBF (00V.A SO-8) is used fr the secnd stage 8
switches ( S S ). Each synchrnus rectifier ( S S ) uses tw SSNHLL (0V A SO-8) in parallel. A single E8 Magnetic cre is used fr the first stage inductrs E is utilized fr the secnd stage pwer transfrmer. Each first stage inductr uses ne uter leg f the E8 cre fr winding. All the legs have gaps with apprximately same distances. herefre is apprximately equal t /. he pwer transfrmer f the secnd stage has 0 turns fr the primary winding turn fr the secndary winding. Fig. Fig. shw the wavefrms f the first stage when the input vltage is 00V. In Fig. Channel shws the drain-surce vltages f S. Channel represents the drainsurce vltage f S. Channel shws the current flwing thrugh the inductr L. Fig. shws the drain-surce vltages f S S the current flwing thrugh the inductr L. As described in [7] when there is n inductr cupling the first stage has discntinuus inductr current at full lad. his significantly reduces the size f the inductr as well as S [7]. he reducing the switching pwer lss fr S change rate f the inductr current f ne buck differs as expected when the ther buck perates in a different mde. his phenmenn ccurs due t the mutual effect between the cupled windings. By cmparing the wavefrms frm the upper lwer buck circuits it can be clearly seen that the tw parts are self-balanced. Each part shares half f the input vltage. Fig. shws the drain-surce vltages f S the current thrugh the primary winding f the S transfrmer. Fig.7 shws the drain-surce vltages f S S the current thrugh the transfrmer. It can be clearly seen that the drain surce vltages f S S drps t a value clse t zer befre the currents start t increase. herefre Zer-Vltage urn-on is almst fulfilled fr the secnd stage switches ( S S ). By applying the prpsed tplgy in the built prttype an efficiency f 89.% at 00V input V/0A utput is btained. he experimental results verify the principle perfrmance f the tplgy. Fig. (n=00v) V (Channel 0V/div) ds _ S V (Channel ds _ S 0V/div) I (Channel A/div) L Fig. (n=00v) V (Channel 0V/div) ds _ S V (Channel ds _ S 00V/div) I (Channel A/div) Fig.7 (n=00v) V (Channel 0V/div) ds _ S V (Channel ds _ S 00V/div) I (Channel A/div) Fig. (n=00v) V (Channel 0V/div) ds _ S V (Channel ds _ S 0V/div) I (Channel A/div) L V. CONCLUSION Self-balanced input-series tw-stage cncept [7] has been prpsed t reduce the vltage stress as well as keeping the benefits f tw-stage structure. his paper presents a new input-series inductr-cupled tw-stage scheme t further reduce the size amunt f the magnetic cmpnents. Discussins f the circuit in DCM are prvided fr bth inverse cupling direct cupling. Accrding t detailed analysis inverse cupling is mre beneficial fr current ripple reductin when the windings are nt s tightly cupled. When the cupling is nt s tight current spikes resnance caused by the vltage mismatch f the tw windings can be 9
suppressed. Experimental results verify the principle perfrmance f the prpsed apprach. REFERENCE [] Abe S. Ninmiya. Yamamt J. Uematsu.; ransient respnse cmparisn f cnventinal utput- inductrless tw-stage DC-DC cnverter with lw-vltage/high-current utput Pwer Electrnics Cngress 00 pp.7-70. [] Abe S. Yamamt J. Zaitsu. Ninmiya. Extensin f bwih f tw-stage DC-DC cnverter with lw-vltage / high-current utput Pwer Electrnics Specialist Cnference 00 vl. pp.9-98. [] Yuancheng Ren Ming Xu Kaiwei Ya Lee F.C. w-stage 8 V pwer pd explratin fr -bit micrprcessr Applied Pwer Electrnics Cnference Expsitin 00 vl. pp.. [] Alu P. Oliver J. Cbs J.A. Garcia O. Uceda J. Buck+half bridge (d=0%) tplgy applied t very lw vltage pwer cnverters Applied Pwer Electrnics Cnference Expsitin 00 vl. pp.7 7. [] Hng Ma; Abu-Qahuq J.A.; Shigu Lu; Batarseh I.; Zer-vltageswitching (ZVS) tw-stage appraches with utput current sharing fr 8 V input DC-DC cnverter Applied Pwer Electrnics Cnference Expsitin 00 vl. pp.078-08 [] Julian Yan Zhu; Lehman B.; Cntrl lp design fr tw-stage DC-DC cnverters with lw vltage/high current utput IEEE ransactins n Pwer Electrnics Issue Jan. 00 vl.0 pp.- [7] ing Qian Brad Lehman Self-Balanced Input-Series w-stage DC-DC Cnverter Ripple Match Design Accepted by Applied Pwer Electrnics Cnference Expsitin 007. [8] Pit-Leng Wng; Peng Xu; Yang P.; Lee F.C.; Perfrmance imprvements f interleaving VRMs with cupling inductrs IEEE ransactins n Pwer Electrnics Issue July 00 vl. pp.99 07. [9] Peng Xu; Ma Ye; Lee F.C.; Single magnetic push-pull frward cnverter featuring built-in input filter cupled-inductr current dubler fr 8V VRM Applied Pwer Electrnics Cnference Expsitin 00 vl. pp.8 89 0