Total Power Mnmzaton n Gltch-Free CMOS Crcuts Consderng Process Varaton Abstract Compared to subthreshold age, dynamc power s normally much less senstve to the process varaton due to ts approxmately lnear relaton to the process parameters. However, the average dynamc power of a crcut optmzed by a determnstc path balancng approach ncreases because the fltered gltches randomly start reappearng under the nfluence of process varaton. Combnng several exstng technques, we propose a new statstcal mxenteger lnear programmng (MILP) formulaton, whch uses path balancng and dual-threshold technques to statstcally mnmze the total power n gltch-free crcuts consderng process varaton. 1. Introducton Wth the contnuous ncrease of the densty and performance of ntegrated crcuts due to the scalng down of the CMOS technology, reducng power dsspaton becomes a serous problem that every crcut desgner has to face. At the same tme, the ncrease n varablty of several key process parameters can sgnfcantly affect the desgn and optmzaton of low power crcuts n the nanometer regme [1]. Due to the exponental relaton of age current wth some process parameters, such as the effectve gate length, oxde thckness and dopng concentraton, process varatons can cause a sgnfcant ncrease n the age current. To mnmze the effect of process varaton, some technques [2-4] statstcally optmze the age power and crcut performance by dual-v th assgnment. Leakage current and delay are treated as random varables. A dynamc programmng approach for age optmzaton by dual-v th assgnment has been proposed [2] usng two prunng crtera that stochastcally dentfy pareto-optmal solutons and prune the sub-optmal ones. Another approach [4] solves the statstcal age mnmzaton problem usng a theoretcally rgorous formulaton for dual-v th assgnment and gate szng. Gltches as unnecessary sgnal transtons account for 20%-70% of the dynamc swtchng power [5]. To elmnate gltches, a desgner can adopt technques of hazard flterng [6, 8-11] and path balancng [7, 9, 12]. Compared to age power, dynamc power s normally much less senstve to the process varaton because of ts approxmately lnear dependency on the process parameters. However, any determnstc path balancng technque used for elmnatng gltches becomes less effectve under process varaton, snce the perfect hazard flterng condtons can be easly corrupted even wth a small varaton n some process parameters. Hu and Agrawal [13-14] proposed a technque to elmnate gltches under process varaton. However, performance has to be sacrfced to obtan a process-varaton-resstant crcut, and the process varaton on age power s not consdered. Our work s motvated by the above research. To mnmze the age power, we use an MILP model to determne the optmal assgnment of V th whle controllng any sacrfce n performance. To elmnate the gltch power, addtonal MILP constrants determne the postons and values of the delay elements to be nserted to balance path delays. Statstcal delay and age models are further adopted to reduce the total power n gltch-free crcuts consderng process varaton. 2. Background Lu and Agrawal [17] propose a statstcal MILP formulaton to mnmze the mpact of process varaton on the subthreshold age. In ths secton, we further dscuss the mpact of process varaton on dynamc power n detal. Dynamc power comprses two parts, logc swtchng power and gltch power, whch can be expressed by the followng equaton: P dyn 1 2 = CLV A F 2 = Logc swtchng power + Gltch power (1) where A s swtchng actvty and F s the crcut operatng frequency. Logc swtchng power s drectly proportonal to the loadng capactances, C L, whch lnearly depends upon gate szes, gate wdth and gate length. Local (ntra-de) process varaton causes gate szes to vary randomly and hence does not affect logc swtchng power too much. Global (nter-de) process varaton changes gate szes n the same tendency and does vary the logc swtchng power. However, t does not affect the soluton of our MILP formulaton, snce gate delays and gate szes n the MILP constrants ether ncrease or decrease wth the same percentage when global process varaton s consdered, and T max (maxmum crcut performance) s assumed to change accordngly. The mpact of process varaton on gltch power s dfferent and more complcated. Gltches are generatef the gltch flterng condton (2) [7] s not satsfed for cell. Snce nertal gate delays vary wth process varatons, Submtted to VLSI Desgn 08 Page 1 of 6
nequalty (2) may change from beng satsfed to beng volated or vce versa. d T t (2) We consder the mpact of global process varaton and local process varaton on gltch power separately. Impact of global process varaton on gltches For every gate, ts tmng wndow - t s actually determned by the two tmng paths, the fastest path (FPath) and the slowest path (SPath) from prmary nputs to gate. s the cumulatve nertal gate delays along that slowest path, and t s the cumulatve nertal gate delays along that fastest path, whch s shown n equaton (3). m m SPath T t = d d (3) n n FPath Assumng there s r 100% (r: 0~1) of global varaton appled to the crcut, gltch flterng condtons for gate keep unchanged snce both tmng wndow, t, and gate delay vary r 100%. Therefore, the technque of gltch elmnaton by path balancng s resstant to the global process varaton. Impact of local process varaton on gltches Now, let s consder the mpact of local process varaton on gltch elmnaton by path balancng. When local varaton s appled to a crcut, and t are the sum of gate delays, whch vary randomly, along the slowest and the fastest paths from prmary nputs to cell s nputs, so, - t s not very senstve to the process varatons, whle does change wth the process varaton. As shown n Fgure 1, there are three possble gltch flterng condtons. Both Fgures 1(b) and 1(c) are gltch free whle Fgure 1(a) has a gltch. In an un-optmzed (wth-gltch) crcut, Fgures 1(a) or 1(b) s the much more common condton for one gate, although Fgure 1(c) s stll possble but wth the least possblty. On the contrary, n a gltch-free optmzed crcut, Fgure 1(c) s appled to lots of gates because Fgure 1(a) s always forced to become Fgure 1(c) by path balancng for gltch elmnaton. - t (a) Gltch Not Free -t (b) Gltch Free -t (c) Gltch Free Fgure 1. Three possble gltch flterng condtons. Wth local process varaton, Fgures 2(a) and 2(b) show that the orgnal condton s not so easly corruptef only the varaton of the tmng wndow or the gate delay falls nto the shaded areas, whle Fgure 2(c) s extremely senstve to the local process varaton, snce a slght ncrease of the tmng wndow or decrease of the gate delay can smply let an orgnal gltch-free gate generate gltches at ts output. - t (a) Gltch Not Free -t (b) Gltch Free -t (c) Gltch Free Fgure 2. Three possble gltch flterng condtons under local process varaton. Ths explans why the dynamc power of an un-optmzed (wth-gltch) crcut s much more resstant to local process varaton than that of a gltch-free crcut optmzed by path balancng. The gltch-free condton shown n Fgure 1(c) cannot be really satsfed even wth a qute small process varaton. Probablty 0.50 0.40 0.30 0.94 0.95 0.97 0.98 1.00 1.01 1.03 1.04 Normalzed Dynamc Power 10% delay varaton 20% delay varaton 30% delay varaton Fgure 3. Normalzed dynamc power dstrbuton of unoptmzed (wth -gltch) C432 under local delay varaton Fgure 3 demonstrates the resstance of un-optmzed crcuts to the local process varaton. We apply 10%, 20% and 30% local delay varatons, whch are caused by the varaton n gate-length-ndependent V th, to the unoptmzed (wth-gltch) crcut C432. The largest percentage of the mean value devated from the nomnal value s 0.22% and the maxmum spread (3*S.D./mean) s only 4.5%. The senstvty of gltch-free crcuts optmzed by path balancng to the local process varaton s llustrated by Fgure 4. It shows that both the mean free crcuts optmzed by path balancng to the local process value and standard devaton of dynamc power dstrbuton ncrease sgnfcantly wth the ncrease of the local process varaton. When 30% local varaton s appled to the optmzed gltch-free C432, ts average dynamc power ncrease 32% and almost equals to the normalzed dynamc power (1.34) of un-optmzed C432. In Fgure 4, some samples of optmzed C432 s dynamc power are even larger than 1.34. It should be mentoned that every sample n Fgure 4 s larger than the nomnal value, 1, whch s the expected mnmum-normalzed-dynamcpower of optmzed gltch-free C432 acheved by path balancng. Process varaton causes some gltches to be 1.05 1.07 Submtted to VLSI Desgn 08 Page 2 of 6
generaten ths gltch-free crcut and hence ncreases the dynamc power. Probablty 0.15 0.05 1.00 1.04 1.08 1.12 1.16 1.20 1.24 1.28 1.32 Normalzed Dyanmc Power 10% delay varaton 20% delay varaton 30% delay varaton 1.36 1.40 1.44 1.48 Fgure 4. Normalzed dynamc power dstrbuton of optmzed (gltch-free) C432 under local delay varaton. It s remarkable that the advantage of gltch elmnaton by path balancng s totally lost due to the local process varaton. The determnstc approach of path balancng s not effectve for power optmzaton wth process varaton. In the followng secton, we combne the MILP formulatons ntroducen [15-17], and thus a new statstcal MILP formulaton s proposed to optmze total power under process varaton and to fully utlze the advantage of path balancng. The determnstc MILP [15-16] usng path balancng and dual-v th assgnment to reduce the total power consumpton s frst adopted as a prerequste for later modfcaton to consder process varaton. 3. Statstcal MILP for Total Power Optmzaton wth Process Varaton In the statstcal MILP formulaton, we treat all gate delays and tmng wndow varables as random varables wth normal dstrbuton whose standard devaton s σ r. 3.1 Varables Integer varables: In our cell lbrary, each standard cell has two possble threshold voltages and three alternatve szes (1X, 2X and 4X). Therefore, ths MILP has sx nteger varables snce each devce has 6 alternatve choces. X1L[, X2L[, X4L[, X1H[, X2H[, X4H[ Contnuous Varables: δ[ - relaxed varable for the gltch flterng constrant of cell. It wll be dscussen Secton 3.3. Sze[ - sze of cell. I [ - nomnal value of age of cell. u_d[ - mean of nertal gate delay of cell. s_d[ - standard devaton of nertal gate delay. u_ d[,j]-mean of d[,j] (the delay of the nserted delay element). s_ d[,j] - standard devaton of d[,j]. u_t[ - mean of T[. s_t[ - standard devaton of T[. u_t[ - mean of t[. s_t[ - standard devaton of t[. 3.2 Constants T max - the maxmum expected crcut performance. σ r - standard devaton of the process parameter varatons. S X2 [ - gate sze of cell wth 2X drvng strength. W 1, W 2,W 3 - weght factors. I X2L [, I X2H [ - nomnal values of the subthrehold age of cell wth 2X drvng strength. D X1L [, D X2L [, D X4L [, D X1H [, D X2H [, D X4H [ - nomnal values of the nertal gate delay of cell at all sx corners. 3.3 Constrants Basc constrants Let LP solver choose one and only one optmal verson for cell. X 1 L[ + X 2L[ + X 4L[ + X1H [ + X 2H[ + X 4H[ = 1 (4) Nomnal value of the subthreshold age of cell : u _ I [ = (0.5 X1L[ + X 2L[ + 2 X 4L[ ) I X 2L [ + (0.5 X1H[ + X 2H[ + 2 X 4H[ ) I [ X 2H Mean and standard devaton of the gate delay of cell : u _ D [ ] = DX 1L[ X1L[ + DX 2L[ X 2L[ + DX 4L[ X 4L[ + D [ X1H[ + D [ X 2H[ + D [ X 4H[ X 2L [ ] u D[ X 2L X 4L s _ D = σ r _ (7) The sze of cell : 0.5 ( X1L[ + X1H[ ) + ( X 2L[ + X 2H[ ) + Sze[ = S X 2[ 2 ( X 4L[ + X 4H[ ) (8) For gltch elmnaton Instead of usng nequalty (2), n the statstcal method, we adopt the followng gltch flterng constrant: [ ] 3 s _ D[ ( u _ T[ + 3 s _ T[ ) ( u _ t[ 3 s _ t[ ) u _ D (5) (6) (9) Submtted to VLSI Desgn 08 Page 3 of 6
Ths constrant can leave certan margn for process varaton n advance as shown n Fgure 2(b) nstead of Fgure 2(c). However, normally the above worst case constrant s too tght to make CPLEX LP solver fnd a feasble soluton. So, we add a relaxed varable δ[ to each gltch flterng constrant (9). [ ] 3 s _ D[ ) ( u _ T[ + 3 s _ T[ ) ( u _ t[ 3 s _ t[ ]) δ[ ] + ( u _ D (10) In the objectve functon, by mnmzng Σδ[, CPLEX LP solver wll try to fnd one optmal soluton to make as large number of constrants (10) satsfed as possble wth a zero δ[, whch means the gltches of correspondng cells can be truly elmnated even n the worst case condton of process varaton. Those constrants only beng satsfed wth the help of a postve δ[ qute lkely fal to flter gltches. For maxmal performance To keep the maxmal performance, at every prmary output k, let, u _ T[ k] + 3 s _ T[ k] T. (11) 3.4 Objectve functon max The objectve functon mnmzes the mpact of process varaton on the total power consumpton. Mn {the mpact of process varaton on the total power consumpton} = Mn {mean and standard devaton of age power + mean and standard devaton of dynamc power} = Mn W [ ] [ ] [ ] + + + 1 C1 I W2 C 2 sze C3, j W3 δ [ j (12) C 1, C 2 and C 3 are fttng parameters to let three terms (C 1 ΣI [, C 2 Σsze[ and C 3 ΣΣ d[,j]) have the same unts (uw). When we talk about process varaton, ts mpact on the mean and standard devaton of the power consumpton should both be consdered. For age, a smaller mean value automatcally means a narrower spread of age power dstrbuton snce more gates are assgned hgh V th. Mn(C 1 ΣI [) should be enough to mnmze the mpact of process varaton on the total subthreshold age. For the dynamc power, standard devaton of the dynamc power dstrbuton s determned by Σδ[, and (C 2 Σsze[+C 3 ΣΣ d[,j]) affects the average dynamc power. Therefore we should mnmze (C 2 Σsze[+ C 3 ΣΣ d[,j]) and Σδ[ smultaneously. The objectve functon (12) s composed of three parts (three sngle objectves), ncludng, to mnmze the average age power, to mnmze the average dynamc power and to mnmze the standard devaton of the dynamc power. It s actually a mult-objectve functon and each sngle objectve conflcts wth others, for nstance, to mnmze Σδ[ results n the ncrease of ΣΣ d[,j], and to optmze ΣI [ leads to a larger Σsze[, etc. It s not easy to get one optmum value for every sngle objectve. What we can do nstnctvely s to carefully select weght factors, W 1, W 2 and W 3 to make a tradeoff among these three objectves. It should be notced that the soluton provded by a determnstc MILP [15-16] gves us a rough mage of whch one s the domnant component between age and dynamc power. We also get ther exact optmal values (power consumpton) for the optmzed crcut. Based on that nformaton, we can choose weght factors and add some constrants of the largest allowable mnmal age or dynamc power n the statstcal MILP formulaton emprcally. The choce of mnmzng the mpact of process varaton on the age or reducng the effect of process varaton on the dynamc power s determned by whch one s the domnant one between the age and the dynamc power, and the crcut applcatons as well. In a crcut optmzed by the determnstc MILP, Case 1 - f the optmal age s much less than the optmal dynamc power ants large spread due to process varaton (for example, 5X dfference under 30% global process varaton ) stll can be gnored, we need put much more emphass on dynamc power resstance to process varaton; Case 2 - f the optmal age s comparable to the optmal dynamc power, and most of the tme the crcut n the standby mode, for example, crcuts of cell phones, the mpact of process varaton on the optmal age should be mnmzed wth prorty defntely snce age s much more senstve to the process varaton; Case 3 - f the optmal age s comparable to the optmal dynamc power, and most of the tme the crcut s n the actve mode, for example, crcuts of portable GPS or portable game machnes, etc., both the mean and standard devaton of the dynamc power dstrbuton should be optmzen the frst place. 3.5 Mnmzng mpact of process varaton on age In case 1 and case 3, dynamc power s the domnant component of the total power consumpton. Its standard devaton s determned by the number of gltch flterng constrants (10) whose δ[ are postve values. So, n the MILP objectve functon (13), we frst let W3 be nfntely large to put the hghest prorty on mnmzng Σδ[. Mn W 1 I [ ] [ ] [ ] + W 2 sze + d, j + W 3 δ [ W 3 > j (13) Submtted to VLSI Desgn 08 Page 4 of 6
Although MILP tres to mnmze Σδ[, δ[ for some gate may stll be postve snce the constrant (9) s too tght to be satsfed wthout the help of a postve δ[. Every postve δ[ possbly results n the gltch generaton at gate s output. From Fgure 4, we can also see that the average dynamc power lnearly ncrease wth the process varaton approxmately. Ths ncrease s contrbuted by the gltch power, whch generates under process varaton condton. To counteract the ncrease n the average dynamc power due to those gltches, or to let the really average dynamc power n process varaton condton stll be close to that one acheved by the determnstc MILP formulaton, we have to sacrfce some age power to get a smaller logc swtchng power n advance. Ths can be acheved by lettng W1 and W2 both equal to 1 n the MILP objectve functon (14) and addng a new constrant (15) to the statstcal MILP formaton. Mn C [ ] [ ] [ ] 1 I + C 2 sze + C 3 d, j + W 3 δ [ W > j (14) [ + C d[ j] P / ρ C < ( ρ>1) (15) 2 sze 3, dyn _ opt j P dyn_opt s the optmal dynamc power obtaned by the determnstc MILP [15-16] and ρ s a constant determned by the process varaton. By lettng ρ larger than 1, the statstcal MILP formulaton can gve an optmal crcut whch has less dynamc power. 3.6 Mnmzng mpact of process varaton on age In case 2, age almost equals to or s even larger than the dynamc power. Snce age s so senstve to the process varaton that we cannot mnmze the effect of process varaton on the dynamc power by sacrfcng age any more. The technque of usng path balancng to elmnate gltches has to be dscarded snce the ncrease n the average dynamc power under process varaton may be close to or even larger than the gltch power elmnated by path balancng. To let the age of optmzed crcuts resstant to the process varaton, we can stll use the MILP proposen [17] except every gate has sx possble choces nstead of two choces. 4. Results In C432 optmzed by the determnstc MILP formulaton n [15-16], the optmzed total power comprses 59.3uW dynamc power and 5.54µW age power. Wth 15% local process varaton, ts average dynamc power ncrease 13.53% and wth 5.34% standard devaton. To reduce the mpact of process varaton on ts dynamc power, the objectve functon (14) and constrant (15) (let P dyn_opt =59.3µW and ρ=1.10) are adopten the statstcal MILP formulaton. The two curves n Fgure 5 show that the average dynamc power only ncreases 3.63% nstead of 13.53%, and standard devaton s also reduced to 2.82% from 5.13% when 15% local process varaton s appled to the optmzed gltch-free C432, although at a cost of 94% average age power ncrease (from 1.0 to 1.94) and a lttle bt wder spread of age power dstrbuton, whch s shown n Fgure 6. Probablty 0.50 0.45 0.40 0.35 0.30 0.25 0.15 0.05 statstcal µ=1.04 3σ/µ=2.82% (µ-n)/n=3.63% determstc µ=1.14 3σ/µ=5.13% (µ-n)/n=13.53% 0.95 0.98 1.01 Normalzed Dynamc Power 1.04 1.07 1.10 1.13 1.16 1.19 1.22 Fgure5. Comparson of the mpacts of 15% local process varaton on the dynamc power n C432 whch s optmzed by the statstcal MILP wth the emphass on the resstance of dynamc power to process varaton, or by the determnstc MILP [15-16]. (N=1, s the expected normalzed mnmum dynamc power n the optmzed gltch-free C432). Probablty 0.18 0.16 0.14 0.12 0.08 0.06 0.04 0.02 0.50 0.65 statstcal 0.80 0.95 1.10 N2=1.94 µ=2.25 σ/µ=10.24% (µ-n1)/n1=16.97% determnstc N1=1.00 µ=1.17 σ/µ=6.64% 1.25 1.40 1.55 1.70 1.85 2.00 2.15 Normalzed Leakage (µ-n2)/n2=15.22% Fgure 6. Comparson of the mpacts of 15% local L eff process varaton on the age power n C432 whch are optmzed by the statstcal MILP wth the emphass on the resstance of dynamc power to process varaton, or the determnstc MILP [15-16]. (N1 and N2 are the normalzed nomnal age power n the optmzed gltch-free C432). 5. Summary In ths paper, the mpact of process varaton on dynamc power s analyzed, and a statstcal MILP formulaton s presented to mnmze the total (dynamc and age) power n gltch-free crcuts consderng process varaton. The mpact of process varaton on dynamc power can be mnmzed by gvng up some age f the dynamc power s stll the domnant power component under process varaton. Fgure 7 gves the flowchart of how to 2.30 2.45 2.60 2.75 2.90 Submtted to VLSI Desgn 08 Page 5 of 6
make a decson as to whch one, age or dynamc power, should be optmzed wth process varaton. Y Use statstcal MILP to mnmze process varaton mpact on dynamc power Use determnstc MILP to get the optmal power Smulate optmzed crcut wth certan process varaton, get mean and standard devaton of age Can age stll be gnored under certan process varaton? N N Is crcut most tme n standby mode? Y Use statstcal MILP to mnmze process varaton mpact on ge power Fgure 7. An algorthm to determne whether age or dynamc power should be optmzed wth process varaton. 6. References [1] M. Man, A. Devgan, and M. Orshansky, "An Effcent Algorthm for Statstcal Mnmzaton of Total Power Under Tmng Yeld Constrants," n Proc. Desgn Automaton Conference, 2005, pp. 309-314. [2] A. Davood and A. Srvastava, Probablstc Dual-V th Optmzaton Under Varablty, Proc. ISLPED, 2005, pp. 143-147. [3] A. Srvastava, D. Sylvester, D. Blaauw, Statstcal Optmzaton of Leakage Power Consderng Process Varatons Usng Dual-V th and Szng, Proc. DAC, 2004, pp. 773-778. [4] M. Man, A. Devgan and M. Orshansky, An Effcent Algorthm for Statstcal Mnmzaton of Total Power Under Tmng Yeld Constrants, Proc. DAC, 2005, pp. 309-314. [5] A. P. Chandrakasan and R. W. Brodersen, Low Power Dgtal CMOS Desgn. Boston: Sprnger, 1995. [6] V. D. Agrawal, "Low Power Desgn by Hazard Flterng," n Proc. 10th Internatonal Conf. VLSI Desgn, 1997, pp. 193-197. [7] V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, "Dgtal Crcut Desgn for Mnmum Transent Energy and a Lnear Programmng Method," n Proc. 12th Internatonal Conf. VLSI Desgn, 1999, pp. 434-439. [8] E. Jacobs and M. Berkelaar, "Usng Gate Szng to Reduce Gltch Power," n Proc. PRORISC/IEEE Workshop on Crcuts, Systems and Sgnal Processng, 1996, pp. 183-188. [9] S. Km, J. Km, and S. Y. Hwang, "New Path Balancng Algorthm for Gltch Power Reducton," IEE Proc. of Crcuts, Devces and Systems, vol. 148, no. 3, pp. 151-156, 2001. [10] C. V. Schmpfle, A. Wroblewsk, and J. A. Nossek, "Transstor Szng for Swtchng Actvty Reducton n Dgtal Crcuts," n Proc. European Conference on Theory and Desgn, 1999. [11] A. Wroblewsk, C. V. Schmpfle, and J. A. Nossek, "Automated Transstor Szng Algorthm for Mnmzng Spurous Swtchng Actvtes n CMOS Crcuts," n Proc. IEEE Internatonal Symposum on Crcuts and Systems, 2000, pp. 291-294. [12] T. Raja, V. D. Agrawal, and M. L. Bushnell, "Mnmum Dynamc Power CMOS Crcut Desgn by a Reduced Constrant Set Lnear Program," n Proc. 16th Internatonal Conf. VLSI Desgn, 2003, pp. 527-532. [13] F. Hu and V. D. Agrawal, "Input-Specfc Dynamc Power Optmzaton for VLSI Crcuts," n Proc. of the Internatonal Symposum on Low Power Electroncs and Desgn, 2006, pp. 232-237. [14] F. Hu, "Process-Varaton-Resstant Dynamc Power Optmzaton for VLSI Crcuts," PhD Thess, Auburn, Alabama: Auburn Unversty, May 2006. [15] Y. Lu and V. D. Agrawal, "CMOS Leakage and Gltch Power Mnmzaton for Power-Performance Tradeoff," Journal of Low Power Electroncs, vol. 2, no. 3, pp. 378-387, Dec. 2006. [16] Y. Lu and V. D. Agrawal, "Leakage and Dynamc Gltch Power Mnmzaton Usng Integer Lnear Programmng for Vth Assgnment and Path Balancng," n Proc. of the Internatonal Workshop on Power and Tmng Modelng, Optmzaton and Smulaton, 2005, pp. 217 226. [17] Y. Lu and V. D. Agrawal, "Statstcal Leakage and Tmng Optmzaton for Submcron Process Varaton," n Proc. 20th Internatonal Conf. VLSI Desgn, 2007, pp. 439-444. Submtted to VLSI Desgn 08 Page 6 of 6