Naztec Operations Manual For Four Channel Inductive Loop Detector Model 724/224 April 2003 Published by: Naztec, Inc. 820 Park Two Drive Sugar Land, Texas 77478 Phone: (281) 240-7233 Fax: (281) 240-7238 Copyright 2003 Naztec, Inc. All rights reserved.
Table of Contents 1.General Description... 2 2. User Interface and Settings... 3 2.1 Sensitivity Selection... 3 2.2 Frequency Selection... 3 2.3 Pulse/Presence Selection... 4 2.4 Detect LEDs... 4 2.5 Fault LEDs... 4 2.5 Fault LEDs... 5 2.6 Reset Button... 5 3. Installation Instructions... 6 3.1 Selecting the Sensitivity... 6 3.2 Field Troubleshooting... 6 3.3 Loop Inspection... 6 4. Theory of Operation... 7 4.1 General Concept... 7 4.2 Loop Oscillator... 7 4.3 Gate Array Counter... 7 4.4 Micro-Controller... 7 5. Troubleshooting... 8 5.1 Required Equipment... 8 5.2 Problem Isolation... 9 5.3 User Interface Repair... 10 5.3.1 Reset Switch... 10 5.3.2 Sensitivity Switches...10 5.3.3 Frequency Switches... 11 5.3.4 Fault LEDs... 11 5.3.5 Detect LEDs... 12 5.4 Processor Repair... 13 5.4.1 Processor Reset Circuitry... 13 5.4.2 Processor... 13 5.4.3 FPGA... 14 5.4.4 Serial PROM... 14 5.5 Power Supply Repair... 15 5.5.1 24 VDC Input... 15 5.5.2 5 VDC Supply... 15 5.5.3 12 VDC Supply...15 5.6 Loop Oscillator Repair... 16 5.7 Output Repair... 17 5.7.1 Detect Outputs... 17 5.7.2 Fault Outputs... 18 6. Specifications... 19 6.1 Electrical Specifications... 19 6.2 Operational Specifications... 19 6.3 Pin Assignments... 20 7. Parts List and Drawings... 20 7. Parts List and Drawings... 21 Naztec, Inc. 1
1. General Description The Naztec 724/224 four channel loop detector is a single slot, rack-mounted, loop detector designed to meet the Model 224 requirements of the State of California Traffic Signal Control Equipment Specification, dated January 1989. The detector also meets or exceeds the NEMA requirements for an inductive loop detector. Naztec s 724/224 provides front panel selectable sensitivity, pulse/presence, and frequency settings. There are 15 sensitivity settings available that range from 1.25% to 0.006%. One sensitivity setting also allows for disabling a channel completely. Two frequency switches are available, allowing a total of four user-selectable frequencies per channel. The pulse/presence setting permits the user to select the detector output mode. Pulse mode will produce a single 125 ms pulsed output each time a car enters the loop, while presence mode will produce a constant output while a car is in the loop. The detector s use of high-speed gate array logic permits far quicker detector response time than conventional scanning detector design. Six of the fifteen available sensitivity settings allow for response in less than 6ms. Never does a response time exceed 65ms. The 724/224 sequentially scans each loop channel. This technique eliminates crosstalk between channels on the same detector, reduces crosstalk between channels on adjacent detectors, and reduces loop oscillator power consumption by 75%. The detection outputs on the 724/224 are optically isolated to maximize transient protection. The design also allows for the outputs to place a constant call when no power is applied to the detector. The 724/224 provides a highly accurate pulse output for count. Naztec, Inc. 2
2. User Interface and Settings The following section is subdivided into the various features available on the 724/224. Each sub-topic then addresses the details of the particular feature. 2.1 Sensitivity Selection Each channel has four switches associated with its sensitivity setting. The switches are labeled 1,2,4 and 8. They permit 15 different sensitivity settings, and the ability to disable a channel. Each channel automatically re-tunes when the sensitivity is changed. Re-tuning caused by a setting change is equivalent to a re-tune caused by a reset -- the channel s associated fault indicators are cleared and the channel operates at the new setting. The following figure and table illustrate sensitivity selection: FREQ SENSE O N A B 1 2 4 8 Setting 224 Sense 724 Sense 8 4 2 1 Resp. Time 0 OFF OFF R R R R N/A 1 1.250% 1.250% R R R L 6 ms 2 1.000% 1.000% R R L R 6 ms 3 0.800% 0.800% R R L L 6 ms 4 0.500% 0.500% R L R R 6 ms 5 0.320% 0.320% R L R L 6 ms 6 0.200% 0.200% R L L R 6 ms 7 0.122% 0.122% R L L L 6 ms 8 0.061% 0.080% L R R R 10 ms 9 0.021% 0.061% L R R L 16 ms 10 0.018% 0.048% L R L R 35 ms 11 0.015% 0.031% L R L L 35 ms 12 0.012% 0.024% L L R R 52 ms 13 0.009% 0.018% L L R L 52 ms 14 0.006% 0.012% L L L R 64 ms 15 0.003% 0.006% L L L L 64 ms 2.2 Frequency Selection Each channel has two switches associated with its frequency setting. The switches are labeled A and B. They permit the user to modify the operating frequency of the loop to reduce crosstalk between adjacent detectors. O N 8 SENSE 4 2 1 FREQ B A Setting Frequency A B 0 Lowest R R 1 Low R L 2 High L R 3 Highest L L Naztec, Inc. 3
2.3 Pulse/Presence Selection Each channel has one switch associated with its pulse/presence setting. The switch is labeled P/PR. Moving the switch changes the operation of the detector immediately. In presence mode, the detection output is held active while a car is present on the loop. In pulse mode, the detection output is pulsed active for 125ms when a car enters the loop. The output is pulsed again for each subsequent car regardless of how many may already be sitting on the loop. The detector s regular detection output may be used for counting when the detector is in pulse mode. PR4 PR3 PR2 PR1 Setting Presense Pulse P R L O N 2.4 Detect LEDs Each channel has one detect LED used to indicate a variety of states relating to the detect output. The LED blinks at different rates to indicate to the user its current state. 1 FLT FREQ SENSE 724 DET A B 1 2 4 8 Rate Meaning Off No vehicle/channel Off On Vehicle on loop 8 Hz Flash Extend is active 2 Hz Flash Delay is active Naztec, Inc. 4
2.5 Fault LEDs For each channel, one fault LED is used to indicate the various fault conditions that may occur. The fault LED indicator latches the last fault that occurred. A blinking fault LED does not necessarily indicate that a fault is in progress; instead, it indicates the most recent fault since the detector was last reset. Pressing the reset button will clear the fault indications and reset the entire detector. 724 1 FLT FREQ SENSE DET A B 1 2 4 8 Rate Meaning Off Loop operation/channel Off On CPU Failure 8Hz Flash Loop Shorted 2Hz Flash Loop open 1/2Hz FlashLoop inductance change > 25% 2.6 Reset Button The reset button available on the front panel has the same effect as removing and reconnecting power. Depressing the reset button will clear all indications and force a re-tune on all channels at their selected sensitivity. 4 FREQ SENSE O N A B 1 2 4 8 FLT DET RESET Naztec, Inc. 5
3. Installation Instructions The following section addresses issues that arise during installation. The topics cover field troubleshooting, loop inspections, and sensitivity selection 3.1 Selecting the Sensitivity It is very important that the proper sensitivity level be selected to allow the loop detector to operate as desired. If the sensitivity is too low, then the loop detector will miss calls. If the sensitivity is too high, the loop detector will issue false calls. However, it is accepted that if a detector is going to be biased, it is desirable that it be biased toward false calls. Therefore, it is better to have the sensitivity a little too high than too low. The following procedure will help simplify this process. 1. Set the sensitivity setting to 5 2. If all vehicles are being detected, reduce the setting by one 3. If all vehicles are NOT being detected, increase the setting by one 4. Repeat steps 2 or 3 until all vehicles are consistently detected 5. Increase the sensitivity setting by one. 3.2 Field Troubleshooting The following section responds to a few common problems: Intermittent Faults Verify good crimps on the loop lead-ins Check that external lightning suppression is not faulty by removing it Tighten loop terminal connections at the loop termination panel in the cabinet Follow loop inspection procedure in section 3.3 to check loop specifications Detector Does Not Operate Verify that 24 VDC is present and within specifications Check that the external reset line is not active (grounded) Make sure channel sensitivities are not set to 0, thus disabling the channels Detector Is Missing Vehicles Increase sensitivity by one until the detector sees all vehicles Detector Is Generating False Calls Decrease sensitivity by one until the false calls cease 3.3 Loop Inspection Many times poor detector performance can be attributed to poor loop condition or installation. The following is a very brief checklist that will allow the user to quickly inspect the loop. It is suggested that each loop lead-in be a twisted pair with shielding termination at the cabinet chassis ground. 1. Disconnect the loop inputs from the cabinet 2. Meg the input to earth ground; they should be greater than 1 MegaOhm 3. Disconnect the loop shield from the cabinet ground 4. Meg the shield to earth ground; they should be greater than 1 MegaOhm 5. Use a multi-meter to measure the resistance of each loop; they should be less than 4 Ohms Naztec, Inc. 6
4. Theory of Operation The following section discusses the 724/224 theory of operation in a modular fashion. The detector is broken down into each major operational block. 4.1 General Concept The basic operation of a loop detector is to monitor the resonant frequency of an inductor (the loop) and a capacitor pair. When a metallic body passes over the loop, a shift in the resonant frequency occurs relative to the change in inductance caused by the vehicle passing over the loop. The sensitivity simply identifies a threshold that must be passed do to the proportional change in order for a detect output to be activated. Simply stated, a loop detector monitors for a vehicle by waiting for a pre-described frequency change to occur due to the passing vehicle. 4.2 Loop Oscillator The basic components of the loop oscillator consist of an op-amp comparator, an inductor (the loop) capacitor pair, some feedback resistors, and control lines. The inductor (the loop) is coupled to the circuit via an isolation transformer. The purpose of the transformer, as its name suggests, is to electrically separate the oscillator circuitry from the loop in the street. This contributes to the circuitry by dampening the effects of static discharges, and permits lower grade loops to operate properly. The transformer is paralleled with a capacitor to form a tank circuit. A tank circuit oscillates at a resonant frequency when excited by a voltage source. The op-amp comparator provides the excitation source, and via positive feedback resistors, it is the crucial component in sustaining excitation at the resonant frequency, and squaring up the output so it can be seen as a digital signal. Each oscillator circuit has control lines that initiate or stop its operation. 4.3 Gate Array Counter The gate array counter enables the use of a high frequency source for the count basis. The squared up output from the oscillator is fed into the gate array. The gate array circuitry then establishes a high-resolution measurement of the amount of time that has passed between a preset number of oscillations. If a frequency difference occurs in the oscillator, it is seen as a change in the measurement time in the gate array. This information is then made available to the micro-controller. 4.4 Micro-Controller The micro-controller is the brains of the detector. It is responsible for coordinating the operation of the gate array counter and the loop oscillators. The micro-controller is also responsible for reading the user switches and determining the sensitivity setting that the user requested. Based upon that information, the micro-controller is able to control the loop oscillators in order to operate them in a manner that will provide the information desired. Naztec, Inc. 7
5. Troubleshooting The following section discusses troubleshooting and repair of the electronics for the 724/224. All proper electrostatic precautions and standard debug common sense should be used. 5.1 Required Equipment Troubleshooting of the 722/224 loop detector requires basic technician equipment. The following list includes all the tools necessary to complete the troubleshooting procedures in this section. Oscilloscope Multi-meter (or volt-meter & continuity checker) DIP & PLCC chip remover Solder Iron & Solder Needle Nose Pliers Flat-Head Screwdriver Test Jig The following test routines require a simply constructed test jig. The jig must provide a place to connect the loops, and pull-ups to 24 VDC for each of the outputs. Do no forget to ground the detect output emitter pins. The following diagram clarifies the jig requirements for the outputs. 24 VDC CH# (+) 1.5KΩ CH# (-) Status 1.5KΩ Naztec, Inc. 8
5.2 Problem Isolation A quick inspection of the loop detector circuitry can offer a lead for isolating the problem. However, prior to hunting a cursory inspection should take place. Test Point Convention To specify a specific IC or component, the following notation will be used: Ref Designator [Pin Number/Name] Examples: U5 [62] means IC U5 pin 62 Z1 [Cathode] means zener diode Z1 cathode pin D9 [Anode] means diode D9 anode pin Cursory Inspection 1. Verify 5 VDC at U7 [40], U4[8], and U5[12] NO: suspect 5 VDC power supply 2. Verify 12 VDC at U9 [8], U10[8], U11[8], and U12[8] NO: suspect 12 VDC power supply Symptom No lights at power up All lights on solid at power up Detector never tunes Channel shows constant fault Detect light active, but no output Frequency switch has no effect Sensitivity switch has no effect No detection indication No fault indication Suspect Power Supply / Processor Processor / User Interface (reset switch) Oscillator Oscillator Output Circuitry User Interface User Interface User Interface User Interface Naztec, Inc. 9
5.3 User Interface Repair Problems in the user interface are rare. However, evidence of their existence includes such things as the detector failure to respond to sensitivity or frequency setting. Other evidence includes lights that fail to turn on or turn off. 5.3.1 Reset Switch Remove power from detector and do not depress reset switch 1. Open circuit between U7 [20] and U4 [3]? NO: suspect reset switch (SW4) 2. Open circuit between U7 [20] and U7 [1]? NO: suspect reset switch (SW4) Remove power and hold in the reset switch for the following test. 3. Closed circuit between U7 [20] and U4 [3]? NO: suspect reset switch (SW4) 4. Closed circuit between U7 [20] and U7 [1]? NO: suspect reset switch (SW4) 5. The reset switch is functioning properly; suspect the processor reset circuitry. 5.3.2 Sensitivity Switches Remove power from detector and set ALL front panel switches to OFF (to the right). The following table is used for this test: Switch Test Point Switch Test Point CH1 1 U5[29] CH2 1 U5[25] CH1 2 U5[28] CH2 2 U5[24] CH1 4 U5[27] CH2 4 U5[23] CH1 8 U5[26] CH2 8 U5[21] CH3 1 U5[46] CH4 1 U5[39] CH3 2 U5[45] CH4 2 U5[37] CH3 4 U5[44] CH4 4 U5[35] CH3 8 U5[40] CH4 8 U5[30] 1. With the switch in the OFF position, is the circuit open between U7 [20] and the test point? NO: suspect switch bank 2. With the switch in the ON position, is the circuit closed between U7 [20] and the test point? NO: suspect switch bank 3. The switch is operating properly; suspect the FPGA (U5) inputs. Naztec, Inc. 10
5.3.3 Frequency Switches Remove power from detector and set ALL front panel switches to OFF (to the right). The following table is used for this test. It will be necessary to refer to the PCB silkscreen drawing provided with the schematics in order to properly identify the components. Switch Test Component Switch Test Component CH1 A C19 CH2 A C28 CH1 B C18 CH2 B C26 CH3 A C35 CH4 A C42 CH3 B C34 CH4 B C41 1. With the switch in the OFF position, is the circuit open across the test capacitor? NO: suspect switch bank 2. With the switch in the ON position, is the circuit closed across the test capacitor? NO: suspect switch bank 3. The switch is operating properly; suspect loop oscillator. 5.3.4 Fault LEDs This test requires that the detector be powered up with no loops connected and all channels active. This will cause each channel to go into a fault mode. They will activate the fault LED and the fault output. Fault LED LED Test Point Output Test Point CH1 U5[81] U14[5] CH2 U5[82] U14[6] CH3 U5[83] U14[7] CH4 U5[84] U14[8] 1. +5 VDC at Output Test Point? NO: detector is not generating fault outputs, suspect processor/fpga 2. 0 VDC at LED Test Point? NO: FPGA not driving LEDs, suspect processor/fpga 3. Fault LED Lit? NO: suspect bad LED Attach loops to each of the channels and allow the detector to tune up with no cause for fault. 4. 0 VDC at Output Test Point? NO: detector is generating bogus fault outputs, suspect processor/fpga 5. 5 VDC at LED Test Point? NO: FPGA outputs generating bogus fault output, suspect processor/fpga Naztec, Inc. 11
6. 0 Fault LED Dark? NO: suspect bad LED 7. The fault LED and associated circuitry is operating properly, no suspects 5.3.5 Detect LEDs This test requires that the detector be powered up with loops connected and all channels active. Place a call on all channels. Detect LED LED Test Point Output Test Point CH1 U5 [75] U14 [1] CH2 U5 [76] U14 [2] CH3 U5 [77] U14 [3] CH4 U5 [78] U14 [4] 1. 0 VDC at Output Test Point? NO: detector is not generating detect outputs, suspect processor/fpga 2. 0 VDC at LED Test Point? NO: FPGA not driving LEDs, suspect processor/fpga 3. Detect LED Lit? NO: suspect bad LED Attach loops to each of the channels and allow the detector to tune up with no cause for fault or detection. 4. 5 VDC at Output Test Point? NO: detector is generating bogus detect outputs, suspect processor/fpga 5. 5 VDC at LED Test Point? NO: FPGA outputs generating bogus detect output, suspect processor/fpga 6. Detect LED Dark? NO: suspect bad LED 7. The detect LED and associated circuitry is operating properly, no suspects Naztec, Inc. 12
5.4 Processor Repair The processor and the FPGA are responsible for the oscillator sequencing, output controls, and interpretation of user interface. Usual processor / FPGA failures are catastrophic, or manifest themselves through other problems. This portion of the troubleshooting section concentrates on the major failures. The subsystem debug will reveal the non-catastrophic failures. 5.4.1 Processor Reset Circuitry This test requires that the detector be powered up at the proper operating voltage. 1. 24 VDC at J2 [B]? NO: proper supply power is not present, suspect test jig 2. Z1 [Anode] greater than 5 VDC? NO: drop across zener diode (Z1) too large, suspect zener (Z1) or switch (SW4) 3. 5 VDC at U7 [1]? NO: processor not receiving reset from FPGA; suspect FPGA 4. No problem with the reset line exists; suspect the FPGA (U5) or the ROM (U4) 5.4.2 Processor 1. 5 VDC at U7 [40]? NO: processor has no power; suspect 5 VDC supply 2. 5 VDC at U7 [1]? NO: processor not receiving reset from FPGA; suspect FPGA 3. Does the following signal appear at U7 [39]? NO: YES: processor not receiving clock from FPGA, suspect FPGA continue 4. The basic signals for processor operation exist. However, the chip may be damaged internally, or the I/O lines may be damaged. Check the affected subsystem that is listed in this section, or swap chip with a known operating chip. If the problem is remedied, then replace the chip; else inspect the affected subsystem. Naztec, Inc. 13
5.4.3 FPGA 1. 5 VDC at U5 []? NO: FPGA has no power; suspect 5 VDC supply 2. 5 VDC at U5 [54]? NO: FPGA not receiving reset; suspect reset circuitry. 3. Does the following signal appear at U5 [57]? NO: YES: Crystal oscillator damaged. Suspect crystal (Y1) and capacitors (C2,3) continue 4. The basic signals for FPGA operation exist. However, the chip may be damaged internally, or the I/O lines may be damaged. Check the affected subsystem that is listed in this section, or swap chip with a known operating chip. If the problem is remedied, then replace the chip; else inspect the affected subsystem. 5.4.4 Serial PROM 1. 5 VDC at U4 [8]? NO: PROM has no power; suspect 5 VDC supply 2. 5 VDC at U4 [3]? NO: PROM not receiving reset, suspect reset circuitry. 3. 0 VDC at U4 [4]? NO: PROM not receiving chip enable, suspect FPGA 4. The basic signals for PROM operation exist. However, the chip may be damaged internally, or the I/O lines may be damaged. Check the affected subsystem that is listed in this section, or swap chip with a known operating chip. If the problem is remedied, then replace the chip; else inspect the affected subsystem. Naztec, Inc. 14
5.5 Power Supply Repair The loop detector has two power supplies with a common ground. The processor supply regulates the 24 VDC down to 5 VDC, and the oscillator supply regulates the 24 VDC down to 12 VDC. 5.5.1 24 VDC Input This test requires that the detector be powered up at the proper operating voltage. 1. 24 VDC at J2 [B]? NO: proper supply power is not present; suspect test jig 2. Voltage across R1 less than.150 VDC? NO: too much current draw, visually look for short, suspect power supply or IC failure 3. Voltage across R2 less than 8 VDC? NO: suspect 5 VDC supply, or component failure on 5 VDC bus 4. Voltage at Z1 [Anode] less than 8VDC? NO: suspect processor reset circuitry 5. 24 VDC portion of power supply appears to be functioning properly, check other portions. 5.5.2 5 VDC Supply This test requires that the detector be powered up at the proper operating voltage. 1. 24 VDC at J2 [B]? NO: proper supply power is not present; suspect test jig 2. Voltage at U1 [3] greater than 5 VDC? NO: suspect regulator (U1) 3. Voltage at U1 [3] less than 5 VDC? NO: suspect regulator (U1), or component failure on 5 VDC bus 4. There appears to be no problems with the 5 VDC supply 5.5.3 12 VDC Supply This test requires that the detector be powered up at the proper operating voltage. 1. 24 VDC at J2 [B]? NO: proper supply power is not present; suspect test jig Naztec, Inc. 15
2. Voltage at U1 [3] greater than 12 VDC? NO: suspect regulator (U2) 3. Voltage at U1 [3] less than 12 VDC? NO: suspect regulator (U2), or component failure on 12 VDC bus 4. There appears to be no problems with the 12 VDC supply 5.6 Loop Oscillator Repair The loop oscillator problems usually manifest themselves as unreliable operation or poor performance. Each channel has an identical oscillator circuit. There are many components in the entire oscillator subsystem. The following table indicates test points per channel: Channel Test Point A Test Point B Test Point C Test Point D CH1 U3 [8] U3 [7] U5 [48,49] VR1 & R6 junction CH2 U6 [8] U6 [7] U5 [52,56] VR2 & R15 junction CH3 U8 [8] U8 [7] U5 [58,59] VR3 & R19 junction CH4 U13 [8] U13 [7] U5 [60,61] VR4 & R23 junction This test requires that the detector be powered up at the proper operating voltage. Loops must also be connected and each channel must be activated. 1. Transformer casing has no cracks or defects? NO: suspect transformer 2. 12 VDC at Test Point A? NO: suspect power supply 3. Voltage across Test Point C 5 VDC? NO: suspect FPGA 3. Signal at Test Point B appears as in the graph? *The pulse widths may vary; look for a 25% duty cycle NO: YES: suspect Op-Amp continue Naztec, Inc. 16
3. Signal at Test Point D appears as in the graph? *The pulse widths will vary, look for similar shape and magnitude NO: YES: suspect the transistor continue 4. Main components of the oscillator appear to be properly operating; examine the FPGA 5.7 Output Repair Failure of the fault/status outputs or the detection outputs is usually evident when the LED for the respective output is lit, but the output shows no activation. 5.7.1 Detect Outputs This test requires that the detector be powered up with loops connected and all channels active. Place a call on all channels. Channel Test Point A Test Point B Test Point C CH1 U14 [1] U14 [18] U10 [5] CH2 U14 [2] U14 [17] U12 [5] CH3 U14 [3] U14 [16] U11 [5] CH4 U14 [4] U14 [15] U9 [5] 1. 0 VDC at Test Point A? NO: detector is not generating detect outputs, suspect processor/fpga 2. 5 VDC at Test Point B? NO: suspect output driver (U14) 3..50 VDC or greater at Test Point C? NO: suspect opto-isolator (U9,10,11,12), or transistor (Q4,5,6,7) 4. Channel output inactive (test jig LED dark)? NO: suspect transistor (Q4,5,6,7) Keep detector powered up, but remove all calls. Naztec, Inc. 17
5. 5 VDC at Test Point A? NO: detector is not generating detect outputs; suspect processor/fpga 6..3 VDC or less at Test Point B? NO: suspect output driver (U14) 7..3 VDC or less at Test Point C? NO: suspect opto-isolator (U9,10,11,12), or transistor (Q4,5,6,7) 8. Channel output active (test jig LED lit)? NO: suspect transistor (Q4,5,6,7) 9. The channel output is operating properly. 5.7.2 Fault Outputs This test requires that the detector be powered up with loops connected and all channels active such that no fault is present. Channel Test Point A Test Point B CH1 U14 [5] U14 [14] CH2 U14 [6] U14 [13] CH3 U14 [7] U14 [12] CH4 U14 [8] U14 [11] 1. 0 VDC at Test Point A? NO: detector is generating bogus fault outputs, suspect processor/fpga 2. 5 VDC at Test Point B? NO: suspect output driver (U14) 3. Channel output inactive (test jig LED dark)? NO: suspect short on PCB trace near diode (D8,9,10,11) Keep detector powered up. Remove loops to create a fault on all channels. 4. 5 VDC at Test Point A? NO: detector is not generating fault outputs; suspect processor/fpga 5. 0 VDC at Test Point B? NO: suspect output driver (U14) 6. Channel output active (test jig LED lit)? NO: suspect diode (D8,9,10,11) 7. The channel fault/status output is operating properly. Naztec, Inc. 18
6. Specifications 6.1 Electrical Specifications The following information provides a detailed set of electrical characteristics of the 724/224 Input Power Supply: 24 VDC +/- 25% 200ma MAX (50ma per channel) Reverse Polarity Protection Oscillator Voltage: 8 VDC +/- 5% Logic Voltage 5 VDC +/- 5% Input Transients: Transient Pulse Width: +/-2000 V @ 5 Ohms +/-1000 V @ 0 Ohms 10 usec 6.2 Operational Specifications Self-Tuning: Temperature Tracking: Loop Inductance Range: Loop Frequency Range: Sequential Scanning: The detector is tuned and fully functional within 1 second after power up for most settings. Higher sensitivities may require more time. The detector automatically compensates for frequency shifts due to changes in temperature. 20uH to 2000uH 10 KHz to 80 KHz The loops are energized alternately to eliminate crosstalk on a single card, and reduce it on a system wide scale. Naztec, Inc. 19
6.3 Pin Assignments The following table details the card-edge connector pin assignments: J1 Card Edge Connector PIN A- DC Gnd PIN 1- Inhibit 1 PIN B- DC Gnd PIN 2- Inhibit 2 PIN C- Ext Reset PIN D- Loop 1A PIN 4- Loop 1A PIN E- Loop 1B PIN 5- Loop 1B PIN F- CH1(+) PIN H- CH1(-) PIN 7- Status 1 PIN J- Loop 2A PIN 8- Loop 2A PIN K- Loop 2B PIN 9- Loop 2B PIN L- Earth Gnd PIN P- LOOP 3A PIN 13- LOOP 3A PIN R- LOOP 3B PIN 14- LOOP 3B PIN S- CH3(+) PIN T- CH3(-) PIN 16- Status 3 PIN U- LOOP 4A PIN 17- LOOP 4A PIN V- LOOP 4B PIN 18- LOOP 4B PIN W- CH2(+) PIN X- CH2(-) PIN 20- Status 2 PIN Y- CH4(+) PIN Z- CH4(-) PIN 22- Status 4 Naztec, Inc. 20
7. Parts List and Drawings The following pages contain a component list that details the reference designation, the quantity, a manufacturer s number, and a Naztec internal part number for each component. A PC Board silk screen is also provided to aid in identifying components by reference designator along with the detector schematics. Naztec, Inc. 21