A Complete Analog Front-End IC Design for ECG Signal Acquisition Yang Xu, Yanling Wu, Xiaotong Jia School of Electrical and Computer Engineering Georgia Institute of Technology yxu327@gatech.edu, yanlingwu@gatech.edu, xjia31@gatech.edu Abstract This paper proposes a analog front end design (AFE) that will be used for Electrocardiogram (ECG) signal acquisition using an instrumentation amplifier (IA), a DC blocking high pass filter, a high order anti-aliasing low pass filter, and a successive approximation register analog-to-digital converter (SAR-ADC). The ECG signal will first get amplified by IA, and after filtering, will then go through SAR-ADC for quantization. A PC client will pick up the digitized signal and transform it back to analog waveform. The system will be built upon AMI 0.6 um process. used in the SAR-ADC resulting in a highly digital operation eliminating static power consumption [5]. Figure 1 [6] shows the overall blocks for this AFE. Index Terms Current balancing IA; chopper stabilization ; auto-zeroing; SAR-ADC; ECG; Gm-C filter I. INTRODUCTION Wearable physiological monitoring systems have big advantages over traditional medical equipment because of their convenience and reliability. The information that we collected from patients such as ECG, Electroencephalogram (EEG), skin temperature, or blood pressure are crucial parameters that could reflect and identify patient's physiology status. With wearable devices, medical staff can monitor these important parameters while subject performs daily activities. However, signal sampling is always one of the critical challenges in biomedical system. Signals such as ECG signal has small amplitude around 100 uv with low frequency <1 KHz, sometimes, common-mode signal can be even larger than that of the ECG signal, therefore for acquisition purpose, a high common-mode rejection ratio (CMRR) is required for any instrumentation amplifier we implemented in this design [1]. In this system, besides a low-noise, low-power, high gain and high CMRR amplifier, we will also adapt Auto-zeroing to cancel the offset of IA [2]. And the chopper technique will be used for noise reduction [3]. Removing DC offset is also necessary to improve CMRR. The common frequency band for ECG monitoring is 0.5 Hz - 40 Hz. A high pass filter (HPF) with corner frequency around 0.5 Hz will be implemented. The HPF is mainly used for canceling DC level shift caused by human skin. Some designs use IA with off-chip capacitor as HPF which will occupy more space on printed circuit board (PCB). In this paper, we proposed to use on chip Gm-C filter to achieve the same purpose with smaller area cost [1],[4]. The low pass filter (LPF) with corner frequency of 50 Hz will be designed using RC filter at the output stage of IA. The LPF is mainly used for eliminating noise with frequencies higher than ECG signal. A voltage-to-time domain comparator will be Figure 1. Block diagram of the proposed design for ECG acquisition. II. SYSTEM DESIGN The system consists of an IA, a combination of filters, and a SAR-ADC. For the instrumentation amplifier, gain of 40 db or greater is needed as well as at least 100 db for CMRR. The HPF requires a cutoff frequency of 0.5 Hz and the LPF requires a cutoff frequency of 50 Hz. The SAR-ADC utilize binary searching algorithm to quantize the signal after filtering. For this design, we are aiming a total power consumption of 400 uw with 3.2 V supply voltage. A. Instrumentation Amplifier Design For IA design, we have come up with two design topologies. The first design consists of three operational amplifiers with several matching resistors to achieve high CMRR, as shown in Figure 2 below. Figure 2. General topology for IA design with three opamps.
For IA design, DC offset is a problem that related to both positive supply rejection ratio (PSRR) and CMRR. To achieve very high PSRR and CMRR, the DC offset needs to be eliminated. By using auto-zeroing technique, we can achieve offset cancellation. Figure 3 shows how the auto-zeroing is applied to an op-amp. This topology has two phases of operation. First phase (Phi1 is on, Phi2 is off) is offset restoring which the op-amp s DC offset Vos will be stored in capacitor, in this case, C1. When phase two(phi2 is on, Phi1 is off) operates, C1 and Vos are in series, voltage stored in C1 cancels Vos and therefore achieve offset cancellation. Figure 5. Chopper-stabilization op-amp schematic. Figure 3. Schematic of applying auto-zeroing to an op-amp. At low frequency domain, flicker noise is the dominate interference to the ECG signal as shown in Figure 4 [3]. Therefore, we will use chopper technique to shift the flicker noise of the two op-amps at the input stage to a higher frequency and later being filtered out by LPF thus not interfering the ECG signal anymore. Figure 6. IA design using both auto-zeroing and chopper techniques. For current-balancing IA, the amplifier consists with a transconductance stage and a transimpedence stage. The idea of the current balancing amplifier is depicted in Figure 7 [7]. Figure 4. Noise power spectrum of standard CMOS opamp. Figure 5 shows how the chopper-stabilization amplifier operates. The input signal is first up-converted to chopper frequency before enter the differential input pair of the op-amp. The input signal is later down-converted back to its original frequency by entering the 2 nd chopper modulator. However, the noise occurred in the circuit only enter the chopper modulator once and therefore is up-converted to chopper frequency, therefore, by setting chopper frequency high, we are able to separate noise from ECG signal in the frequency domain. By applying both auto-zeroing and chopper techniques to our IA design, as shown in Figure 6, we are able to have a low-noise and high gain IA. The disadvantages of this topology are its high power consumption and large area occupation. Based on [6], such an IA can consume 1.3 mw of power under 1.2 V voltage supply, which way exceeds our design specifications of 400 uw. Therefore, the current-balancing topology is proposed as our second solution for our IA design. Figure 7. Simplified model for current balancing IA. The voltage across differential pair of the input stage generates current output and this current is mirrored by the current mirror to the output stage. Therefore, the gain is simply the output impedance over the input impedance of this IA. Figure 8 [1] is the schematic of our proposed IA design with current-balancing technique. The differential voltage input V in1 and V in2, are converted by the transconductance stage into differential current i g whcih goes through R g. The current mirror composed by M5 - M16 mirrors i g to the transimpedence stage as i s, i s goes through R s which forms a differential output voltage pair at M19 and M20. Therefore, the gain of this IA is A d = R s / R g. For this design, a perfectly matched cascade current mirror is necessary for yielding very high CMRR and PSRR. By applying this topology, we are able to manage the power consumption of IA under 100 uw, which is way smaller than the first topology.
Figure 8. Schematic of proposed current-balancing IA with a Gm-C HPF. However, further adjustment to the design topology will be made to meet the specifications. B. Filter Design The HPF is designed to cancel low frequency noise as well as eliminate DC offset. We proposed to use Gm-C filter which can yield a large resistance without too much area cost. Gm-C filter is implemented as shown in Figure 9. V ref is coupled to T24 and the low cutoff frequency is achieved by the feedback path from M20 to T25, a very large C filter is required and thus still occupy a lot of spaces. Therefore, an alternative way of design is by realizing the transconductance of this filter Gm is directly propotional to the -3 db cutoff frequency, we can implement an OTA which usually has very small Gm. By implementing such small Gm OTA as shown in Figure 8, we can bias MR1 and MR2 into triode region by tuning MC1 s size. The voltage difference of MM1 and MM2 is converted to current goes through MR1 and MR2. One thing needs to be noticed is that MM_1 and MM_2 must be much larger than M1_1 and M1_2 so the current get divided into M1_1 and M1_2 is much smaller than that of MM. The overall Gm is expressed in function below. M is the gate ratio of MM to M1, g o MR is the conductance of MR1 and MR2, and W, L, V G, V CM, V T are all parameters related to MR1,2. By looking at the expression, we can increase M or decrease V G - V CM - V T term to achieve a small Gm. C. Biasing Circuit The biasing circuit is composed of a start-up circuit and a beta multiplier to generate two bias voltage V biasp and Vbiasn. All the transistors are operating in saturation region and by tuning MM1 - MM4 and R1, we are able to generate the bias voltage. Figure 9. Schematic for a Gm-C filter
D. ADC Design In low voltage ADC design, one of the most important design factor is the resolution of the comparator because the voltage of 1 LSB decreases as supply voltage decreases, but meanwhile the circuit induced noise is not scaled down by the same factor. Therefore, it is crucial to reduce the effect of noise. In this design, we proposed to use time-domain comparator. The proposed comparator uses highly digital differential delay architecture operating in a very low power supply voltage. By cascading multi- stage delay cells, the input referred noise and offset can be greatly reduced by this comparator. Figure 10 shows the proposed time-domain comparator which consists of two differential voltagecontrolled lines (VCDL) and a binary phase detector. The VCDLs correspond to the differential input stage of the preamplifier for comparison [5]. The digital swing of VCDL s internal nodes eliminates the static power consumption and therefore makes it possible to reduce the supply voltage to its minimal required level for proper digital circuit operation. When CLK is high, both outputs of VCDLS are set to zero. When the CLK goes to low, the current-limiting transistors in one of the VCDLs exhibit higher current which produce a nonzero differential delay to the CLK propagation. Because a N-stage delay chain increase V-to-T gain by N while the random noise and offset are increased only by N 1/2, therefore we achieve an overall noise reduction by N 1/2. (a) Figure 10. Architecture of SAR-ADC. Figure 11. Timing diagram of SAR-ADC. This ADC conversion requires 12 clock cycles. The first cycle is reset which initialize node voltages in DAC. During the second circle, the output of CDACs are both raised to V DD /2 which is the common-mode analog inputs for sampling differential input voltage. In next 10 cycles, the conversion of data is performed. The operation modes of CDAC is shown in Figure 12. Time-domain comparator compare the voltage difference between VDAC and VDAC to a delay difference which can be sensed by phase detector (PD) whose schematic is shown in Figure 13 [5]. (b) Figure 9. Circuit schematic of (a) time-domain comparator (b) VCDL. We proposed a 10-bit SAR-ADC design consists of a timedomain comparator, two capacitive digital-to-analog converters (CDACs), a successive approximation register, and a logic controller. Figure 10 [6] shows architecture of this SAR-ADC design and Figure 11 [5] provides a timing diagram of the ADC. Figure 12. Three operation modes for CDAC.
Figure 13. Schematic of the phase detector. III. EXPERIMENT RESULTS In order to obtain a straightforward impression of the performance of the system-on-chip proposed, simulations with ideal OpAmp are conducted in LT Spice and Cadence Virtuoso. A. Instrumentation Amplifier IA with the topology of general three OpAmps is simulated first, there are no switches in the schematic since AC gain is the object being investigated first, the schematic of this IA is shown in Fig. 14. In Fig. 15, it can be observed that the gain is 41 db, close to the hand calculation, and the f 3dB is 96.6 khz, which is beyond the ECG signal frequency range. However, it is obvious that eight resistors are put into application, which will cost large area and consume significant power to drive all resistors. To avoid these drawbacks, the next version of IA design is based on the topology of current-balancing IA shown in Fig. 8. B. Filter The frequency range ECG signal for monitoring is from 0.5 Hz to 50 Hz, to reduce the impact of flicker noise and the interference from higher frequency, a bandpass filter should be implemented, which can be realized in several approaches. The first and the simplest method is to use resistors and capacitors, and the circuit and simulation result are presented in Fig. 16 and Fig. 17, respectively. Fig. 16 RC Band Pass Filter Fig. 14 Three-OpAmp-Based IA without Switch The aim is to obtain a 40 db gain, based on hand calculation, which can be written as 400k 600k A v 150 43.5dB 4k 400k And the corresponding simulation result is presented in Fig. 15. Fig. 17. Frequency Response of BPF Large resistors in Giga Ohm can be a pain in the chip, consuming a large amount of power, although frequency range is achieved. The second approach is the application of Gm-C filter, which is shown in Fig. 18. And the simulation result is presented in Fig. 19. Fig. 15. Frequency Analysis of Three-OpAmp-Based IA Fig.18. Gm-C LPF
to achieve a symmetrical structure in IA with the function of signal amplification, and Gm-C filter is utilized to obtain the low frequency of 0.5 Hz to avoid the application of large resistors and capacitors. SAR-ADC realized analog to digital converting. Fig. 19. AC Analysis of Gm-C LPF The capacitor in Fig. 18 is 400 pf when all transistors are in saturation region. As we can see in Fig. 19., the cut off frequency is 47.6 Hz, after fine tuning the perfect 50 Hz cut off frequency can be obtained. However, it can be found that there is no resistor while the capacitor is larger than that of in the RC filter. To address this issue, in the next step, the topology in Fig. 8 will be implemented to boost the performance of the filter. IV. WORK DISTIBUTION AND SPECIFICATION TABLE I. Supply Voltage Process Technology Gain of IA Power consumption Input referred noise (rms) CMRR PSRR HPF corner frequency LPF corner frequency DESIGN SPECIFICATIONS ADC ENOB >9 3.2 V AMI 0.6 um >40 db 400 uw 100 nv >90 db >60 db 0.5 Hz 50 Hz REFERENCES [1] Chia-Hao Hsu, Chi-Chun Huang, Kian Siong, Wei-Chih Hsiao and Chua-Chin Wang, "A high performance current-balancing instrumentation amplifier for ECG monitoring systems," 2009 International SoC Design Conference (ISOCC), Busan, 2009, pp. 83-86. doi: 10.1109/SOCDC.2009.5423877. [2] Chih-Jen Yen, Wen-Yaw Chung and Mely Chen Chi, "Micro-power low-offset instrumentation amplifier IC design for biomedical system applications," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 4, pp. 691-699, April 2004. doi: 10.1109/TCSI.2004.826208. [3] A. Bakker, K. Thiele and J. H. Huijsing, "A CMOS nested-chopper instrumentation amplifier with 100-nV offset," in IEEE Journal of Solid-State Circuits, vol. 35, no. 12, pp. 1877-1883, Dec. 2000. doi: 10.1109/4.890300 [4] C. Nanda, J. Mukhopadhyay, D. Mandal and S. Chakrabarti, "A CMOS instrumentation amplifier with low voltage and low noise for portable ECG monitoring systems," 2008 IEEE International Conference on Semiconductor Electronics, Johor Bahru, 2008, pp. 54-58. doi: 10.1109/SMELEC.2008.4770276. [5] S. K. Lee, S. J. Park, H. J. Park and J. Y. Sim, "A 21 fj/conversion-step 100 ks/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface," in IEEE Journal of Solid-State Circuits, vol. 46, no. 3, pp. 651-659, March 2011. doi: 10.1109/JSSC.2010.2102590. [6] Y. J. Lyu, Q. X. Wu, P. S. Huang and H. C. Chen, "CMOS analog front end for ECG measurement system," 2012 International Symposium on Intelligent Signal Processing and Communications Systems, Taipei, 2012, pp. 327-332. doi: 10.1109/ISPACS.2012.6473505. [7] Honglei Wu and Yong-Ping Xu, "A low-voltage low-noise CMOS instrumentation amplifier for portable medical monitoring systems," The 3rd International IEEE-NEWCAS Conference, 2005., 2005, pp. 295-298. doi: 10.1109/NEWCAS.2005.1496659. TABLE II. Member Yang Xu Yanling Wu Xiaotong Jia Xiangyu Mao (audit) TEAM WORK DISTRIBUTION Tasks SAR-ADC, Layout IA, Gm-C filter, Layout Biasing Circuit SAR-ADC V. CONCLUSION In this paper, we proposed a system-on-chip for ECG monitoring, which is mainly consist of an IA, Gm-C highpass filter and a SAR-ADC. Current balancing technique is chosen