70 CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS A novel approach of full adder and multipliers circuits using Complementary Pass Transistor with Asynchronous Adiabatic Logic (CPTAAL) are described in this chapter. The CPTAAL and its design details for the implementation of full adder and multiplier circuits are also discussed. The performance analysis of the proposed designs of asynchronous adiabatic CMOS circuit design styles such as CPTAAL, DPTAAL and DRDAAL are reported and discussed in further sections. 5.1 COMPLEMENTARY PASS TRANSISTOR LOGIC (CPL) Complementary pass-transistor logic (CPL) refers to a logic family which is designed for specific advantages. CPL uses series of transistors to select between possible inverted output values of the logic, by which output can be used to drive an inverter to generate the non-inverted output signal. Inverted and non-inverted inputs are required to drive the gates of the pass-transistors. The main concept behind CPL is the use of an NMOS pass-transistor network for logic organization. CPL consists of complementary inputs/outputs and NMOS passtransistor logic network, CMOS output inverters. These inverters can be replaced by PMOS latches. The high level of the pass-transistor outputs
71 (nodes Q and Q') is a threshold voltage which is lower than the supply voltage. This loss in output voltage is pulled up by PMOS latches or CMOS output inverters. To maintain high speed switching and to make sure that the output signal has the same voltage swing as the input signal, it is important to use the PMOS latches or output inverters. This has the disadvantage that spikes occur on the power supply during switching. The input voltage-levels are equivalent to those of standard CMOS, and this has the disadvantage that the voltage-swing is equal to Vdd, as reported in Dai et al (2006). Complementary pass-transistor logic (CPL) uses a complementary output pass-transistor logic network to perform logic evaluation and CMOS inverters for driving of the outputs. The main concept behind CPL is the use of only NMOS network for the implementations of logic functions. This results in low input capacitance and high speed operation. The schematic diagram of the CPL full adder circuit is shown in the Figure 5.1. Because the high voltage level of the pass-transistor outputs is lower than the supply voltage level by the threshold voltage of the pass transistors, the signals have to be amplified by using CMOS inverters at the outputs, as reported in Zimmermann & Fichtner (1997). CPL circuits consume less power than conventional static circuits because the logic swing of the pass transistor outputs is smaller than the supply voltage level.
72 Figure 5.1 CPL full adder cell The switching power dissipated from charging or discharging the pass transistor outputs is given by, P D =V dd V swing C node f (5.1) Where V swing =V dd -V tn.
73 In the case of conventional static CMOS circuits the voltage swing at the output nodes is equal to the supply voltage resulting in high power dissipation. To minimize the static current due to the incomplete turn-off of the pmosfet in the output inverters, a weak pmosfet feedback device can also be added in the CPL circuits, in order to pull the pass-transistor outputs to full supply voltage level, as reported in Hu et al (2004). 5.2 CPTAAL DESIGN DESCRIPTIONS In this section, a framework for designing a low power full adder and multiplier circuits using CPTAAL designs are discussed. A unique approach, called complementary pass transistor with asynchronous adiabatic logic (CPTAAL) has been followed in these designs. Complementary pass transistor logic (CPL) is suitable for complex arithmetic circuits where no compromise on power dissipation is allowed. This technique is combined with asynchronous adiabatic logic (AAL) to obtain the energy saving benefits with improved circuit performance in full adder and multiplier designs. The main objective of this work is to design low power full adder using asynchronous adiabatic logic. The logic scheme for the proposed full adder cell is illustrated in Figure.5.2. In this, the entire system consists of two main blocks, namely logical block and control and regeneration (C&R) block.
74 Figure 5.2 Logic scheme for the proposed CPTAAL design As in Figure.5.2, data output signal of any adiabatic CPL block is not only going into next adiabatic CPL block as data input, but also, it is used to generate a control signal for the next adiabatic CPL block using C&R block. This technique helps to save the required power clock generator with less power than any other designs as reported by the authors Arsalan & Shams (2005). 5.2.1 CPTAAL Full Adder The schematic diagram of the CPTAAL full adder circuit is shown in Figure 5.3. In this, asynchronous adiabatic full adder logic uses complementary pass-transistor logical block with C&R structures. The main difference of pass-transistor logic design compared to the CMOS logic design is that the source side of the logic transistor networks is connected to some input signals instead of the power lines, as reported in Hu et al (2005).
75 Figure 5.3 CPTAAL full adder logic diagram The benefit is that one pass-transistor network (either NMOS or PMOS) is sufficient to perform the logic operation, which results in a smaller number of transistors and smaller input loads, especially when NMOS networks are used. The proposed CPTAAL design uses an NMOS network for the implementation of logic functions and has differential inputs and outputs, thus resulting in low input capacitance, good output driving capability and
76 high-speed operation. As the high voltage level of the pass-transistor outputs is lower than the supply voltage level by the threshold voltage of the pass transistors, the signals have to be amplified by using CMOS inverters at the outputs. All these CPTAAL full adder blocks have been designed with PMOS/NMOS transistors, focusing low power consumption and high efficient operation. Table 5.1 illustrates the final sizes of the transistors used in each design block of the CPTAAL full adder. Table 5.1 Transistors sizes used in each design block of CPTAAL full adder PMOS NMOS Design Blocks Minimum Length (µm) Width (µm) Minimum Length (µm) Width (µm) Adiabatic CPL Gates 0.18 5.0 0.18 5.0 C&R section 0.18 5.0 0.18 2.0 5.2.2 CPTAAL Multiplier The proposed multiplier design scheme is illustrated in Figure.5.4. In this, data output signal of any CPTAAL full adder is not only going into next CPTAAL full adder as data input. But also, it is used to generate a control signal for the next CPTAAL full adder using C&R block 1. This technique helps to save the required power clock generator with less power. This approach gives the feasibility of using the adiabatic logic in real time implementations.
77 Figure 5.4 Logic scheme for the proposed CPTAAL multiplier design In this CPTAAL multiplier design, Control block is used to follow and preserve the power clock sequences with the input vectors. Regeneration gives power saving strategy. All logic gates or logic sequences are connected through C&R structure. The throughput of the logical systems is reduced by the intermediate C&R blocks due to the asynchronous mode of operation. The speed of operations can be compensated for the higher input frequency due to the improvement of speed grade of proposed asynchronous adiabatic logic, as reported in Wang et al (2007). 4 bit and 8 bit multipliers with energy efficient full adder using CPTAAL have been implemented and compared.
78 5.3 SIMULATION RESULTS CPTAAL full adder cell design using asynchronous adiabatic logic with complementary pass transistor is implemented. The simulation results of the CPTAAL full adder are presented in Figure 5.5, for the various combinations of the inputs from 000 to 111. The Power clock sequence for this full adder structure is shown in this simulation results and it is based on the conventional structure. These simulation results are obtained for a periodic sequence as represented in the Figure 5.5, propagated through the buffer chain. The CPTAAL full adder and multiplier design are studied and simulated on TSMC 0.18-μm CMOS process models in Tanner EDA tools with SPICE support, at 1.8V supply voltage. The standard values of gate capacitances and other MOSFET model parameters were included in this simulation. The simulation parameters of this process technology are discussed and summarized in Table 3.2, of chapter 3.
79 Figure 5.5 Simulation results of CPTAAL full adder cell 5.4 PERFORMANCE ANALYSIS AND DISCUSSION The performance analysis of the proposed CPTAAL design is discussed in this section. For the various frequency ranges, the average power consumed, delay of the circuit and power-delay product (PDP) of the proposed CPTAAL full adder is obtained and compared with the conventional CMOS full adder and the synchronous adiabatic full adder designs namely, PFAL, TGAL adders. The proposed CPTAAL design performances are also compared with DPTAAL and DRDAAL designs. By comparing the performance of the proposed design with DPTAAL, DRDAAL, PFAL, TGAL and CMOS designs, the proposed CPTAAL full adder circuit design exhibits less power consumption and a good robustness against technological parameter variations. This is reported in Table 5.2.
80 Table 5.2 Performance analysis of CPTAAL full adder with different logic designs Performance Metrics Logic Design Frequency (MHz) 1 10 100 200 300 CPTAAL 0.074 0.096 0.147 0.206 0.281 DPTAAL 0.116 0.135 0.197 0.342 0.554 Power (μw) DRDAAL 0.182 0.222 0.265 0.550 0.72 PFAL 0.21 0.25 0.5 3.2 5.6 TGAL 0.35 0.7 1.3 3.65 6.2 Conventional CMOS 0.7 1.12 2.95 7.54 13.2 CPTAAL 54 51 48 45 41 DPTAAL 43 40 38 35 31 Delay (ns) DRDAAL 34 31 29 24 21 PFAL 35 31 28 23 19 TGAL 46 41 38 20.05 13.7 Conventional CMOS 107 67 25 10 5.7 CPTAAL 4 4.9 7.1 9.3 11.52 DPTAAL 5 5.4 7.5 12 17.2 PDP (µw-ns) DRDAAL 6.2 6.9 7.7 13.2 15.12 PFAL 7.35 7.75 14 74 106.4 TGAL 16 29 49 73 85 Conventional CMOS 75 75 75 75 75
Power (µw) 81 As reported in Table 5.2, CPTAAL full adder circuit consumes less power than that of the conventional designs. The proposed design exhibits better PDP than the conventional designs. CPTAAL full adder design features the lowest power consumption per additions as compared with conventional CMOS design. HSPICE simulations showed power savings up to 93% in this full adder design, for clock rates ranging from 1MHz to 300MHz maintaining proper functionality. The Power consumption of proposed CPTAAL full adder circuit is compared with DPTAAL and DRDAAL full adder circuit designs and shown in the Figure 5.6. From this comparison graph, it is observed that the proposed CPTAAL design of full adder circuit achieves significant power savings as compared with DPTAAL and DRDAAL full adder circuit designs for clock rates ranging from 1MHz to 300MHz. Power Comparison CPTAAL DPTAAL DRDAAL 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 10 100 200 300 Frequency (MHZ) Figure 5.6 Power comparison of the proposed adders for different frequencies
Delay (ns) 82 The CPTAAL full adder circuit delay is compared with DPTAAL and DRDAAL full adder circuit designs and shown in the Figure 5.7. From this comparison graph, it is observed that the proposed DRDAAL design of full adder circuit exhibits less delay as compared with CPTAAL and DPTAAL full adder circuit designs for the various clock rates. CPTAAL DPTAAL DRDAAL 60 50 40 30 20 10 0 1 10 100 200 300 Frequency (MHZ) Figure 5.7 Delay comparison of the proposed adders for different frequencies The power delay product of CPTAAL full adder circuit is compared with DPTAAL and DRDAAL full adder designs and shown in the Figure 5.8. The obtained PDP of this full adder is specified in μw-ns. From this comparison graph, it is observed that the proposed CPTAAL design of full adder circuit exhibits better PDP than the DPTAAL and DRDAAL designs for clock rates ranging from 1MHz to 300MHz.
PDP (µw-ns) 83 CPTAAL DPTAAL DRDAAL 20 15 10 5 0 1 10 100 200 300 Frequency (MHZ) Figure 5.8 PDP comparison of the proposed adders for different frequencies A 4x4 and 8x8 multiplier circuits using CPTAAL full adder are designed and simulated, which exhibit low power and reliable logical operations for the various clock rates. For the various frequency ranges, the average power consumed of the proposed CPTAAL multiplier is obtained and compared with the other proposed designs, reported in Table 5.3. The proposed CPTAAL multiplier design achieves significant power savings than DPTAAL and DRDAAL multiplier designs.
84 Table 5.3 Power consumption of CPTAAL, DPTAAL and DRDAAL multipliers No. of Bits Frequency 1 MHZ 10 MHZ 100 MHZ 200 MHZ 300 MHZ CPTAAL (µw) 4 bit 0.132 0.318 1.8 2.145 2.896 8 bit 0.156 0.494 2.296 4.365 6.846 DPTAAL (µw) 4 bit 0.19 0.39 1.75 2.42 3.21 8 bit 0.25 0.51 2.42 5.02 8.09 DRDAAL (µw) 4 bit 0.2 0.4 2.3 2.9 4.2 8 bit 0.3 0.6 2.9 5.9 9.7 The power comparison graph for 4x4 and 8x8 CPTAAL, DRDAAL and DPTAAL multiplier is shown in Figure 5.9. The Power consumption of this multiplier is specified in micro-watts (μw). From this comparison graph, it is observed that the proposed CPTAAL design of multiplier circuits achieves significant power savings for clock rates ranging from 100MHz to 300MHz.
Power (µw) 85 4 bit CPTAAL 4 bit DPTAAL 4 bit DRDAAL 8 bit CPTAAL 8 bit DPTAAL 8 bit DRDAAL 12 10 8 6 4 2 0 1 10 100 200 300 Frequency (MHZ) Figure 5.9 Power consumption of proposed multipliers for different frequencies 5.5 QUALITATIVE COMPARISION OF LOGIC DESIGNS The qualitative comparison of four logic designs CMOS, CPL, DPL and DRDL which influences circuit performance and power consumption are given in Table 5.4. In particular, the number of MOS logic networks, the output driving capabilities, the presence of input/output decoupling, the number of signal rails, and the robustness with respect to voltage scaling for the logic styles are discussed. In CMOS, Logic gates are built from an NMOS pulldown and a PMOS pull-up logic network. A key deprivation of CMOS is the relatively weak output driving capability due to series transistors in the output stage.
86 CPL gate consists of two NMOS logic networks (one for each signal rail), two small pull-up PMOS transistors for swing restoration, and two output inverters for the complementary output signals. The good output driving capability is achieved due to the output inverters in CPL. The main concept behind CPL is the use of an NMOS passtransistor network for logic organization, which results in low input capacitance and high speed operation. In DPL, the robustness with respect to voltage scaling is high, which improves circuit performance at reduced supply ranges. Its symmetrical arrangement and double transmission characteristics compensate for the speed degradation arising from the use of PMOS and NMOS pass transistors. In DRDL, the dynamic circuit consists of a pmosfet precharge transistor and an nmosfet evaluation transistor with the clock signal applied to their gate nodes, and an nmosfet logic block which implements the required logic function. DRDL eliminates the spurious transitions and the corresponding power dissipation. This is discussed in Zimmermann & Fichtner (1997). Table 5.4 Qualitative comparison of logic designs Logic Designs No. of MOS Logic Output Driving Capability Input / Output Decoupling Signal Rails Robustness CMOS n+p Medium-Good Yes Single High CPL 2n Good Yes Dual Medium DPL 2n+2p Good Yes Dual High DRDL n+p Good Yes Dual High
87 In the proposed designs, the transistor count of the DPTAAL full adder is increased as compared with CPTAAL and DRDAAL designs. Hence a large on-chip area overhead is associated with DPTAAL design. Taking into consideration the gain in energy efficiency and performance, the area overhead is acceptable. The transistor count of the proposed full adders is compared with conventional CMOS and adiabatic full adders. It is given in Table5.5. The circuit area of the proposed full adders is compared. It is given in Table 5.6.The area of this circuit is specified in μm2. Table 5.5 Transistor count comparison of full adder designs Logic Design No. of Transistors CPTAAL 56 DPTAAL 65 DRDAAL 52 PFAL 38 TGAL 60 Conventional CMOS 28 Table 5.6. Area comparison of proposed full adder designs Logic Design Area ( µm 2 ) DRDAAL 46.8 CPTAAL 50.4 DPTAAL 58.5 Based on these proposed AAL designs, it is observed that the CPTAAL approach offers less power consumption in the full adder and multiplier circuits than the other design. The DPTAAL approach offers a
88 more reasonable trade-off between power and delay in the full adder circuit. The DRDAAL approach exhibits the lowest delay in the full adder circuit, having a power dissipation penalty greater than the speed improvement. Hence, these three approaches confirm the feasibility of asynchronous adiabatic circuits in low power computing applications and have shown great prospect for the development of power aware systems. 5.6 SUMMARY In this chapter, the proposed design of CPTAAL full adder and multiplier circuits have been discussed. A unique approach, namely Complementary Pass-transistor with Asynchronous Adiabatic Logic (CPTAAL) has been followed in the full adder design. Complementary Passtransistor Logic (CPL) is suitable for complex arithmetic circuits where no compromise on power dissipation is allowed. This technique is combined with Asynchronous Adiabatic Logic (AAL) to obtain the energy saving benefits with improved circuit performance in full adder design. For the various frequency ranges, the average power consumed, delay of the circuit, and Power-Delay Product (PDP) of the proposed CPTAAL full adder is compared with the DRDAAL, DPTAAL, conventional CMOS full adders and the synchronous adiabatic full adder designs namely, Positive Feedback Adiabatic Logic (PFAL) adder, and Transmission Gate based Adiabatic Logic (TGAL) adder. The proposed CPTAAL, DPTAAL and DRDAAL full adders are achieved significant power savings for the various frequency ranges, as compared with existing designs. As compared with the DRDAAL and DPTAAL full adder design, the CPTAAL full adder design is achieved significant power savings up to 93%. This power efficient full adder cell is used in the multiplier design. The performance of this design is analyzed with 4 bit and 8 bit multipliers for
89 operating frequencies as low as 1 MHz and as high as 300 MHz. The power results of the proposed multiplier design are reported. The CPTAAL multiplier circuits have been implemented and studied using 0.18-μm TSMC technology file with 1.8V supply voltage and have shown great prospect for the development of power aware systems. This approach confirms the feasibility of asynchronous adiabatic multiplier in low power computing applications.