Integrated S12 MCU-Based Relay Driver with Diagnostic Bus

Integrated S12 MCU-Based Relay Driver with Diagnostic Bus FTF-AUT-F0182 Vincent M. McNeil, Ph.D. Product Line Manger, ASG A P R. 2 0 1 4 TM External Use

Objectives Educate session participants about the features and capabilities of the MM912_634 relay motor driver Explain a few of the target applications for the product Inform participants about the tools available to start quickly evaluating or developing applications with the product External Use 1

Agenda Introduction Overview of Motor Drive Applications in Body Electronics: Overview of the MM912_634 Family of Relay-motor Driver Products Key Digital Functions and Features Key Analog Functions and Features Tools and Product Enablement Summary External Use 2

What is Intelligent Distributed Control (IDC)? Example: Distributed Door > 34 nodes per car Networked motor driver system solution for body electronics optimized per application Designed for LIN/CAN distributed systems Well-suited for distributed motor control applications Distributed systems architecture can address both low end and high end requirements, due to its plug and play nature LIN/CAN Distributed Systems Standard interface (LIN) allows a wide selection of products without changing door concepts, and keeping a simple wire harness Optimized products with an integrated intelligent unit (MCU) External Use 3

Intelligent Distributed Control Solution Architecture LIN or CAN Physical Layer External Use 4

H-bridge Driven DC Motors Relay-Driven DC Motors H-bridge Driven DC & Stepper Motors TM IDC Product Portfolio MM912_634 MM912x634 Window lift /Sun roof MM908E624 MM908E622 Mirror MM908E621 MM908E626 Light-leveling MM908E625 8-bit MCU 16-bit MCU External Use 5

Window Lift Application Background Typical Anti-Pinch Window Lifter ECU Module Mounting Point Function DC Motor Key Up/Down Function Basic Features Implementation Relay Driver Wakeup Input Additional Features Implementation Anti-Pinch Hall Sensor / Current Sensing Ramp Up/Down Safety Features Communication Motor Current Nominal Voltage MOSFET (PWM) Watchdog Supply Voltage Sensor LIN Transceiver Technical Data Typ. 2-5 A, 12-20 A pk 12V DC External Use 6

MM912_634 Application: Power Window (Window Lift) Anti-pinching Hall sensing pulses Δt Hall IC1 Hall IC2 Forward : Δt > 0 Hall IC1 Hall IC2 Reverse: Δt < 0 The system stores the window position in SRAM, and the value also is stored regularly to data flash memory for the back up after Ignition (IG) is turned-off ECU checks the battery voltage to compensate the pulse interval due to the voltage variation. ECU A/D battery Hall IC1 M Hall IC2 External Use 7

MM912_634 Application: Windshield Wiper (Mechanical Methods) Single motor type Dual motor type M ECU Forward This is currently the major control type for the wipers. The two wiper arms are linked together, and controlled by a single motor. Forward/ Reverse Window washer M This system can control the motors with forward/ reverse direction. Rear wiper is connected to ECU in some car types LIN ECU LIN M M External Use 8

H-bridge Driven DC Motors Relay-Driven DC Motors H-bridge Driven DC & Stepper Motors TM IDC Product Portfolio MM912_634 MM912x634 Window lift /Sun roof MM908E624 MM908E622 Mirror MM908E621 MM908E626 Light-leveling MM908E625 8-bit MCU 16-bit MCU External Use 9

Application Performance TM MagniV Product Positioning 12V-Vreg MM912H634 S12 Core LIN-PHY 64K Flash MM912G634 12V-Vreg S12 Core LIN-PHY 48K Flash 2 HSD / 2 LSD 2K RAM 4/6 HV Inputs* 2k Data 5-18V Hall Sup. Current Sense* 48 LQFP /LQFP-EP* 2 HSD / 2 LSD 6K RAM 6 HV Inputs 4k Data 5-18V Hall Sup. Current Sense 48 LQFP / LQFP-EP S12VR MM912F634 12V-Vreg S12 Core 12V-Vreg S12 Core LIN-PHY 48-64K Flash* LIN-PHY 32K Flash 2 HSD* / 2 LSD 2K RAM 2 HSD / 2 LSD 2K RAM 4 HV Inputs 512 EEPROM 4/6 HV Inputs* S12VR 12V-Vreg LIN-PHY 5V Hall Supply Additional SCI 48 LQFP S12 Core 48-64K Flash* 5-18V Hall Sup. Current Sense* 48 LQFP / LQFP-EP* Digital Components 5V Analogue Components 1 HSD* / 2 LSD 2K RAM 4 HV Inputs 512 EEPROM 5V Hall Supply Additional SCI 32 LQFP MCU Core and Memories * Optional Feature Price High-Voltage Components EP = Exposed Pad External Use 10

Intelligent Distributed Control Solution Architecture LIN or CAN Physical Layer External Use 11

MM912_634 Integrated Relay Driver Solution for Motor Control 7x7 48-LQFP Differentiation Auto (18V,125 C) & Industrial (30V, 85 C) versions Smaller foot print & BOM with MCU + Analog functions in one package 20Mhz 16bit S12 MCU (up to 6kB SRAM & 64kB flash) 2 LS Drivers 50kHz PWM with 10mJ Eclamp Diagnostics and Protection features 18V external supply and 6 HV inputs Applications Auto window-lift and sunroof motors Machine tools, industrial robots, vending machines, building automation,... External Use 12

MM912_634: An Intelligent Relay Driver for DC Motors Single-package Intelligent DC Motor Driver solutions targeting space-constrained applications such as car window lift and sun roof External Use 13

MM912_634: Features and Application Example Internals High-performance 16-bit S12 CPU with 20 MHz max. bus freq. 48/64 kbyte FLASH, 2/4 kbyte RAM Alternate oscillator options: Internal RC oscillator, trimmable to +/-2% Full swing pierce oscillator for external resonator/crystal 2 autonomous window watchdog with dedicated oscillator Real time interrupt module Cyclic wakeup from low power mode (forced wakeup) Chip temperature sensor (readable via ADC channel) Application Specific Modules Cascaded low drop out voltage regulators (5V and 2.5V) with fault detection and low voltage reset (LVR) circuitry LIN 2.1 physical layer interface, fast mode capable Two protected low-side outputs to drive inductive loads Two protected high-side outputs Six high voltage inputs L[5:0] (shared digital and analog inputs, with wake-up capability) Battery voltage sense with low battery warning (IRQ), reverse battery protected Configurable cyclic sense & forced wake-up feature Current sense module with selectable gain Hall sensor supply implemented as switchable 18V voltage regulator External Use 14

MM912_634: Features and Application Example BDM Interface Pod Standard Modules Serial Background Debug Module (BDM) Three 5V digital/2.5v analog I/Os shared with timer, PWM, ADC and SCI with selectable pull-up resistor per terminal Serial Peripheral Interface (SPI AND SCI) 16-bit timer module with 4 channels (connected to PTB and Rx) 10-bit analog-to-digital converter (ADC) with twelve channel MUX (internal/external) 2 channel PWM module for direct control of the high-side (HS), low-side (LS) and PTB2 output(s) External Use 15

MM912_634 Modes of Operation I RUN = 20 ma typ at max. Temp. I STOP = 30µA typ optional cyclic sense +15µA I SLEEP = 15µA typ. optional cyclic sense +15µA External Use 16

MM912_634 Package and Pin-out LQFP48 Exposed Pad (EP) or Non-exposed Pad (NEP) 48-PIN LQFP-EP 48-PIN LQP-NEP External Use 17

S12 Core and Memory LIN -PHY Pierce Osc. Temp Sense 10-Bit ADC Features and Key Parameters G P I O SCI SPI BDM KWU Win Wdog TIM 16b 4ch PWM 2ch 8b E-Vreg 18V/ 80 ma RCosc. +/-1.3% 32/48/64kB Flash (ECC) 2 kb-4kb D-Flash PLL S12 CPU with 20MHz Bus 6 HV Inputs 2 kb-6kb RAM Vbat sense 2 HS Drivers 2 LS Drivers Current Sense Vreg 80mA Vsup sense 16-bit S12 CPU clocked at 40 MHz 16-20 MHz bus clock frequency Flash: 32 kb / 48 kb / 64 kb SRAM: 2 kb to 6 kb Data flash: 2 kb / 4 kb RC oscillator: +/-1.3% BDM and DBG modules Die-to-die interface allowing translation of all registers as one global memory map and interrupt management External Use 18

Serial Communication Interface (SCI) Features of SCI module Full-duplex, standard non-return-to-zero (NRZ) format Double-buffered transmitter and receiver with separate enables Programmable baud rates (13-bit modulo divider) Interrupt-driven or polled operation: Transmit data register empty and transmission complete Receive data register full Receive overrun, parity error, framing error, and noise error Idle receiver detect Active edge on receive pin Break detect supporting LIN Hardware parity generation and checking Programmable 8-bit or 9-bit character length Receiver wake-up by idle-line or address-mark Optional 13-bit break character generation / 11-bit break character detection Selectable transmitter output polarity External Use 19

LIN Physical Layer Interface SAE J2602-2 LIN 2.1 Compliant Features LIN physical layer 2.1 and SAE J2602-2 compliant Slew rate selection 20 kbit, 10 kbit and fast mode (100 kbit) Over-temperature shutdown - HTI Permanent pull up in normal mode 30 kω, 1 MΩ in low power Current limitation External Rx / Tx access via general purpose I/O - PTB[0..2] Rx available at TimCh3 Direct Rx / Tx access via EMC Compliant External Use 20

Alternative SCI / LIN Functionality Features Default Mode: SCI internally connected the LIN physical layer interface. PTB0 and PTB1 are digital I/Os External SCI mode: SCI connected to PTB0 and PTB1 (external SCI mode) External LIN mode: LIN physical layer interface connected to PTB0 and PTB1 Observe Mode: SCI internally connected the LIN physical layer interface and PTB0 and PTB1 are connected both as outputs (respectively Rx & Tx) External Use 21

PWM Module Features Two independent 8-bit PWM channels with programmable period and duty cycle Dedicated counter for each PWM channel Programmable PWM enable/disable for each channel Software selection of PWM duty pulse polarity for each channel Period and duty cycle are double buffered. Change takes effect when the end of the effective period is reached (PWM counter reaches zero) or when the channel is disabled Programmable center or left aligned outputs on individual channels Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies Programmable clock select logic External Use 22

Analog Digital Converter (ADC) Features 10-bit resolution Integrated selectable offset compensation 14+1 analog channels AD0 AD8 Isense Tsense Vsense & Vsense1 Bandgap + calibration channel Dedicated result register for each channel External reference pin with over-current protection Sequence or Continuous Conversion Mode with IRQ on complete, sequence configurable Key Parameters 13 µs conversion time Total error of ±5 LSB External Use 23

Power Supply and Regulators Features Based on the supply voltage applied to the VS1 pin, VDD (2.5 V) and VDDX (5.0 V) are provided to supply the S12S MCU I/O, the CPU core & the analog chip logic Also based on the Vs1 pin, to supply external Hall effect sensors, the HSUP pin will supply a switchable regulated supply To separate the high side outputs from the main power supply, the VS2 pin only powers the high side drivers Both supply pins have to be externally protected against reverse battery conditions Key Parameters 5V regulator (VDDX) 80 ma typ (with current limitation 80 ma min.) I/O voltage supply on the S12S MCU 2.5V regulator (VDD) 50 ma typ. (with current limitation 50 ma min.) Used to supply the CPU core and analog chip logic Cascaded from 5V VDDX output (80 ma total!) Clamped Hall sensor supply 10 ma typ. (with current limitation 50 ma) Clamped supply with 18V max. Implemented as typ. 17.5V vreg External Use 24

Power Supply and Temperature Control Features Power Up/Down Sequence LBI - Low Battery Interrupt, internally measured at VSENSE LVI - Low Voltage Interrupt, internally measured at VS1 LVR - Low Voltage Reset, internally measured at VDD LVRX - Low Voltage Reset, internally measured at VDDX Over Voltage Conditions HVI - High Voltage Interrupt, internally measured at VS2 In case of HVI, it will shut down both high side drivers VROVI - Voltage Regulator Over-voltage Interrupt internally measured at VDD and VDDX To protect the application from an unintentional activation of the drivers in case of a voltage regulator over-voltage failure, the low side drivers will automatically shut down in case of an over-voltage on one of the two regulators. Power Supply Over Temperature Conditions HTI - High Temperature Interrupt measured between VDD and VDDX Over Temperature Shutdown measured between VDD and VDDX External Use 25

Low-Side Drivers Features PWM capability Open-load detection: while enabled (with interrupt) Current limit protection (with maskable interrupt) Over -temperature: Shutdown and re-enable Active clamp Independent Vreg Over-voltage protection Key Parameters R DS(ON) = 2.5Ω @ 25⁰C, ILOAD = 150 ma PWM frequency = 10 khz Energy clamp: 10 mj @ Ta=125 C and VCLAMP = 40V Current limitation: 275 ma (typ.) Inductive load capability: 400 mh V SUP = 5.5V to 27 V External Use 26

LS Driver Protection: Energy Clamp @ 25 C 1 2 LS OFF LS ON VLS ( yellow) = 0V Irelay (blue) = 67mA 40V active clamp activated to allow current decrease 3 No more current VLS = VSup External Use 27

High-Side Drivers Features GND VDD High Side Driver VHS PWM capability Open-load detection: while enabled disabled (with interrupt) Current limit protection (with interrupt) PWM Independent over -temperature : Shutdown and re-enable Open Load Det. Over-temp Current Limit Over-Voltage shut. HSx Over-voltage protection (shutdown) HVI (software maskable) Separate high-side power supply pin VS2 Cyclic wake-up capability during low power modes Key Parameters R DS(ON) = 7.0Ω @ 25⁰C, ILOAD = 50 ma PWM Frequency = 50 khz Current Limitation: 110 ma (typ.) V SUP = 5.5V to 27 V External Use 28

Current Sense Module ISENSE The Current Sense Module is implemented to amplify the voltage drop across an external shunt resistor to measure the actual application current using the internal ADC. Typical application is the motor current in a window lift control module. Features 8 programmable gain settings Low input offset voltage (Internal offset compensation) External filter charge compensation Key Parameters Gain settings: 7, 9, 10, 12, 14, 18, 24, 36 Gain accuracy = ± 3% Resolution = 51 ma/ LSB Offset = ± 1.5% External Use 29

Temperature Sensor (TSENSE) The TSENSE feature allows accurate and dynamic monitoring of the analog die temperature. A constant temperature related gain of TSG can be routed to the internal ADC. Features Chip Temperature Sense element placed centered on the analog die Routed to the ADC Key Parameters +/-5 C accuracy full path -50 to 150 C measurement External Use 30

Supply Voltage Sense: VSENSE and VSENSE1 Two Vsense features measure directly at battery level (bypassing VSUP capacitor and external reverse battery diode) and at IC supply level. VSENSE Module: Direct measurement of the Battery Level Voltage VSENSE1 Module Measurement of the VS1 Level Voltage VSENSE Features Measures battery level voltage directly Reverse battery protected supply sense input External sense resistor RVSENSE required (10kW) LBI (low battery IRQ) warning internally measured Routed to the ADC Measurement of the Vsup pin level voltage LVI (low voltage IRQ) warning internally measured on this pin Routed to the ADC Key Parameters (VSENSE and VSENSE1) 10.8 divider to sample voltage via ADC (+/-5%) Max. 5% error full path Measurement of the Vsup pin level voltage VSENSE1 Features LVI (low voltage IRQ) warning internally measured on this pin Routed to the ADC External Use 31

MM912_634 EcoSystem: Evaluation Kit Fast evaluation of performance: EVBs for MM912_634 Easy to use debugging tool (register or module access) CodeWarrior compiler Programs S12 P&E 1. LEDs indicate HS and LS switching 2. Input power connectors 3. Prototype area 4. TBDML interface 5. LIN connector 6. Wake-up button 7. Reset button 8. BDM connector for external programming/debugging BDM interface 9. MM912_634 External Use 32

MM912_634 EcoSystem: Evaluation Kit Documentation Complete technical documentation to ease design Datasheets, EVB contents Official EMC reports from external laboratories External Use 33

MM912_634 EcoSystem: Tools and Software FreeMASTER Direct Register Access Control Page FreeMASTER Modules Access Control Page 1 Six tabs with registers 2 Register address 3 Register name 4 Bit field - by clicking the button the bit value is toggled 5 Numerical value of the register 6 Read and Write buttons 7 BDM communication error 8 Back button to return to the start page 9 Read all Registers button 10 Selection of number format for all read register values 11 Message box stating whether the correct register value was entered 1 Status Field : last reset and wake-up events, volathe monitor & watchdog enabler 2 LIN module 3 High side, low side switches and PWM control 4 ADC module 5 Low power modes control 6 BDM communication error 7 Backbutton to return to the start page External Use 34

Session Summary You have been introduced to Freescale s architecture for S12- based Body Electronic motor drivers. This architecture continues under the MagniV moniker Examined some of the target application and important product features to meet the application requirements Introduction to available enablement tools to assist customers in getting started quickly in using the product. External Use 35

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