WO 2008/ A3 PCT. (19) World Intellectual Property Organization International Bureau

Similar documents
Time allowed TWO hours plus 15 minutes reading time

GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, PANY [US/US]; 1500 City West Boulevard, Suite 800,

(10) International Publication Number (43) International Publication Date

(10) International Publication Number (43) International Publication Date

WO 2014/ Al P O P C T. 30 May 2014 ( )

2 December 2010 ( ) WO 2010/ Al

PCT WO 2008/ A2

WO 2008/ Al. (19) World Intellectual Property Organization International Bureau

(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)

(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)

(54) Title: APPARATUS INCLUDING STRAIN GAUGES FOR ESTIMATING DOWNHOLE STRING PARAMETERS

WO 2007/ Al PCT. (19) World Intellectual Property Organization International Bureau

1 September 2011 ( ) 2U11/1U4712 A l

Published: with international search report (Art. 21(3))

WO 2008/ A2. π n. (19) World Intellectual Property Organization International Bureau

WO 2016/ Al. 25 February 2016 ( ) P O P C T. kind of regional protection available): ARIPO (BW, GH, [Continued on next page]

I International Bureau (10) International Publication Number (43) International Publication Date

(10) International Publication Number (43) International Publication Date P O P C T

(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)

FIG May 2010 ( ) WO 2010/ Al. (43) International Publication Date

* Bitstream Bitstream Renderer encoder decoder Decoder

PCT WO 2007/ A2

(19) World Intellectual Property Organization International Bureau

(43) International Publication Date (10) International Publication Number 22 November 2001 ( ) PCT w A1

(10) International Publication Number (43) International Publication Date

WO 2008/ Al PCT. (19) World Intellectual Property Organization International Bureau

WO 2015/ A3. 10 December 2015 ( ) P O P C T FIG. 1. [Continued on nextpage]

o o WO 2013/ Al 3 January 2013 ( ) P O P C T

WO 2017/ Al. 24 August 2017 ( ) P O P C T

upon receipt of that report (Rule 48.2(g)) Fig. I a

WO 2017/ Al. 12 October 2017 ( ) P O P C T

TEPZZ 879Z A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: G06F 3/0354 ( )

The European Frequencies Shortage and what we are doing about it RFF- 8.33

WO 2009/ Al PCT. (19) World Intellectual Property Organization International Bureau

(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)

Published: with international search report (Art. 21(3))

as to applicant's entitlement to apply for and be granted a

I International Bureau (10) International Publication Number (43) International Publication Date

27 October 2011 ( ) W O 2011/ A l

Open Research Online The Open University s repository of research publications and other research outputs

(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)

SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM,

TEPZZ Z7Z7 5A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: H01F 30/12 ( )

TEPZZ 8 5ZA_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION

TEPZZ A T EP A2 (19) (11) EP A2 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: H02K 11/04 ( )

TEPZZ 7 Z_ 4A T EP A2 (19) (11) EP A2 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: G06F 3/0488 ( ) G06F 3/0482 (2013.

TEPZZ 7545 A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2014/29

TEPZZ Z 98 _A_T EP A1 (19) (11) EP A1. (12) EUROPEAN PATENT APPLICATION published in accordance with Art.

TEPZZ 76 84_A_T EP A1 (19) (11) EP A1. (12) EUROPEAN PATENT APPLICATION published in accordance with Art.

WO 2013/ Al. Fig 4a. 2 1 February 2013 ( ) P O P C T

P C T P O. GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, 4409 Headen Way, Santa Clara, CA (US). KONA-

TEPZZ 48A T EP A2 (19) (11) EP A2 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: H02M 3/335 ( ) H02M 1/00 (2006.

EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2012/37

WO 2009/ Al PCT. (19) World Intellectual Property Organization International Bureau

PCT WO 2007/ Al

TEPZZ Z47794A_T EP A1 (19) (11) EP A1. (12) EUROPEAN PATENT APPLICATION published in accordance with Art.

TEPZZ 9_Z47 A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2015/35

Fig November 2009 ( ) WO 2009/ Al. (43) International Publication Date

21 October 2010 ( ) WO 2010/ Al


WO 2009/ Al PCT. (19) World Intellectual Property Organization International Bureau

(10) International Publication Number (43) International Publication Date P C T P O

EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2012/33

APSI WIFI, LLC. Company S Monroe Plaza Way Suite A Sandy, UT 84070

TEPZZ ZZ 86ZA_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION

TEPZZ 6Z7 A_T EP A1 (19) (11) EP A1. (12) EUROPEAN PATENT APPLICATION published in accordance with Art.

DWPI Start Date A Examined granted patents (1975 only) 6 February 1975

TEPZZ 67ZZ A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION

I International Bureau

(43) International Publication Date _... _.. 28 April 2011 ( ) WO 2011/ Al

EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2011/40

EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2010/51

PCT Status Report. Francis Gurry

TEPZZ A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: G01S 7/40 ( ) G01S 13/78 (2006.

TEPZZ 9746 A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: A41F 1/00 ( )

TEPZZ A T EP A2 (19) (11) EP A2 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: H04B 1/40 ( ) H04W 52/02 (2009.

(51) Int Cl.: G03B 37/04 ( ) G03B 21/00 ( ) E04H 3/22 ( ) G03B 21/60 ( ) H04N 9/31 ( )

Transient Voltage Suppressors (TVS) Data Sheet

600W SURFACE MOUNT TRANSIENT VOLTAGE SUPPRESSOR SMB(DO-214AA) PACKAGE. SMBJ Series WILLAS ELECTRONIC CORP.

TEPZZ 5496_6A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: H02J 3/38 ( ) H02M 7/493 (2007.

TEPZZ 87_76ZA_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION

TEPZZ _7 8Z9A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: G01S 5/06 ( ) G01S 5/02 (2010.

I International Bureau (10) International Publication Number (43) International Publication Date 30 October 2014 ( )

TEPZZ _ Z9 7A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: G01P 3/66 ( )

(51) Int Cl.: G07D 9/00 ( ) G07D 11/00 ( )

TEPZZ _79748A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: H04W 4/04 ( ) B60Q 1/00 (2006.

TEPZZ 45A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2017/01

SECTION A APPENDIX J - COST-OF-LIVING INDEXES: FROM TO LOCALITIES FROM TO LOCALITIES , 999

SMBJ5.0 THRU SMBJ440CA

*EP A2* EP A2 (19) (11) EP A2 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2002/33

EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2010/31

TEPZZ _ 59 _A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2017/09

Science, research and innovation performance of the EU 2018

(19) World Intellectual Property Organization International Bureau

TEPZZ A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: B66B 1/34 ( )

TEPZZ A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: B29B 15/12 ( ) B32B 5/26 (2006.

EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2010/50

TEPZZ A_T EP A1 (19) (11) EP A1. (12) EUROPEAN PATENT APPLICATION published in accordance with Art.

(51) Int Cl.: F16D 1/08 ( ) B21D 41/00 ( ) B62D 1/20 ( )

Office de la Propriete Canadian CA Al 2012/09/27 PI Intellectuelle Intellectual Property du Canada Office (21)

Transcription:

(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date (10) International Publication Number 17 July 2008 (17.07.2008) PCT WO 2008/086050 A3 (51) International Patent Classification: (81) Designated States (unless otherwise indicated, for every G05F 1/46 (2006.01) H05B 33/08 (2006.01) kind of national protection available): AE, AG, AL, AM, AO, AT,AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, (21) International Application Number: CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, PCT/US2008/050026 EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, (22) International Filing Date: 2 January 2008 (02.01.2008) IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, (25) Filing Language: English LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, (26) Publication Language: English PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, (30) Priority Data: SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, 11/619,675 4 January 2007 (04.01.2007) US ZA, ZM, ZW (71) Applicant (for all designated States except US): ALLE (84) Designated States (unless otherwise indicated, for every GRO MICROSYSTEMS, INC. [US/US]; 115 Northeast kind of regional protection available): ARIPO (BW, GH, Cutoff, Worcester, Massachusetts 01615-0036 (US). GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, (72) Inventors; and ZW), Eurasian (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), (75) Inventors/Applicants (for US only): SZCZESZYNSKI, European (AT,BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, Gregory [CA/US]; 9 Logan Road, Nashua, New Hamp FR, GB, GR, HR, HU, IE, IS, IT, LT,LU, LV,MC, MT, NL, shire 03063 (US). WEKHANDE, Shashank [IN/US]; 10 NO, PL, PT, RO, SE, SI, SK, TR), OAPI (BF, BJ, CF, CG, Barrington Avenue, #102, Nashua, New Hampshire 03062 CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG). (US). MANGTANI, Vijay [US/US]; 7 Terramar Lane, Declarations under Rule 4.17: Nashua, New Hampshire 03062 (US). as to applicant's entitlement to applyfor and be granted a (74) Agents: ROBINSON, Kermit et al.; Daly, Crowley, Mof- patent (Rule 4.17(U)) ford & Durkee, LLP, Suite 30IA, 354A Turnpike Street, as to the applicant's entitlement to claim the priority of the Canton, Massachusetts 02021 (US). earlier application (Rule 4.17(Ui)) [Continued on next page] (54) Title: ELECTRONIC CIRCUIT FOR DRIVING A DIODE LOAD (57) Abstract: An electronic circuit includes circuit portions for identifying a largest voltage drop through one of a plurality of series connected diode strings and for controlling a boost switching regulator according to the largest voltage drop. The electronic circuit can sense an open circuit series connected diode string, which would otherwise have the largest voltage drop, and can disconnect that open circuit series connected diode string from control of the boost switching regulator. Another electronic circuit includes a current limiting circuit coupled to or within a boost switching regulator and configured to operate with a diode load. Another electronic circuit includes a pulse width modulation circuit configured to dim a series connected string of light emitting diodes.

Published: Date ofpublication of the amended claims: 18 December 2008 with international search report with amended claims (88) Date of publication of the international search report: 16 October 2008

AMENDED CLAIMS received by the International Bureau on 05 September 2008 (05.09.2008) 1. An electronic circuit, comprising: a current regulator having a current sense node, wherein the current regulator is configured to pass a predetermined current through the current regulator; an open-circuit detection circuit having an input node and an output node, wherein the input node of the open-circuit detection circuit is coupled to the current sense node of the current regulator, and wherein the open-circuit detection circuit is configured to provide an output signal at the output node of the open-circuit detection circuit indicative of a current flowing through the current regulator being below a predetermined current threshold; and a switch having an input node, an output node, and a control node, wherein the input node of the switch is coupled to the current sense node of the current regulator, wherein a selected one of the input node or the output node of the switch is coupled to the input node of open-circuit detection circuit, wherein the control node of the switch is coupled to the opencircuit detection circuit, and wherein the open-circuit detection circuit is configured to open the switch in response to the current flowing through the current regulator being below the predetermined current threshold. 2. The electronic circuit of Claim 1, further comprising: a minimum select circuit having an input node and an output node, wherein the input node of the minimum select circuit is coupled to the output node of the switch, wherein the minimum select circuit is configured to provide a signal at the output node of the minimum select circuit indicative of a signal at the output node of the switch; and 32

a switching circuit having a switching node and a control node, wherein the control node of the switching circuit is coupled to the output node of the minimum select circuit, wherein a duty cycle of the switching circuit is responsive to the signal at the output node of the minimum select circuit. 3. The electronic circuit of Claim 2, further comprising an over-voltage detection circuit having an input node and an output node, wherein the input node of the over-voltage detection circuit is coupled to the switching node of the switching circuit, wherein the output node of the over-voltage protection circuit is coupled to a second input node of the open-circuit detection circuit, wherein the over-voltage detection circuit is configured to provide an output signal at the output node of the over-voltage protection circuit indicative of a voltage at the input node of the over-voltage detection circuit being above a predetermined voltage threshold, wherein the output signal at the output node of the open-circuit detection circuit is indicative of the current flowing through the current regulator being below the predetermined current threshold and also indicative of the voltage at the input node of the over-voltage detection circuit being above the predetermined voltage threshold. 4. The electronic circuit of Claim 1, further comprising an over-voltage detection circuit having an input node and an output node, wherein the output node of the over-voltage protection circuit is coupled to a second input node of the open-circuit detection circuit, wherein the over-voltage detection circuit is configured to provide an output signal at the output node of the over-voltage protection circuit indicative of a voltage at the input node of the over-voltage detection circuit being above a predetermined voltage threshold, wherein the 33

output signal at the output node of the open-circuit detection circuit is indicative of the current flowing through the current regulator being below the predetermined current threshold and also indicative of the voltage at the input node of the over-voltage detection circuit being above the predetermined voltage threshold. 5. The electronic circuit of Claim 1, further comprising a temperature detection circuit having an output node coupled to a second input node of the open-circuit detection circuit, wherein the temperature detection circuit is configured to provide an output signal at the output node of the temperature detection circuit indicative of a temperature of the electronic circuit being above a predetermined temperature threshold, and wherein the output signal at the output node of the open-circuit detection circuit is indicative of the current flowing through the current regulator being below the predetermined current threshold and also indicative of the temperature of the electronic circuit being above the predetermined temperature threshold. 6. The electronic circuit of Claim 1, wherein the open-circuit detection circuit comprises: an open detect comparator having an input node and an output node, wherein the input node of the open detect comparator is coupled to the input node of the open-circuit detection circuit; a first logic gate having an input node and an output node, wherein the input node of the first logic gate is coupled to the output node of the open detect comparator; and a latching circuit having an input node and an output node, wherein the input node of the latching circuit is coupled to the output node of the first logic gate, and wherein the output node of the latching circuit is coupled to the output node of the open-circuit detection circuit.

7. The electronic circuit of Claim 6, wherein the open-circuit detection circuit further comprises: a second logic gate having an input node and an output node, wherein the input node of the second logic gate is coupled to the output node of the open detect comparator; and a delay module having an input node and an output node, wherein the input node of the delay module is coupled to the output node of the second logic gate, and wherein the output node of the delay module is coupled to a second input node of the first logic gate. 8. An electronic circuit, comprising: a switch having an input node, an output node, and a control node; a current-passing circuit having first and second nodes, wherein the first node of the current-passing circuit is coupled to the input node of the switch and the second node of the current-passing circuit is coupled to the output node of the switch; a boost switching regulator having an input node and an output node, wherein the input node of the boost switching regulator is coupled to the output node of the switch, and wherein the output node of the boost switching regulator is configured to couple to a diode load; and a resistor having first and second nodes, wherein the first node of the resistor is coupled to the control node of the switch and wherein the second node of the resistor is coupled to the output node of the boost switching regulator. 9. The electronic circuit of Claim 8, wherein the current-passing circuit comprises a resistor. 35

10. The electronic circuit of Claim 8, wherein the current-passing circuit comprises a current source. 11. The electronic circuit of Claim 8, wherein the switch comprises a field effect transistor. 12. The electronic circuit of Claim 11, wherein the current-passing circuit corresponds to a leakage of the field effect transistor. 13. The electronic circuit of Claim 12, wherein the boost switching regulator comprises: an inductor having first and second nodes, wherein the first node of the inductor is coupled to the input node of the boost switching regulator and is coupled to the output node of the switch; a diode having an anode and a cathode, wherein the anode is coupled to the second node of the inductor; a capacitor coupled to the cathode; and a switching circuit having an input node coupled to the second node of the inductor. 14. The electronic circuit of Claim 8, wherein the boost switching regulator comprises: an inductor having first and second nodes, wherein the first node of the inductor is coupled to the input node of the boost switching regulator and is coupled to the output node of the switch; 36

a diode having an anode and a cathode, wherein the anode is coupled to the second node of the inductor; a capacitor coupled to the cathode; and a switching circuit having an input node coupled to the second node of the inductor. 15. An electronic circuit for dimming a light emitting diode having an anode and a cathode, the electronic circuit comprising: a current regulator having a current node and a control node, wherein the current node of the current regulator is configured to couple to the light emitting diode; a boost switching regulator having an input node, an output node, and a control node, wherein the output node of the boost switching regulator is configured to couple to a selected one of the anode of the light emitting diode or to the current regulator, and wherein the boost switching regulator is enabled to switch or is disabled from switching in response to an input signal at the control node of the boost switching regulator; and a pulse width modulation circuit having an output node and a control node, wherein the output node of the pulse width modulation circuit is coupled to the control node of the current regulator, wherein the pulse width modulation circuit is configured to generate an AC output signal at the output node of the pulse width modulation circuit, which enables and disables the current regulator at a predetermined frequency and at a selected duty cycle in response to a respective selected input signal at the input node of the pulse width modulation circuit, wherein the duty cycle is selected in accordance with a selected brightness of the light emitting diode, and wherein, substantially simultaneously with the current regulator being disabled, the input 37

signal at the control node of the switching regulator is indicative of the boost switching regulator being disabled. 16. The electronic circuit of Claim 15, wherein an output voltage at the output node of the boost switching regulator is substantially the same when the boost switching regulator is disabled from switching as when the boost switching regulator is enabled to switch. 17. The electronic circuit of Claim 15, wherein the output node of the pulse width modulation circuit is coupled to the control node of the current regulator via a single-wire or multi-wire serial interface. 18. The electronic circuit of Claim 15, further comprising: a switch having an input node, an output node, and a control node, wherein the output node of the switch is coupled to the control node of the boost switching regulator, and wherein the control node of the switch is coupled to the pulse width modulation circuit, wherein the switch is closed when the current regulator is enabled and open when the current regulator is disabled; and a capacitor coupled to the input node of the switch, wherein the capacitor approximately holds a voltage when the switch is open corresponding to a voltage of the control node of the switching regulator when the switch is closed. 19. The electronic circuit of Claim 15, wherein the boost switching regulator is disabled in response to the current regulator being disabled. 38

20. The electronic circuit of Claim 19, wherein the predetermined frequency is within a range of about twenty to one thousand cycles per second. 21. An open circuit protection method for an LED driver circuit comprising a boost switching regulator, the method comprising: drawing a respective predetermined current through each of a plurality of LEDs and through a respective plurality of current regulators; detecting a smallest current passing through one of the plurality of current regulators; and detecting a respective current passing through each one of the plurality of current regulators to determine whether the respective current is less than a predetermined current threshold; wherein the detecting the smallest current does not take into account a current passing through at least one of the plurality of current regulators that is less than the predetermined current threshold. 22. The method of Claim 21, further comprising detecting whether an output voltage of the boost switching regulator is greater than a predetermined voltage threshold, wherein the disconnecting comprises disconnecting the LED from the LED driver circuit in response to a determination that the current passing through the current regulator is less than the predetermined current threshold and a determination that the output voltage of the boost switching regulator is greater than the predetermined voltage threshold. 39

23. The method of Claim 21, further comprising detecting whether a temperature of the LED driver circuit is greater than a predetermined temperature threshold, wherein the disconnecting comprises disconnecting the LED from the LED driver circuit in response to a determination that the current passing through the current regulator is less than the predetermined current threshold and a determination that the temperature of the LED driver circuit is greater than the predetermined temperature threshold. 24. The method of Claim 2 1, further comprising providing a delayed detection signal that is a delayed version of a signal indicative of whether the current passing through the current regulator is less than the predetermined current threshold, wherein the disconnecting comprises disconnecting the LED from the LED driver circuit in response to the delayed detection signal. 25. The method of Claim 2 1, further comprising: regulating an output voltage of the boost switching regulator in accordance with the detected smallest current. 40