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ECE 270 Learning Outcome 1-1 - Practice Exam / Solution LEARNING OUTCOME #1: an ability to analyze and design CMOS logic gates. Multiple Choice select the single most appropriate response for each question. Note that none of the above MAY be a VALID ANSWER. 1. The unsigned hexadecimal number (537)16 is equivalent to the following unsigned binary number: (A) (101 11 111)2 (B) (101 011 111)2 (C) (101 0011 0111)2 (D) all of the above 2. The expression (X+Y) (X+Z) = X + Y Z is an example of: (A) distributivity (B) commutitivity (C) associativity (D) consensus 3. A circuit consisting of a level of NOR gates followed by a level of AND gates is logically equivalent to: 2 (A) a multi-input OR gate 1 3 (B) a multi-input AND gate 2 1 3 (C) a multi-input NOR gate 2 1 (D) a multi-input NAND gate 3 4. The high impedance state of a tri-state buffer is created by: (A) turning off the PMOS transistor and turning on the NMOS transistor at the output of the buffer (B) turning off both the PMOS and the NMOS transistors at the output of the buffer (C) turning on both the PMOS and the NMOS transistors at the output of the buffer (D) turning on the PMOS transistor and turning off the NMOS transistor at the output of the buffer 5. The direction that current flows between the drain (D) and source (S) of N-channel and P-channel MOSFETS is as follows: (A) N-channel: D S; P-channel: S D (B) N-channel: S D; P-channel: D S (C) N-channel: D S; P-channel: D S (D) N-channel: S D; P-channel: S D

ECE 270 Learning Outcome 1-2 - Practice Exam / Solution 6. For most CMOS logic families, the maximum acceptable VIL is: (A) 10% of the power supply voltage (B) 30% of the power supply voltage (C) 50% of the power supply voltage (D) 70% of the power supply voltage (E) 90% of the power supply voltage 7. The nominal (minimum) case for the outputs of logic family A to be able to successfully drive the inputs of logic family B is: (A) fanouta B 1 and DCNMA B < 0 (B) fanouta B 0 and DCNMA B < 1 (C) fanouta B 1 and DCNMA B > 0 (D) fanouta B 0 and DCNMA B > 1 8. If a CMOS gate input voltage is 50% of its Vcc (power supply) voltage, then: (A) the logic gate will dissipate less power than it would if the input was 1% of its power supply voltage (B) the logic gate will dissipate less power than it would if the input was 99% of its power supply voltage (C) the logic gate will dissipate more power than it would if the input was either 1% or 99% of its power supply voltage (D) the logic gate will dissipate no power 9. A microcontroller designed to operate over a power supply range of 2 V to 4 V and a clock frequency range of 0 to 60 MHz dissipates a maximum of 320 mw. If the supply voltage used is 3 V and the clock frequency is 40 MHz, the power dissipation of the microcontroller will be reduced to: (A) 60 mw (B) 120 mw (C) 160 mw (D) 180 mw 10. A microcontroller designed to operate over a power supply range of 2 V to 4 V and a clock frequency range of 0 to 60 MHz dissipates a maximum of 320 mw. If the supply voltage used is 4 V and the clock frequency is 1 Hz, the power dissipation of the microcontroller will be reduced to: (A) 60 mw (B) 120 mw (C) 160 mw (D) 180 mw

ECE 270 Learning Outcome 1-3 - Practice Exam / Solution The following table applies to questions 11 through 14: Table 1. DC Characteristics of a Hypothetical Logic Family. VCC = 5 V VOH = 3.50 V VOL = 0.50 V VIH = 2.50 V VIL = 1.00 V VTH = (VOH VOL)/2 IOH = 5.0 ma IOL = 10 ma IIH = 500 µa IIL = 2.0 ma 11. The DC noise margin for this logic family is: (A) 0.50 V (B) 1.00 V (C) 1.50 V (D) 2.00 V 12. The practical fanout for this logic family is: (A) 1 (B) 2 (C) 5 (D) 10 13. When interfacing an LED that has a forward voltage of 1.5 V to this logic family in a current sourcing configuration, maximum brightness will be achieved (within the rated specifications) using a current limiting resistor of the value: (A) 200 Ω (B) 300 Ω (C) 400 Ω (D) 500 Ω 14. When interfacing an LED that has a forward voltage of 1.5 V to this logic family in a current sinking configuration, maximum brightness will be achieved (within the rated specifications) using a current limiting resistor of the value: (A) 200 Ω (B) 300 Ω (C) 400 Ω (D) 500 Ω

ECE 270 Learning Outcome 1-4 - Practice Exam / Solution The following circuit applies to questions 15 through 17: 5 V R 1 2 4 5 3 7403 6 7403 O.D. O.D. 1 2 7404 9 10 8 7403 O.D. 15. If the minimum value of pull-up resistor R used for this circuit is 1000 Ω, the IOLmax of each 7403 open-drain NAND gate is specified to be +5 ma, and the IIL required by the 7404 inverter is -0.5 ma, then the VIL provided to the 7404 input is guaranteed to be no higher than: (A) 0.1 V (B) 0.5 V (C) 4.5 V (D) 5.0 V 16. If the maximum value of pull-up resistor R used for this circuit is 10,000 Ω, the off-state leakage current of each of the 7403 open-drain NAND gate outputs is +10 μa, and the IIH required by the 7404 inverter is +20 μa, then the VIH provided to the 7404 input is guaranteed to be no lower than: (A) 0.1 V (B) 0.5 V (C) 4.5 V (D) 5.0 V 17. A valid reason for choosing the minimum value of R (provided above) is: (A) to minimize the fall time (tthl) of the circuit (B) to minimize the rise time (ttlh) of the circuit (C) to minimize the power dissipation of the circuit (D) to minimize the DC noise margin of the circuit

ECE 270 Learning Outcome 1-5 - Practice Exam / Solution The following circuit applies to questions 18 through 20: 5 V A B F A B GND 18. This circuit implements the following type of logic gate: (A) two-input OR (B) two-input AND (C) two-input NOR (D) two-input NAND 19. If A = 5V and B = 5V, the output F will be: (A) disconnected ( floating or high impedance) (B) 0 V (C) 2.5 V (D) 5.0 V 20. If the on resistance of both the P-channel and N-channel MOSFETs is 50 Ω, the amount of power this circuit will dissipate when input A = 5V and input B = GND is: (A) 25 mw (B) 50 mw (C) 250 mw (D) 500 mw

ECE 270 Learning Outcome 1-6 - Practice Exam / Solution The following circuit applies to questions 21 through 23: 5 V A B QP on resistance = 200 Ω F A B QN on resistance = 100 Ω GND 21. This circuit implements the following type of logic gate: (A) two-input OR (B) two-input AND (C) two-input NOR (D) two-input NAND 22. If the on resistance of the MOSFET labeled QP is 200 Ω and the on resistance of the MOSFET labeled QN is 100 Ω, then if 10 ma of current is sourced in the high state, VOH will be: (A) 1 V (B) 2 V (C) 3 V (D) 4 V 23. If the on resistance of the MOSFET labeled QP is 200 Ω and the on resistance of the MOSFET labeled QN is 100 Ω, then if 10 ma of current is sunk in the low state, VOL will be: (A) 1 V (B) 2 V (C) 3 V (D) 4 V

ECE 270 Learning Outcome 1-7 - Practice Exam / Solution The following figure applies to questions 24 through 25 (assume each horizontal division is 1 nanosecond): X Y X Y 1 ns 24. Based on the definition provided in the course text, the fall time (tthl) for the inverter is approximately: (A) 1.0 ns (B) 1.5 ns (C) 2.0 ns (D) 3.0 ns 25. The rise propagation delay (tplh) for the inverter is approximately: (A) 1.0 ns (B) 1.5 ns (C) 2.0 ns (D) 3.0 ns

ECE 270 Learning Outcome 1-8 - Practice Exam / Solution 26. A floating (unconnected) gate input will most likely cause the gate s output to: (A) always be high (B) always be low (C) be one-half (50%) of the supply voltage (D) be unpredictable 27. A CMOS circuit only consumes a significant amount of power: (A) when warming up (B) when cooling off (C) during output transitions (D) during input transitions 28. The primary purpose of decoupling capacitors is to: (A) provide an instantaneous source of current during output transitions (B) increase the output current sourcing/sinking capability (C) prevent VOH from falling below VOHmin (D) prevent VOL from rising above VOLmax 29. When a gate s rated IOL specification is exceeded, the following is likely to happen: (A) the VOH of the gate will increase and the ttlh of the gate will decrease (B) the VOL of the gate will decrease and the tthl of the gate will increase (C) the VOH of the gate will decrease and the ttlh of the gate will increase (D) the VOL of the gate will increase and the tthl of the gate will increase 30. If a CMOS inverter drives a capacitive load of 100 pf and the on resistance of its P-channel MOSFET is 20 Ω, then the gate s output rise time (ttlh) is approximately: (A) 0.2 ns (B) 2 ns (C) 20 ns (D) 2000 ns Answer key: 1-C, 2-A, 3-C, 4-B, 5-A, 6-B, 7-C, 8-C, 9-B, 10-E, 11-A, 12-C, 13-C, 14-B, 15-B, 16-C, 17-B, 18-E, 19-B, 20-C, 21-B, 22-C, 23-A, 24-A, 25-D, 26-D, 27-C, 28-A, 29-D, 30-B

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