Ultralow Noise, LDO XFET Voltage References with Current Sink and Source ADR0/ADR/ADR3/ADR/ADR5 FEATURES Ultralow noise (0. Hz to 0 Hz) ADR0: μv p-p ADR:. μv p-p ADR3:. μv p-p ADR:.8 μv p-p ADR5:.5 μv p-p Superb temperature coefficient A grade: 0 ppm/ C B grade: 3 ppm/ C Low dropout operation: 500 mv Input range: (VOUT + 500 mv) to 8 V High output source and sink current +0 ma and 5 ma, respectively Wide temperature range: 0 C to +5 C APPLICATIONS Precision data acquisition systems High resolution data converters Battery-powered instrumentation Portable medical instruments Industrial process control systems Precision instruments Optical control circuits GENERAL DESCRIPTION The ADRx series is a family of XFET voltage references featuring ultralow noise, high accuracy, and low temperature drift performance. Using Analog Devices, Inc., patented temperature drift curvature correction and XFET (extra implanted junction FET) technology, voltage change vs. temperature nonlinearity in the ADRx is greatly minimized. The XFET references offer better noise performance than buried Zener references, and XFET references operate off low supply voltage headroom (0.5 V). This combination of features makes the ADRx family ideally suited for precision signal conversion applications in high-end data acquisition systems, optical networks, and medical applications. The ADRx family has the capability to source up to 0 ma of output current and sink up to 5 ma. It also comes with a trim terminal to adjust the output voltage over a 0.5% range without compromising performance. PIN CONFIGURATIONS TP V IN NC 3 GND ADR0/ ADR/ ADR3/ ADR/ ADR5 TOP VIEW (Not to Scale) TP NOTES. NC = NO CONNECT. TP = TEST PIN (DO NOT CONNECT) 8 7 6 5 NC V OUT TRIM Figure. 8-Lead SOIC_N (R-Suffix) TP V IN NC 3 GND ADR0/ ADR/ ADR3/ ADR/ ADR5 TOP VIEW (Not to Scale) 8 7 6 5 TP NC V OUT TRIM NOTES. NC = NO CONNECT. TP = TEST PIN (DO NOT CONNECT) Figure. 8-Lead MSOP (RM-Suffix) Offered in two electrical grades, the ADRx family is available in 8-lead MSOP and narrow SOIC packages. All versions are specified over the extended industrial temperature range of 0 C to +5 C. Table. Selection Guide Output Voltage Initial Accuracy Temperature Coefficient Model (V) (mv) (ppm/ C) ADR0A.08 ±3 0 ADR0B.08 ± 3 ADRA.500 ±3 0 ADRB.500 ± 3 ADR3A 3.000 ± 0 ADR3B 3.000 ±. 3 ADRA.096 ±5 0 ADRB.096 ±.6 3 ADR5A 5.000 ±6 0 ADR5B 5.000 ± 3 058-00 058-00 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, MA 006-906, U.S.A. Tel: 78.39.700 www.analog.com Fax: 78.6.33 005 00 Analog Devices, Inc. All rights reserved.
TABLE OF CONTENTS Features... Applications... Pin Configurations... General Description... Revision History... Specifications... 3 ADR0 Electrical Characteristics... 3 ADR Electrical Characteristics... ADR3 Electrical Characteristics... 5 ADR Electrical Characteristics... 6 ADR5 Electrical Characteristics... 7 Absolute Maximum Ratings... 8 Thermal Resistance... 8 ESD Caution... 8 Typical Performance Characteristics... 9 Theory of Operation... Power Dissipation Considerations... Basic Voltage Reference Connections... Noise Performance... Turn-On Time... Applications Information... 5 Output Adjustment... 5 Bipolar Outputs... 5 Programmable Voltage Source... 5 Programmable Current Source... 6 High Voltage Floating Current Source... 6 Precision Output Regulator (Boosted Reference)... 6 Outline Dimensions... 7 Ordering Guide... 8 REVISION HISTORY /0 Rev. D to Rev. E Deleted Negative Reference Section... 5 Deleted Figure 37; Renumbered Sequentially... 5 3/0 Rev. C to Rev. D Changes to Figure 37... 5 Updated Outline Dimensions... 8 3/08 Rev. B to Rev. C Changes to Table 8... 8 Change to Figure... 0 Changes to Figure 36... 5 Changes to Figure 39... 6 Changes to Figure... 7 Updated Outline Dimensions... 8 9/06 Rev. 0 to Rev. A Updated Format...Universal Changes to Features... Changes to Pin Configurations... Changes to Specifications Section...3 Changes to Figure and Figure 5...9 Inserted Figure 6 and Figure 7...9 Changes to Figure 5... Changes to Power Dissipation Considerations Section... Changes to Figure 35 and Figure 36... 5 Changes to Figure 38 and Table 9... 6 Updated Outline Dimensions... 8 Changes to Ordering Guide... 9 0/05 Revision 0: Initial Version 8/07 Rev. A to Rev. B Change to Table, Ripple Rejection Ratio Specification... 3 Change to Table 3, Ripple Rejection Ratio Specification... Change to Table, Ripple Rejection Ratio Specification... 5 Change to Table 5, Ripple Rejection Ratio Specification... 6 Change to Table 6, Ripple Rejection Ratio Specification... 7 Rev. E Page of 0
SPECIFICATIONS ADR0 ELECTRICAL CHARACTERISTICS VIN = 3 V to 8 V, TA = 5 C, CIN = COUT = 0. μf, unless otherwise noted. ADR0/ADR/ADR3/ADR/ADR5 Table. Parameter Symbol Conditions Min Typ Max Unit OUTPUT VOLTAGE VO A Grade.05.08.05 V B Grade.07.08.09 V INITIAL ACCURACY VOERR A Grade 3 mv 0.5 % B Grade mv 0.05 % TEMPERATURE DRIFT TCVO A Grade 0 C < TA < +5 C 0 ppm/ C B Grade 0 C < TA < +5 C 3 ppm/ C LINE REGULATION ΔVO/ΔVIN 0 C < TA < +5 C 0 +0 +0 ppm/v LOAD REGULATION ΔVO/ΔILOAD ILOAD = 0 ma to 0 ma, VIN = 3.5 V, 0 C < TA < +5 C 50 +50 ppm/ma ΔVO/ΔILOAD ILOAD = 0 ma to 5 ma, VIN = 3.5 V, 0 C < TA < +5 C 50 +50 ppm/ma QUIESCENT CURRENT IIN No load, 0 C < TA < +5 C 3 3.75 ma VOLTAGE NOISE en p-p 0. Hz to 0 Hz μv p-p VOLTAGE NOISE DENSITY en khz 5 nv/ Hz TURN-ON SETTLING TIME tr 0 μs LONG-TERM STABILITY VO 000 hours 50 ppm OUTPUT VOLTAGE HYSTERESIS VO_HYS 70 ppm RIPPLE REJECTION RATIO RRR fin = khz 80 db SHORT CIRCUIT TO GND ISC 7 ma SUPPLY VOLTAGE OPERATING RANGE VIN 3 8 V SUPPLY VOLTAGE HEADROOM VIN VO 500 mv The long-term stability specification is noncumulative. The drift in the subsequent 000-hour period is significantly lower than in the first 000-hour period. Rev. E Page 3 of 0
ADR ELECTRICAL CHARACTERISTICS VIN = 3 V to 8 V, TA = 5 C, CIN = COUT = 0. μf, unless otherwise noted. Table 3. Parameter Symbol Conditions Min Typ Max Unit OUTPUT VOLTAGE VO A Grade.97.500.503 V B Grade.99.500.50 V INITIAL ACCURACY VOERR A Grade 3 mv 0. % B Grade mv 0.0 % TEMPERATURE DRIFT TCVO A Grade 0 C < TA < +5 C 0 ppm/ C B Grade 0 C < TA < +5 C 3 ppm/ C LINE REGULATION ΔVO/ΔVIN 0 C < TA < +5 C 0 0 ppm/v LOAD REGULATION ΔVO/ΔILOAD ILOAD = 0 ma to 0 ma, VIN = V, 0 C < TA < +5 C 50 +50 ppm/ma ΔVO/ΔILOAD ILOAD = 0 ma to 5 ma, VIN = V, 0 C < TA < +5 C 50 +50 ppm/ma QUIESCENT CURRENT IIN No load, 0 C < TA < +5 C 3 3.75 ma VOLTAGE NOISE en p-p 0. Hz to 0 Hz. μv p-p VOLTAGE NOISE DENSITY en khz 8 nv/ Hz TURN-ON SETTLING TIME tr 0 μs LONG-TERM STABILITY VO 000 hours 50 ppm OUTPUT VOLTAGE HYSTERESIS VO_HYS 70 ppm RIPPLE REJECTION RATIO RRR fin = khz 80 db SHORT CIRCUIT TO GND ISC 7 ma SUPPLY VOLTAGE OPERATING RANGE VIN 3 8 V SUPPLY VOLTAGE HEADROOM VIN VO 500 mv The long-term stability specification is noncumulative. The drift in subsequent 000-hour period is significantly lower than in the first 000-hour period. Rev. E Page of 0
ADR3 ELECTRICAL CHARACTERISTICS VIN = 3.5 V to 8 V, TA = 5 C, CIN = COUT = 0. μf, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit OUTPUT VOLTAGE VO A Grade.996 3.000 3.00 V B Grade.9988 3.000 3.00 V INITIAL ACCURACY VOERR A Grade mv 0.3 % B Grade. mv 0.0 % TEMPERATURE DRIFT TCVO A Grade 0 C < TA < +5 C 0 ppm/ C B Grade 0 C < TA < +5 C 3 ppm/ C LINE REGULATION ΔVO/ΔVIN 0 C < TA < +5 C 0 0 ppm/v LOAD REGULATION ΔVO/ΔILOAD ILOAD = 0 ma to 0 ma, VIN = 5 V, 0 C < TA < +5 C 50 +50 ppm/ma ΔVO/ΔILOAD ILOAD = 0 ma to 5 ma, VIN = 5 V, 0 C < TA < +5 C 50 +50 ppm/ma QUIESCENT CURRENT IIN No load, 0 C < TA < +5 C 3 3.75 ma VOLTAGE NOISE en p-p 0. Hz to 0 Hz. μv p-p VOLTAGE NOISE DENSITY en khz 57.6 nv/ Hz TURN-ON SETTLING TIME tr 0 μs LONG-TERM STABILITY VO 000 hours 50 ppm OUTPUT VOLTAGE HYSTERESIS VO_HYS 70 ppm RIPPLE REJECTION RATIO RRR fin = khz 80 db SHORT CIRCUIT TO GND ISC 7 ma SUPPLY VOLTAGE OPERATING RANGE VIN 3.5 8 V SUPPLY VOLTAGE HEADROOM VIN VO 500 mv The long-term stability specification is noncumulative. The drift in the subsequent 000-hour period is significantly lower than in the first 000-hour period. Rev. E Page 5 of 0
ADR ELECTRICAL CHARACTERISTICS VIN =.6 V to 8 V, TA = 5 C, CIN = COUT = 0. μf, unless otherwise noted. Table 5. Parameter Symbol Conditions Min Typ Max Unit OUTPUT VOLTAGE VO A Grade.09.096.0 V B Grade.09.096.0976 V INITIAL ACCURACY VOERR A Grade 5 mv 0.3 % B Grade.6 mv 0.0 % TEMPERATURE DRIFT TCVO A Grade 0 C < TA < +5 C 0 ppm/ C B Grade 0 C < TA < +5 C 3 ppm/ C LINE REGULATION ΔVO/ΔVIN 0 C < TA < +5 C 0 0 ppm/v LOAD REGULATION ΔVO/ΔILOAD ILOAD = 0 ma to 0 ma, VIN = 5.5 V, 0 C < TA < +5 C 50 +50 ppm/ma ΔVO/ΔILOAD ILOAD = 0 ma to 5 ma, VIN = 5.5 V, 0 C < TA < +5 C 50 +50 ppm/ma QUIESCENT CURRENT IIN No load, 0 C < TA < +5 C 3 3.75 ma VOLTAGE NOISE en p-p 0. Hz to 0 Hz.8 μv p-p VOLTAGE NOISE DENSITY en khz 78.6 nv/ Hz TURN-ON SETTLING TIME tr 0 μs LONG-TERM STABILITY VO 000 hours 50 ppm OUTPUT VOLTAGE HYSTERESIS VO_HYS 70 ppm RIPPLE REJECTION RATIO RRR fin = khz 80 db SHORT CIRCUIT TO GND ISC 7 ma SUPPLY VOLTAGE OPERATING RANGE VIN.6 8 V SUPPLY VOLTAGE HEADROOM VIN VO 500 mv The long-term stability specification is noncumulative. The drift in the subsequent 000-hour period is significantly lower than in the first 000-hour period. Rev. E Page 6 of 0
ADR5 ELECTRICAL CHARACTERISTICS VIN = 5.5 V to 8 V, TA = 5 C, CIN = COUT = 0. μf, unless otherwise noted. ADR0/ADR/ADR3/ADR/ADR5 Table 6. Parameter Symbol Conditions Min Typ Max Unit OUTPUT VOLTAGE VO A Grade.99 5.000 5.006 V B Grade.998 5.000 5.00 V INITIAL ACCURACY VOERR A Grade 6 mv 0. % B Grade mv 0.0 % TEMPERATURE DRIFT TCVO A Grade 0 C < TA < +5 C 0 ppm/ C B Grade 0 C < TA < +5 C 3 ppm/ C LINE REGULATION ΔVO/ΔVIN 0 C < TA < +5 C 0 0 ppm/v LOAD REGULATION ΔVO/ΔILOAD ILOAD = 0 ma to 0 ma, VIN = 6.5 V, 0 C < TA < +5 C 50 +50 ppm/ma ΔVO/ΔILOAD ILOAD = 0 ma to 5 ma, VIN = 6.5 V, 0 C < TA < +5 C 50 +50 ppm/ma QUIESCENT CURRENT IIN No load, 0 C < TA < +5 C 3 3.75 ma VOLTAGE NOISE en p-p 0. Hz to 0 Hz.5 μv p-p VOLTAGE NOISE DENSITY en khz 90 nv/ Hz TURN-ON SETTLING TIME tr 0 μs LONG-TERM STABILITY VO 000 hours 50 ppm OUTPUT VOLTAGE HYSTERESIS VO_HYS 70 ppm RIPPLE REJECTION RATIO RRR fin = khz 80 db SHORT CIRCUIT TO GND ISC 7 ma SUPPLY VOLTAGE OPERATING RANGE VIN 5.5 8 V SUPPLY VOLTAGE HEADROOM VIN VO 500 mv The long-term stability specification is noncumulative. The drift in the subsequent 000-hour period is significantly lower than in the first 000-hour period. Rev. E Page 7 of 0
ABSOLUTE MAXIMUM RATINGS TA = 5 C, unless otherwise noted. Table 7. Parameter Rating Supply Voltage 0 V Output Short-Circuit Duration to GND Indefinite Storage Temperature Range 65 C to +5 C Operating Temperature Range 0 C to +5 C Junction Temperature Range 65 C to +50 C Lead Temperature, Soldering (60 sec) 300 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 8. Thermal Resistance Package Type θja θjc Unit 8-Lead SOIC (R-Suffix) 30 3 C/W 8-Lead MSOP (RM-Suffix) 3.5 3.9 C/W ESD CAUTION Rev. E Page 8 of 0
TYPICAL PERFORMANCE CHARACTERISTICS VIN = 7 V, TA = 5 C, CIN = COUT = 0. μf, unless otherwise noted..05.0980 OUTPUT VOLTAGE (V).050.09.08.07.06.05 0 0 0 0 0 60 80 00 0 Figure 3. ADR0 Output Voltage vs. Temperature 058-0 OUTPUT VOLTAGE (V).0975.0970.0965.0960.0955.0950.095 DEVICE DEVICE 3 DEVICE.090 0 5 0 5 0 35 50 65 80 95 0 5 Figure 6. ADR Output Voltage vs. Temperature 058-005.500 5.006.505 5.00 OUTPUT VOLTAGE (V).500.5005.5000 OUTPUT VOLTAGE (V) 5.00 5.000.998.995.996.990 0 5 0 5 0 35 50 65 80 95 0 5 Figure. ADR Output Voltage vs. Temperature 058-003.99 0 0 0 0 0 60 80 00 0 Figure 7. ADR5 Output Voltage vs. Temperature 058-03 3.000.0 3.005 OUTPUT VOLTAGE (V) 3.000 3.0005 3.0000.9995.9990 DEVICE DEVICE DEVICE 3 SUPPLY CURRENT (ma) 3.5 3.0.5 0 C +5 C +5 C.9985.9980 0 5 0 5 0 35 50 65 80 95 0 5 Figure 5. ADR3 Output Voltage vs. Temperature 058-00.0 6 8 0 6 8 INPUT VOLTAGE (V) Figure 8. ADR Supply Current vs. Input Voltage 058-006 Rev. E Page 9 of 0
.0 0 SUPPLY CURRENT (ma) 3.5 3.0.5 LINE REGULATION (ppm/v) 8 6.0 0 5 0 5 0 35 50 65 80 95 0 5 058-007 0 0 5 0 5 0 35 50 65 80 95 0 5 058-00 Figure 9. ADR Supply Current vs. Temperature Figure. ADR Line Regulation vs. Temperature SUPPLY CURRENT (ma) 3.5 3. 3.3 3. 3. +5 C 3.0.9 +5 C.8.7 0 C.6.5 5.3 7.3 9.3.3 3.3 5.3 7.3 9.3 INPUT VOLTAGE (V) Figure 0. ADR5 Supply Current vs. Input Voltage 058-008 LOAD REGULATION (ppm/ma) 60 55 50 5 0 35 I LOAD = 0mA TO 0mA V IN = 6V V IN = 8V 30 0 5 0 5 0 35 50 65 80 95 0 5 Figure 3. ADR Load Regulation vs. Temperature 058-0 3.5 7 SUPPLY CURRENT (ma) 3.5 3.05.95.85.75 0 5 0 5 0 35 50 65 80 95 0 5 Figure. ADR5 Supply Current vs. Temperature 058-009 LINE REGULATION (ppm/v) 6 5 3 0 0 5 0 5 0 35 50 65 80 95 0 5 Figure. ADR5 Line Regulation vs. Temperature 058-0 Rev. E Page 0 of 0
LOAD REGULATION (ppm/ma) 50 0 30 0 0 0 0 0 30 V IN = 6V I LOAD = 0mA TO +0mA I LOAD = 0mA TO 5mA DIFFERENTIAL VOLTAGE (V).0 0.9 0.8 0.7 0.6 0.5 0. 0.3 0. +5 C +5 C 0 C 0 50 0 5 0 5 0 35 50 65 80 95 0 5 Figure 5. ADR5 Load Regulation vs. Temperature 058-03 0. 0 5 0 5 0 LOAD CURRENT (ma) Figure 8. ADR5 Minimum Input/Output Differential Voltage vs. Load Current 058-06 0.7 0.5 DIFFERENTIAL VOLTAGE (V) 0.6 0.5 0. 0.3 0. 0. +5 C LOAD CURRENT (ma) +5 C 0 C 0 0 5 0 5 0 Figure 6. ADR Minimum Input/Output Differential Voltage vs. Load Current 058-0 MINIMUM HEADROOM (V) 0. 0.3 0. 0. NO LOAD 0 0 5 0 5 0 35 50 65 80 95 0 5 Figure 9. ADR5 Minimum Headroom vs. Temperature 058-07 0.5 NO LOAD C IN = C OUT = 0.µF 0. MINIMUM HEADROOM (V) 0.3 0. 0. V IN = 5V/DIV V OUT = V/DIV 0 0 5 0 5 0 35 50 65 80 95 0 5 Figure 7. ADR Minimum Headroom vs. Temperature 058-05 TIME = 0µs/DIV Figure 0. ADR Turn-On Response 058-08 Rev. E Page of 0
C IN = C OUT = 0.µF C IN = 0.µF C OUT = 0µF LOAD OFF LOAD ON V IN = 5V/DIV 5mV/DIV V OUT = V/DIV TIME = 00µs/DIV 058-09 TIME = 00µs/DIV 058-03 Figure. ADR Turn-Off Response Figure. ADR Load Transient Response C IN = 0.µF C OUT = 0µF C IN = C OUT = 0.µF LOAD OFF LOAD ON V IN = 5V/DIV V OUT = V/DIV 5mV/DIV TIME = 00µs/DIV 058-00 TIME = 00µs/DIV 058-0 Figure. ADR Turn-On Response Figure 5. ADR Load Transient Response C IN = 0.µF C OUT = 0µF V/DIV V µv/div CH p-p.8µv mv/div TIME = 00µs/DIV 058-0 TIME = s/div 058-0 Figure 3. ADR Line Transient Response Figure 6. ADR 0. Hz to 0.0 Hz Voltage Noise Rev. E Page of 0
6 50µV/DIV CH p-p 9µV NUMBER OF PARTS 0 8 6 TIME = s/div Figure 7. ADR 0 Hz to 0 khz Voltage Noise 058-05 0 50 30 0 90 70 50 30 0 0 30 50 70 90 0 30 50 DEVIATION (ppm) Figure 30. ADR Typical Output Voltage Hysteresis 058-08 0 9 8 µv/div CH p-p.µv OUTPUT IMPEDANCE (Ω) 7 6 5 3 ADR5 ADR3 TIME = s/div 058-06 0 0 00 k FREQUENCY (Hz) 0k ADR 00k 058-09 Figure 8. ADR5 0. Hz to 0.0 Hz Voltage Noise Figure 3. Output Impedance vs. Frequency 0 0 50µV/DIV CH p-p 66µV RIPPLE REJECTION RATIO (db) 0 30 0 50 60 70 80 TIME = s/div 058-07 90 00 00 k 0k FREQUENCY (Hz) 00k 058-030 M Figure 9. ADR5 0 Hz to 0 khz Voltage Noise Figure 3. Ripple Rejection Ratio vs. Frequency Rev. E Page 3 of 0
THEORY OF OPERATION The ADRx series of references uses a new reference generation technique known as XFET (extra implanted junction FET). This technique yields a reference with low dropout, good thermal hysteresis, and exceptionally low noise. The core of the XFET reference consists of two junction field-effect transistors (JFETs), one of which has an extra channel implant to raise its pinch-off voltage. By running the two JFETs at the same drain current, the difference in pinch-off voltage can be amplified and used to form a highly stable voltage reference. The intrinsic reference voltage is around 0.5 V with a negative temperature coefficient of about 0 ppm/ C. This slope is essentially constant to the dielectric constant of silicon, and it can be closely compensated for by adding a correction term generated in the same fashion as the proportional-to-absolute temperature (PTAT) term used to compensate band gap references. The advantage of an XFET reference is its correction term, which is approximately 0 times lower and requires less correction than that of a band gap reference. Because most of the noise of a band gap reference comes from the temperature compensation circuitry, the XFET results in much lower noise. Figure 33 shows the basic topology of the ADRx series. The temperature correction term is provided by a current source with a value designed to be proportional to the absolute temperature. The general equation is VOUT = G (ΔVP R IPTAT) () where: G is the gain of the reciprocal of the divider ratio. ΔVP is the difference in pinch-off voltage between the two JFETs. IPTAT is the positive temperature coefficient correction current. ADRx devices are created by on-chip adjustment of R and R3 to achieve the different voltage options at the reference output. I PTAT I * I V P R ADRx *EXTRA CHANNEL IMPLANT V OUT = G ( V P R I PTAT ) Figure 33. Simplified Schematic Device R R3 V IN GND V OUT 058-033 POWER DISSIPATION CONSIDERATIONS The ADRx family of references is guaranteed to deliver load currents to 0 ma with an input voltage that ranges from 3 V to 8 V. When these devices are used in applications at higher currents, use the following equation to account for the temperature effects of increases in power dissipation: TJ = PD θja + TA () where: TJ and TA are the junction and ambient temperatures, respectively. PD is the device power dissipation. θja is the device package thermal resistance. BASIC VOLTAGE REFERENCE CONNECTIONS The ADRx family requires a 0. μf capacitor on the input and the output for stability. Although not required for operation, a 0 μf capacitor at the input can help with line voltage transient performance. V IN + 0µF 0.µF TP NC 3 GND ADR0/ ADR/ ADR3/ ADR/ ADR5 TOP VIEW (Not to Scale) 6 V OUT NOTES. NC = NO CONNECT. TP = TEST PIN (DO NOT CONNECT) Figure 3. Basic Voltage Reference Configuration 8 7 5 TP NC TRIM 0.µF NOISE PERFORMANCE The noise generated by the ADRx family of references is typically less than. μv p-p over the 0. Hz to 0.0 Hz band for ADR0, ADR, and ADR3. Figure 6 shows the 0. Hz to 0 Hz noise of the ADR, which is only. μv p-p. The noise measurement is made with a band-pass filter composed of a pole high-pass filter with a corner frequency at 0. Hz and a pole low-pass filter with a corner frequency at 0.0 Hz. TURN-ON TIME Upon application of power (cold start), the time required for the output voltage to reach its final value within a specified error band is defined as the turn-on settling time. Two components normally associated with this are the time for the active circuits to settle and the time for the thermal gradients on the chip to stabilize. Figure 0 and Figure show the turn-on and turn-off settling times for the ADR. 058-03 Rev. E Page of 0
APPLICATIONS INFORMATION OUTPUT ADJUSTMENT +V DD The ADRx family features a TRIM pin that allows the user to adjust the output voltage of the part over a limited range. This allows errors from the reference and overall system errors to be trimmed out by connecting a potentiometer between the output and the ground, with the wiper connected to the TRIM pin. Figure 35 shows the optimal trim configuration. R allows fine adjustment of the output and is not always required. RP should be sufficiently large so that the maximum output current from the ADRx is not exceeded. 0.µF V IN ADR0/ ADR/ ADR3/ ADR/ ADR5 GND V OUT 6 0.µF R 0kΩ +0V R 0kΩ +5V 0.µF V IN V OUT 6 V O = ±0.5% ADR0/ 0.µF ADR/ ADR3/ ADR/ ADR5 R TRIM 5 P 0kΩ GND R 00kΩ R kω Figure 35. ADRx Trim Function Using the trim function has a negligible effect on the temperature performance of the ADRx. However, all resistors need to be low temperature coefficient resistors, or errors may occur. BIPOLAR OUTPUTS By connecting the output of the ADRx to the inverting terminal of an operational amplifier, it is possible to obtain both positive and negative reference voltages. Care must be taken when choosing Resistors R and R (see Figure 36). These resistors must be matched as closely as possible to ensure minimal differences between the negative and positive outputs. In addition, care must be taken to ensure performance over temperature. Use low temperature coefficient resistors if the circuit is used over temperature; otherwise, differences exist between the two outputs. 058-035 R3 5kΩ 0V Figure 36. ADRx Bipolar Outputs PROGRAMMABLE VOLTAGE SOURCE To obtain different voltages than those offered by the ADRx, some extra components are needed. In Figure 37, two potentiometers are used to set the desired voltage and the buffering amplifier provides current drive. The potentiometer connected between VOUT and GND, with its wiper connected to the noninverting input of the operational amplifier, takes care of coarse trim. The second potentiometer, with its wiper connected to the trim terminal of the ADRx, is used for fine adjustment. Resolution depends on the end-to-end resistance value and the resolution of the selected potentiometer. +V DD V IN ADR0/ ADR/ ADR3/ ADR/ ADR5 GND V OUT 6 R 0kΩ R 0kΩ Figure 37. Programmable Voltage Source 5V 058-036 ADJ V REF For a completely programmable solution, replace the two potentiometers in Figure 37 with one Analog Devices dual digital potentiometer, offered with either an SPI or an I C interface. These interfaces set the position of the wiper on both potentiometers and allow the output voltage to be set. Table 9 lists compatible Analog Devices digital potentiometers. 058-038 Rev. E Page 5 of 0
Table 9. Digital Potentiometer Parts Part No. No. of Channels No. of Positions ITF R (kω) VDD (V) AD55.00 6.00 I C, 0, 50, 00 5.5 AD507.00 56.00 SPI 0, 50, 00 5.5 AD5.00 56.00 I C 0, 00, M 5.5 AD56.00 56.00 SPI 0, 50, 00 5 AD58.00 56.00 I C 0, 50, 00 5 AD55.00 56.00 I C, 0, 50, 00 5.5 AD53.00 56.00 SPI 0, 50, 00 5.5 AD535.00 0.00 SPI 5, 50 5.5 ADN850.00 0.00 SPI 5, 50 5.5 Can also use a negative supply. Adding a negative supply to the operational amplifier allows the user to produce a negative programmable reference by connecting the reference output to the inverting terminal of the operational amplifier. Choose feedback resistors to minimize errors over temperature. PROGRAMMABLE CURRENT SOURCE It is possible to build a programmable current source using a setup similar to the programmable voltage source, as shown in Figure 38. The constant voltage on the gate of the transistor sets the current through the load. Varying the voltage on the gate changes the current. This circuit does not require a dual digital potentiometer. V CC 0.µF V IN ADR0/ ADR/ ADR3/ ADR/ ADR5 V OUT 6 GND 0.µF AD559 Figure 38. Programmable Current Source I LOAD R SENSE 058-039 HIGH VOLTAGE FLOATING CURRENT SOURCE Use the circuit in Figure 39 to generate a floating current source with minimal self heating. This particular configuration can operate on high supply voltages, determined by the breakdown voltage of the N-channel JFET. V IN ADR0/ ADR/ ADR3/ ADR/ ADR5 V OUT 6 GND OP90 +V S SST VISHAY N390 V S Figure 39. Floating Current Source PRECISION OUTPUT REGULATOR (BOOSTED REFERENCE) V IN C IN 0.µF V IN ADR0/ ADR/ ADR3/ ADR/ ADR5 V OUT GND 6 C OUT 0.µF 5V V Figure 0. Boosted Output Reference 058-00 R L 00Ω N700 V O C L µf Higher current drive capability can be obtained without sacrificing accuracy by using the circuit in Figure 0. The operational amplifier regulates the MOSFET turn-on, forcing VO to equal the VREF. Current is then drawn from VIN, allowing increased current drive capability. The circuit allows a 50 ma load; if higher current drive is required, use a larger MOSFET. For fast transient response, add a buffer at VO to aid with capacitive loading. 058-0 Rev. E Page 6 of 0
OUTLINE DIMENSIONS 5.00 (0.968).80 (0.890).00 (0.57) 3.80 (0.97) 8 5 6.0 (0.) 5.80 (0.8) 0.5 (0.0098) 0.0 (0.000) COPLANARITY 0.0 SEATING PLANE.7 (0.0500) BSC.75 (0.0688).35 (0.053) 0.5 (0.00) 0.3 (0.0) 8 0 0.5 (0.0098) 0.7 (0.0067) 0.50 (0.096) 0.5 (0.0099).7 (0.0500) 0.0 (0.057) 5 COMPLIANT TO JEDEC STANDARDS MS-0-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 007-A 3.0 3.00.80 3.0 3.00.80 8 5 5.5.90.65 PIN IDENTIFIER 0.65 BSC 0.95 0.85 0.75 0.5 0.05 COPLANARITY 0.0 0.0 0.5.0 MAX 6 0 5 MAX 0.3 0.09 COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions show in millimeters 0.80 0.55 0.0 0-07-009-B Rev. E Page 7 of 0
ORDERING GUIDE Model Initial Output Accuracy Voltage (V) ±mv % Temperature Coefficient Package (ppm/ C) Package Description Branding Temperature Range ADR0ARZ.08 3 0.5 0 8-Lead SOIC_N 0 C to +5 C R-8 ADR0ARZ-REEL7.08 3 0.5 0 8-Lead SOIC_N 0 C to +5 C R-8 ADR0ARMZ.08 3 0.5 0 8-Lead MSOP R0 0 C to +5 C RM-8 ADR0ARMZ-REEL7.08 3 0.5 0 8-Lead MSOP R0 0 C to +5 C RM-8 ADR0BRZ.08 0.05 3 8-Lead SOIC_N 0 C to +5 C R-8 ADR0BRZ-REEL7.08 0.05 3 8-Lead SOIC_N 0 C to +5 C R-8 ADRARZ.500 3 0. 0 8-Lead SOIC_N 0 C to +5 C R-8 ADRARZ-REEL7.500 3 0. 0 8-Lead SOIC_N 0 C to +5 C R-8 ADRARMZ.500 3 0. 0 8-Lead MSOP R0 0 C to +5 C RM-8 ADRARMZ-REEL7.500 3 0. 0 8-Lead MSOP R0 0 C to +5 C RM-8 ADRBRZ.500 0.0 3 8-Lead SOIC_N 0 C to +5 C R-8 ADRBRZ-REEL7.500 0.0 3 8-Lead SOIC_N 0 C to +5 C R-8 ADR3ARZ 3.000 0.3 0 8-Lead SOIC_N 0 C to +5 C R-8 ADR3ARZ-REEL7 3.000 0.3 0 8-Lead SOIC_N 0 C to +5 C R-8 ADR3ARMZ 3.000 0.3 0 8-Lead MSOP R03 0 C to +5 C RM-8 ADR3ARMZ-REEL7 3.000 0.3 0 8-Lead MSOP R03 0 C to +5 C RM-8 ADR3BRZ 3.000. 0.0 3 8-Lead SOIC_N 0 C to +5 C R-8 ADR3BRZ-REEL7 3.000. 0.0 3 8-Lead SOIC_N 0 C to +5 C R-8 ADRARZ.096 5 0.3 0 8-Lead SOIC_N 0 C to +5 C R-8 ADRARZ-REEL7.096 5 0.3 0 8-Lead SOIC_N 0 C to +5 C R-8 ADRARMZ.096 5 0.3 0 8-Lead MSOP R0 0 C to +5 C RM-8 ADRARMZ-REEL7.096 5 0.3 0 8-Lead MSOP R0 0 C to +5 C RM-8 ADRBRZ.096.6 0.0 3 8-Lead SOIC_N 0 C to +5 C R-8 ADRBRZ-REEL7.096.6 0.0 3 8-Lead SOIC_N 0 C to +5 C R-8 ADR5ARZ 5.000 6 0. 0 8-Lead SOIC_N 0 C to +5 C R-8 ADR5ARZ-REEL7 5.000 6 0. 0 8-Lead SOIC_N 0 C to +5 C R-8 ADR5ARMZ 5.000 6 0. 0 8-Lead MSOP R05 0 C to +5 C RM-8 ADR5ARMZ-REEL7 5.000 6 0. 0 8-Lead MSOP R05 0 C to +5 C RM-8 ADR5BRZ 5.000 0.0 3 8-Lead SOIC_N 0 C to +5 C R-8 ADR5BRZ-REEL7 5.000 0.0 3 8-Lead SOIC_N 0 C to +5 C R-8 Z = RoHS Compliant Part. Package Option Rev. E Page 8 of 0
NOTES Rev. E Page 9 of 0
NOTES I C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). 005 00 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D058-0-/0(E) Rev. E Page 0 of 0