OPEN BASE STATION ARCHITECTURE INITIATIVE

OPEN BASE STATION ARCHITECTURE INITIATIVE Conformance Test Cases Appendix D Clock and Control Module (CCM) Version.00 Issue.00 (7)

FOREWORD OBSAI description and specification documents are developed within the Technical Working Group of the Open Base Station Architecture Initiative Special Interest Group (OBSAI SIG). Members of the OBSAI TWG serve voluntarily and without compensation. The description and specifications developed within OBSAI represent a consensus of the broad expertise on the subject within the OBSAI SIG. The OBSAI SIG uses the following terminology in the specifications: Ä Ä Ä "shall" expresses a provision that is binding "should" and "may" expresses non-mandatory provisions "will" expresses a declaration of purpose on the part of the OBSAI SIG. It may be necessary to use "will" in cases where the simple future tense is required Use of an OBSAI reference or specification document is wholly voluntary. The existence of an OBSAI Specification does not imply that there are no other ways to produce, test, measure, purchase, market, or provide other goods and services related to the scope of the OBSAI Specification. Furthermore, the viewpoint expressed at the time a specification is approved and issued is subject to change brought about through developments in the state of the art and comments received from users of the specification. Every OBSAI Specification is subjected to review in accordance with the Open Base Station Architecture Initiative Rules And Procedures. Implementation of all or part of an OBSAI Specification may require licenses under third party intellectual property rights, including without limitation, patent rights (such a third party may or may not be an OBSAI Member). The Promoters of the OBSAI Specification are not responsible and shall not be held responsible in any manner for identifying or failing to identify any or all such third party intellectual property rights. The information in this document is subject to change without notice and describes only the product defined in the introduction of this documentation. This document is intended for the use of OBSAI Member s customers only for the purposes of the agreement under which the document is submitted, and no part of it may be reproduced or transmitted in any form or means without the prior written permission of OBSAI Management Board. The document has been prepared for use by professional and properly trained personnel, and the customer assumes full responsibility when using it. OBSAI Management Board, Marketing Working Group and Technical Working Group welcome customer comments as part of the process of continuous development and improvement of the documentation. The information or statements given in this document concerning the suitability, capacity, or performance of the mentioned hardware or software products cannot be considered binding but shall be defined in the agreement made between OBSAI members. However, the OBSAI Management Board, Marketing Working Group or Technical Working Group have made all reasonable efforts to ensure that the instructions contained in the document are adequate and free of material errors and omissions. Issue.00 (7)

OBSAI liability for any errors in the document is limited to the documentary correction of errors. OBSAI WILL NOT BE RESPONSIBLE IN ANY EVENT FOR ERRORS IN THIS DOCUMENT OR FOR ANY DAMAGES, INCIDENTAL OR CONSEQUENTIAL (INCLUDING MONETARY LOSSES), that might arise from the use of this document or the information in it. This document and the product it describes are considered protected by copyright according to the applicable laws. OBSAI logo is a registered trademark of Open Base Station Architecture Initiative Special Interest Group. Other product names mentioned in this document may be trademarks of their respective companies, and they are mentioned for identification purposes only. Copyright Open Base Station Architecture Initiative Special Interest Group. All rights reserved. Users are cautioned to check to determine that they have the latest edition of any OBSAI Specification. Interpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate to specific applications. When the need for interpretations is brought to the attention of OBSAI, the OBSAI TWG will initiate action to prepare appropriate responses. Since OBSAI Specifications represent a consensus of OBSAI Member s interests, it is important to ensure that any interpretation has also received the concurrence of a balance of interests. For this reason OBSAI and the members of its Technical Working Groups are not able to provide an instant response to interpretation requests except in those cases where the matter has previously received formal consideration. Comments on specifications and requests for interpretations should be addressed to: 4 Peter Kenington Chairman, OBSAI Technical Working Group Linear Communications Consultants Ltd. Email: pbk@linearcomms.com Issue.00 (7)

Contents Summary of Changes...7 Current Test Case Status...8 Scope...0 4 Clock and Control Module Test Cases... 4. Input Signal Verification and Recovery...4 4. Holdover Stability...5 4. SCLK Output Skew...6 4.4 SYNC Output Skew...7 4.5 SCLK/SYNC Output Skew...8 4.6 System Clock/Synchronization Port Power Down...9 4.7 Normal Operating Temperature Range...0 4.8 Test Specifications and Figures... 5 Glossary...5 5. Abbreviations...5 5. Definition of Terms...6 6 References...7 6. OBSAI...7 6. TIA/EIA...7 Issue.00 4 (7)

Figures Figure - OBSAI BTS System reference...0 Figure - Block Diagram of Timing flows in the Clock and Control Module... Figure - Timing Test Setup... Figure 4 - Timing Test Setup... Figure 5 System synchronization timing...4 Issue.00 5 (7)

List of Tables Table - Test case status...9 Table - Input Clock Signal Specifications... Table System Clock Electrical Parameters... Table 4 - System Synchronization Signal Electrical Parameters... Table 5 - Abbreviations...5 Issue.00 6 (7)

Summary of Changes Version Approved by Date 0.0 Draft 6-dec-004 0.0 Draft 08-jan-005 0.0 Draft 07-feb-005 0.04 Draft 6-feb-005.00 Approved by MB Issue.00 7 (7)

Current Test Case Status Table presents all CCM test cases and their current progress status (Changed, Waiting for comments, Work in process, Approved) 4 Test case Status Last change Input Signal Verification and Recovery Approved 7-feb-005 Input Signal Fault Detection Deleted 7-feb-005 Input Signal Requalification Deleted 7-feb-005 Jitter/Wander Filtering Steady State Deleted 7-feb-005 Jitter/Wander Filtering Switching Between Phase Aligned Clocks Deleted 7-feb-005 Jitter/Wander Filtering Switching Between Phase Misaligned Clocks Deleted 7-feb-005 Jitter/Wander Filtering - Cold Start Deleted 7-feb-005 Holdover Entry - Manual Deleted 7-feb-005 Holdover Recovery - Manual Approved 7-feb-005 Holdover Entry - Automatic Deleted 7-feb-005 Holdover Recovery - Automatic Deleted 7-feb-005 Holdover Mode - Stability Approved 7-feb-005 SCLK Output - Skew Approved 7-feb-005 SYNC Output - Skew Approved 7-feb-005 SCLK/SYNC Output - Skew Approved 7-feb-005 SCLK/SYNC Port - Power Down Approved 7-feb-005 Clock Output Port Short Circuit Tolerance Tip and Deleted 7-feb-005 Issue.00 8 (7)

Test case Status Last change Ring Clock Output Port Short Circuit Tolerance Tip or Ring to Ground Deleted 7-feb-005 Normal Operating Temperature Range Approved 7-feb-005 Input Source Selection Non- Revertive Mode Deleted 7-feb-005 Input Source Selection Revertive Mode Deleted 7-feb-005 Input Source Selection SSM Processing Single Source Deleted 7-feb-005 Input Source Selection SSM Processing Redundant Source Deleted 7-feb-005 Input Source Selection SSM Processing Redundant Source - Non-Revertive Switching Deleted 7-feb-005 Input Source Selection SSM Processing Redundant Source - Revertive Switching Deleted 7-feb-005 Table - Test case status Issue.00 9 (7)

Scope 4 5 6 This document specifies test methods and conformance requirements to the OBSAI CCM module. OBSAI module and interface conforms to common OBSAI specifications if it fulfills minimum acceptance criterion of all test cases presented in this document. RP RP Iub or Abis Transport Block BaseBand Block RF Block Power Proprietary Block RP4 RP 7 Control and Clock Block Control Traffic Clock Power 8 Figure - OBSAI BTS System reference 9 0 4 5 6 7 The purpose of this test plan is to verify proper functionality of the Clock and Control Module (CCM) timing functions only. These functions include the following high level capabilities:. The ability to recover timing from external signal sources. The ability to process this timing and generate a stable system clock reference. The ability to distribute the stable clock reference 4. The ability to exercise clock management functions. Issue.00 0 (7)

For the purposes of this test plan, Figure - Block Diagram of Timing flows in the Clock and Control Module will be used to illustrate high level functionality and the origin of signals. 4 5 6 7 8 9 0 GPM GPM GPS Receiver GPM GPM TM TM PPSCLK LVDS AUXCLK LVDS From Mate CCM REFCLK LVDS CCM (opt) CCM PLL Control SCLK/SYNC LVDS To Mate CCM SCLK/SYNC LVDS SCLK/SYNC LVDS BBM N BBM BBM TM TM RFM RFM SCLK/SYNC LVDS EM EM Figure - Block Diagram of Timing flows in the Clock and Control Module 4 5 6 7 8 9 0 4 5 The CCM timing tests are organized into four categories. ) Timing Recovery These tests deal with verifying that the CCM can recover timing from external timing signals. These timing signals include the reference clock (REFCLK), PPS clock (PPCLK) and auxiliary clock (AUXCLK) inputs. ) Timing Processing - The timing processing tests will evaluate how well the CCM is able to perform the following functions: a) Frequency regeneration - Lock on to the input reference and generate an accuracy frequency clock b) Holdover performance Timing stability in holdover mode ) Timing Distribution - The timing distribution tests will evaluate how well the CCM is able to generate output signals with the following characteristics: Issue.00 (7)

4 5 6 7 8 9 0 a) Skew including how well the output CCM clocks are phase aligned over variety of temperature an input conditions b) Output Level For both differential outputs and offset voltage c) Output rise and fall times Under loaded conditions d) Disabling unused output ports Including the ability to create a high impedance for unused outputs 4) Timing Environmental Performance- This tests that the CCM is able to start-up and operate over its entire working temperature range. a) Operating Temperature range The CCM shall be able to meet all functions and timing specifications over the entire operating temperate range. Issue.00 (7)

4 Clock and Control Module Test Cases 4 5 6 7 8 9 0 4 5 6 7 8 9 0 Issue.00 (7)

4. Input Signal Verification and Recovery Test Case ID: Test Case status: Relevant to: CCM-TF-00 Mandatory CCM Timing Recovery Source reference: OBSAI Clock and Control Module (CCM) Specification Test Purpose: Test Models: Method of Test: Test Conditions: Assumptions and Limitations: Procedure: Verify that the clock input function is capable of operating over the entire defined range. Input signal frequency/voltage range. Verify that the DUT accepts a valid input signal and recovers its timing. Insert test module into the test fixture and apply power, appropriate control signals, and input clock signals. -. Apply each input signal separately with specifications conforming to Table - Input Clock Signal Specifications to each clock input port of the DUT. a. The reference clock inputs shall be 8.000 khz with an accuracy of 0.06 PPM. b. The PPS clock Inputs shall be pulse-per-second with an accuracy of 0.06 PPM. c. The auxiliary clock inputs shall be 0.0 MHz with an accuracy of 0.06 PPM.. Configure the DUT to accept the appropriate input type.. Allow the DUT to acquire lock and stabilize. 4. Vary the input timing signal frequency over the range as specified Table - Input Clock Signal Specifications Verify that the DUT accepts the input timing signal via the management interface. 5. Measure the output SCLK per the parameters in Table System Clock Test setup: Figure - Timing Test Setup Minimum acceptance criteria: Ä Ä DUT shall accept input clock over the entire frequency range and track the input source. DUT shall derive timing from the input clock and use this to generate the 0.7 MHz SCLK over the entire frequency range. Parameters Value Limit Comments Frequency Duty Cycle PP Jitter See Table System Clock Electrical Parameters Issue.00 4 (7)

4. Holdover Stability Test Case ID: Test Case status: Relevant to: CCM-TF-050 Mandatory CCM Timing processing Source reference: OBSAI Clock and Control Module (CCM) Specification, System Reference Document Test Purpose: Test Models: Method of Test: Test Conditions: Assumptions and Limitations: Procedure: Verify that the timing engine of the CCM is capable of meeting the jitter/wander filtering requirements during entry into holdover mode. CCM holdover mode performance. Verify holdover mode of operation by verifying conformance to specifications at the output clock signal. Insert test module into the test fixture and apply power, appropriate control signals, and input clock signals. All SCLK and SYNC outputs shall be terminated with a differential 00 ohm resistive load. Need to first train and stabilize the CCM holdover oscillator before entering holdover mode.. Apply each input signal separately with specifications conforming to Table - Input Clock Signal Specifications to each clock input port of the DUT.. Provision the DUT to accept the appropriate input type.. Verify that the DUT accepts the input timing signal via the management interface. 4. Allow sufficient time for the DUT to acquire lock and stabilize. 5. Use the management interface to switch from the input source to holdover mode. 6. Vary the ambient temperature of the DUT over the specified operating range of -40 to 65 Å C. Let the temperature of the DUT soak at several fixed temperature values and take the following measurements. a. Verify that the DUT SCLK and SYN outputs comply with the specifications as listed in Table System Clock Electrical Parameters and Table 4 - System Synchronization Signal Electrical Parameters. Test setup: Figure - Timing Test Setup Minimum acceptance criteria: Ä Testing should be done over the normal operating range of -40 to +60 degrees C. Parameters Value Limit Comments Frequency drift in 4 hours 0.06 ppm max - This represents a maximum, absolute frequency drift from nominal. Issue.00 5 (7)

4 4. SCLK Output Skew Test Case ID: Test Case status: Relevant to: CCM-TF-00 Mandatory CCM Timing Distribution Source reference: OBSAI Clock and Control Module (CCM) Specification Test Purpose: Test Models: Method of Test: Test Conditions: Assumptions and Limitations: Procedure: Verify that the clock output function is capable of limiting the skew of the output SCLK outputs. CCM output driver performance. Verify output skew by measuring relative phase of SCLK outputs. Insert test module into the test fixture and apply power, appropriate control signals, and input clock signals. All SCLK and SYNC outputs shall be terminated with a differential 00 ohm resistive load. -. Apply an 8 khz reference clock with specifications conforming to Table - Input Clock Signal Specifications to the primary input port of the DUT.. Provision the DUT to accept the appropriate input type.. Verify that the DUT accepts the input timing signal via the management interface. 4. Allow sufficient time for the DUT to acquire lock and stabilize. 5. Select one of the SCLK outputs and use this as a timing reference. Measure the phase deviation of all other SCLK outputs against this reference. Test setup: Figure - Timing Test Setup Minimum acceptance criteria: Ä All SCLK outputs must meet this requirement. Parameters Value Limit Comments System Clock to Clock Skew 5 ns max - This represents the maximum skew between any two SCLK outputs. Issue.00 6 (7)

4.4 SYNC Output Skew Test Case ID: Test Case status: Relevant to: CCM-TF-00 Mandatory CCM Timing Distribution Source reference: OBSAI Clock and Control Module (CCM) Specification Test Purpose: Test Models: Method of Test: Test Conditions: Assumptions and Limitations: Procedure: Verify that the clock output function is capable of controlling the skew of the output SYNC outputs. CCM output driver performance. Verify output skew by measuring relative phase of the system synchronization signal output. Insert test module into the test fixture and apply power, appropriate control signals, and input clock signals. All SCLK and SYNC outputs shall be terminated with a differential 00 ohm resistive load. -. Apply an 8 khz reference clock with an accuracy of 0.06 ppm to the primary input port of the DUT. Test setup: Figure - Timing Test Setup Minimum acceptance criteria: Ä. Provision the DUT to accept the appropriate input type.. Verify that the DUT accepts the input timing signal via the management interface. 4. Allow sufficient time for the DUT to acquire lock and stabilize. 5. Select one of the System Synchronization l outputs and use this as a timing reference. Measure the phase deviation of all other System Synchronization outputs against this reference. All SYNC outputs must meet this requirement. Parameters Value Limit Comments SYNC Skew Ç 8 ns This represents a maximum skew between any two SYNC outputs. Issue.00 7 (7)

4.5 SCLK/SYNC Output Skew Test Case ID: Test Case status: Relevant to: CCM-TF-00 Mandatory CCM Timing Distribution Source reference: OBSAI Clock and Control Module (CCM) Specification Test Purpose: Test Models: Method of Test: Test Conditions: Assumptions and Limitations: Procedure: Verify that the DUT is capable of controlling the skew between the SCLK and Sync Burst outputs. CCM output driver performance. Verify output skew by measuring relative phase between the system clock and system synchronization signal output. Insert test module into the test fixture and apply power, appropriate control signals, and input clock signals. All SCLK and SYNC outputs shall be terminated with a differential 00 ohm resistive load. -. Apply an 8 khz reference clock with specifications conforming to Table - Input Clock Signal Specifications to the primary input port of the DUT.. Provision the DUT to accept the appropriate input type.. Verify that the DUT accepts the input timing signal via the management interface. 4. Allow sufficient time for the DUT to acquire lock and stabilize. 5. Measure the phase difference between each SCLK and SYNC pair per Figure 5 System synchronization timing. Test setup: Figure - Timing Test Setup Minimum acceptance criteria: Ä All SCLK and SYNC outputs must meet these criteria. Parameters Value Limit Comments Max Skew Ç 6.5 ns Maximum Skew between any SCLK and SYNC pair Issue.00 8 (7)

4.6 System Clock/Synchronization Port Power Down Test Case ID: Test Case status: Relevant to: CCM-TF-040 Mandatory CCM Timing Distribution Source reference: OBSAI Clock and Control Module (CCM) Specification Test Purpose: Test Models: Method of Test: Test Conditions: Verify that selected system clock and synchronization output ports are in high impedance state in a power down state CCM output driver Verify the impedance of the output system clock and synchronization ports. Do not terminate the SLCK and SYNC outputs. Assumptions - and Limitations: Procedure:. Using an ohm meter, verify the impedance of each differential output lead to ground.. Measurements should be made on each lead of the SCLK and SYNC output ports to ground. Test setup: Connect Ohm meter to DUT Minimum acceptance criteria: Ä The impedance of each differential output lead to ground should be greater than 00 kohm. Parameters Value Limit Comments All parameters that affect the test. Limits of the acceptance criteria. Per TIA/EIA644-A Issue.00 9 (7)

4.7 Normal Operating Temperature Range Test Case ID: Test Case status: Relevant to: Source reference: Test Purpose: Test Models: Method of Test: Test Conditions: Assumptions and Limitations: Procedure: CCM-TF-400 Mandatory Timing Environmental CCM OBSAI BTS System Reference Document Verify that the timing engine of the CCM is capable of meeting the normal operating requirements over the specified temperature range. CCM operation over temperature. Verify output signals with all possible input signals over the specified temperature range. Insert test module into the test fixture and apply power, appropriate control signals, and input clock signals. All SCLK and SYNC outputs shall be terminated with a differential 00 ohm resistive load. -. Apply each input signal separately with specifications conforming to Table - Input Clock Signal Specifications to each clock input port of the DUT.. Provision the DUT to accept the appropriate input type.. Vary the ambient temperature of the DUT over the specified operating range of -40 to 65 Å C. Let the temperature of the DUT soak at several fixed temperature values and take the following measurements. a. Vary the input timing signal frequency over the range as specified Table - Input Clock Signal Specifications. b. Verify that the DUT SCLK and SYN outputs comply with the specifications as listed in Table System Clock Electrical Parameters and Table 4 - System Synchronization Signal Electrical Parameters. c. Verify that the DUT can restart upon a power down/power-up cycle. Test setup: Figure - Timing Test Setup Minimum acceptance criteria: Ä The SCLK and SYNC outputs need to operate and start-up. Parameters Comments Comments Comments Frequency Duty Cycle PP Jitter See Table System Clock Electrical Parameters Issue.00 0 (7)

4.8 Test Specifications and Figures Table - Input Clock Signal Specifications Parameter Symbol Min Typical Max Unit Receiver Input Threshold V TH - - Ç 00 mv Input Current (Power On) I IN_ON - - Ç 0 ua Input Current (Power Off) I IN_OFF - - Ç 0 ua Input Voltage Range V IN 0 -.4 V Differential Input Impedance Z IN 80 00 0 É 4 5 Table System Clock Electrical Parameters Values Parameter Symbol Min Typical Max Unit Frequency F CLK -0.06 ppm 0.7 +0.06 ppm MHz Duty Cycle T DUTY_CYCLE 40 50 60 % PP Jitter T P-P JITTER -- 400 600 ps 6 Issue.00 (7)

Table 4 - System Synchronization Signal Electrical Parameters Values Parameter Symbol Min Typical Max Unit Transmitter Differential Output Voltage V OD 47-454 mv Transmitter Offset Voltage V os.5 -.75 V Input Current (Power Off) I IN_OFF - - Ç0 ua System Clock (SCLK) to System Synchronization Signal (SYUNC) Delay t QUT_SYNC -8 - +8 ns Issue.00 (7)

Adjustable Frequency Source DUT 4 5 6 Timing Signal T Waveform Generator * Analysis Equipment 7 8 9 Used for redundant input clock testing Management System Terminal Power 0 Figure - Timing Test Setup 4 5 6 Adjustable Frequency Source Timing Signal Waveform DUT 7 8 9 0 Management System Terminal Power Figure 4 - Timing Test Setup Issue.00 (7)

4 5 6 Figure 5 System synchronization timing Issue.00 4 (7)

5 Glossary 4 5. Abbreviations For the purposes of the present document, the following abbreviations apply: ABBREVIATION DESIGNATION AUXCLK Auxiliary Clock BBM Base Band Module BTS Base Transceiver Station CCM Clock and Control Module EM Extension Module GND Ground GPM General Purpose Module LVDS Low Voltage Differential Signaling OBSAI Open Base Station Architecture Initiative PPSCLK Pulse Per Second Clock REFCLK Reference Clock RFM Radio Frequency Module RP Reference Point RP Reference Point RP Reference Point SCLK System Clock SW Software SYNC Synchronization Signal TM Transport Module 5 Table 5 - Abbreviations Issue.00 5 (7)

4 5 6 7 8 9 0 4 5 6 7 8 9 0 5. Definition of Terms For the purposes of the present document, the following terms and definitions apply: Common Signals: Common Signals are common to all modules and shall be supported. Common Signals are assigned to fixed pin positions at the Data Connector(s) which are present at all modules. Module Type Specific Signals: Module Type Specific Signals are specific to a certain module type (TM, CCM, BBM, RFM, and PM) and shall be supported. Module Type specific Signals shall be assigned to fixed pin positions at the Data Connector(s). Module Type Unspecified Signals: Module Type Unspecified Signals are optional. Their functional and electrical characteristics are not specified. If present, Module Type Unspecified Signals shall be assigned to a range of pin positions at the Data Connector(s). The range of pin positions shall be fixed for a certain module type, but may differ between module types. Signal Group: A group of signals forming a functional entity e.g. a fabric port. High Impedance State: http://www.patentec.com/data/class/defs/6/56.html Issue.00 6 (7)

6 References 4 5 6 7 8 9 6. OBSAI [OBSAI RP] [OBSAI CCM] [OBSAI RP] [OBSAI TM] [OBSAI SRD] OBSAI Reference Point Specification OBSAI Clock and Control Module Specification OBSAI Reference Point Specification OBSAI Transport Module Specification OBSAI BTS System Reference Document 0 4 6. TIA/EIA [TIA/EIA-644A] ELECTRICAL CHARACTERISTICS OF LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) INTERFACE CIRCUITS Issue.00 7 (7)