Department of Electronics n Evolvable, Field-Programmable Full Custom nalogue Transistor rray (FPT)
Outline What`s Behind nalog? Evolution Substrate custom made configurable transistor array (FPT) Ways to Go Tackling Real-World Problems one analog circuit one fitness value? understanding evolved circuits finding new design principles achievement or information aim or desire
What s Behind nalog? CMOS Transistor Basics 1. Behavioral (model) 2. Symbolic view (schematic) 3. Data structure (SPICE netlist).subckt evocir 3 1 5 m0 5 1 3 5 modp l=1u w=12u m1 3 3 0 0 modn l=1u w=5u.ends
What s Behind nalog? CMOS Transistor Basics 4. Physical representation (layout) B S G D D G S B p+ n+ p-substrate SiO 2 SiO 2 n+ p+ n-channel p-channel W W p+ n-well L L 4. Physical representation (motifs)
Building a Programmable Transistor transistor configuration: length is programmed by selecting the according row width is varied by enabling combinations of parallel transistors (columns) selectable W/L ratio: (1/8... 15/0.6)
Parasitics of the FPT Cell Programmability comes at the cost of parasitic effects!
Characteristics of the FPT Bandwidth & Total Harmonic Distortion (measured using a sine-wave accross the chip, so it s effectively faster) Only routing resources are used!
Characteristics of the FPT Characteristics of the programmable transistors compared with a single transistor of corresponding size 900 PMOS output characteristics W = 1,2,4,8,15 um, L = 2 um, -Vgs = 4 V 800 700 600 -Id [u] 500 400 300 200 100 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -Vds [V]
Configuration Options of the FPT routing capabilities: interconnect outer cell nodes N,S,W,E transistor configuration: selectable W/L ratio: (1/8.. 15/0.6) connect terminals to N,S,W,E,Vdd,Gnd 16x16 transistor cells: PMOS & NMOS W N E 2/1 3/1 16/1 S 1/2 2/2 3/2 1/3 2/3 3/3 I/O via the border cells test patterns consist of sample voltages 1/16 16/16
FPT in the Loop Evolution System E measurement with FPG based controller write: configuration data test pattern candidate circuit read: measured data a real time chip-in-the-loop measuring system * Langeheine, Schemmel, Meier: CMOS FPT Chip for Hardware Evolution of nalog Electronic Circuits. Proceedings of the 2001 NS/DoD Conference on Evolvable Hardware.
Natural Evolution parent selection mutation evolutionary loop crossover aim: catching flies best fitness evaluation
Evolution of Transistor Circuits parent selection mutation evolutionary loop crossover aim: an inverter fitness evaluation
The Basic G: Variation Operators mutation operator randomly connecting...... nodes... transistors randomly varying...... width (W)... length (L)
It Works: Logic Gates, Gaussian Function first experiments: evolution of logic gates, gaussian circuits the G: straight forward implementation (Basic G) 5.5 4 5 NND 22 % 3.5 NND 4 3 3.5 Vout [V] NOR 4.5 Vout [V] gate success rate RMS<500mV 3 2.5 2 1.5 31 % 2.5 2 1.5 1 1 0.5 ND 29 % 0 OR 17 % 5.5 XOR Vout Vgoal 0 1 2 3 4 0 5 1 2 3 4 5 Vin2 [V] Vin2 [V] 5 4.5 1% XOR 4 90 runs each Vout [V] 3.5 3 2.5 2 1.5 1 0.5 0 0 1 2 3 Vin2 [V] 4 5 a fully functional configurable transistor array no trivial designed solution for a gaussian function circuit what now?
Ways to Go transfer to other technologies & discover new designs find solutions for complex circuits understanding evolved circuits investigate the course of evolution modelling next generation FPTs unconstrained evolution influence of parasitics using human made building blocks evolvability and representation
Building Blocks The design on transistor level allows for customizable building blocks How about a Logic Gates Cell Library? B B B B B B Inverter Buffer NOR NND * Langeheine*, Trefzer*, Schemmel, Meier: On the Evolution of nalog Electronic Circuits Using Building Blocks on a CMOS FPT. Proceedings of the Genetic and Evolutionary Computation Conference (GECCO 2004).
Building Blocks Place & route of the building blocks E exchanges building blocks and changes the connections
Building Blocks for Tone Discrimination Tackled problem: tone discriminator (based on. Thompson) 5 Input Voltage [V] 4 3 2 1 0 200 khz 40 khz 0 50 100 150 200 250 300 350 400 Time [us] 5 4 Inverter Buffer NOR NND B B B B Vout [V] 3 2 1 B B 0 100 200 300 400 Time [us]
Ways to Go transfer to other technologies & discover new designs find solutions for complex circuits understanding evolved circuits investigate the course of evolution modelling next generation FPTs unconstrained evolution influence of parasitics using human made building blocks evolvability and representation
The Turtle G: Variation Operators random wires mutation select start create wire create transistor validate
The Turtle G: Variation Operators implanting crossover select partners crossover block implant and validate
Transfer of evolved FPT circuits new variation operators to facilitate understanding of evolved circuits Æ Turtle G Basic G Turtle G SPICE netlist:.subckt evocir 3 1 5 m0 5 1 3 5 modp l=1u w=12u m1 3 3 0 0 modn l=1u w=5u.ends (0=gnd, 5=vdd) avoid unconnected nodes validate circuits in simulation use a simplified simulation model transfer to other technologies * Trefzer, Langeheine, Schemmel, Meier: New Genetic Operators to Facilitate Understanding of Evolved Transistor Circuits. Proceedings of the 2004 NS/DoD Conference on Evolvable Hardware.
Validate Evolved Comparators with SPICE how does a comparator look like? Characteristics of the best solutions Basic G Turtle G V out [V] V out [V] DC simulation (dashed line) V sweep [V] V sweep [V] V out [V] transient simulation (dashed=target voltage) time [ns]
Evolution of Comparators 50 evolution runs with a population size of 50 individuals are carried out for 20.000 generations respectively (100 gen/min) Basic G Turtle G reference comparators FPT measuring DC simulation trans. simulation rms error [V] rms error [V] no. of used transistors both algorithms perform equally well Turtle-G reduces ressource consumption comparison with basic human design 25% perform similar in a simulation with simplified FPT configuration circuitry best individual of run why do so many still not work in simulation?
Evolution likes it smooth... Example: NND Gate... unlike circuit simulators and human designers! increase the complexity of the problems amplifiers
Ways to Go transfer to other technologies & discover new designs find solutions for complex circuits understanding evolved circuits investigate the course of evolution modelling next generation FPTs unconstrained evolution influence of parasitics using human made building blocks evolvability and representation