RT A, V, 00kHz ACOT TM Synchronous Step-Down Converter General Description The RT is an adaptive on-time ACOT TM mode synchronous buck converter. The adaptive on-time ACOT TM mode control provides a very fast transient response with few external components. The low impedance internal MOSFET can support high efficiency operation with wide input voltage range from.5v to V. The proprietary circuit of the RT enables to support all ceramic capacitors. The output voltage can be adjustable between 0.5V and V. The soft-start is adjustable by an external capacitor. Ordering Information RT Package Type SP : SOP- (Exposed Pad-Option ) Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free) Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-00. Suitable for use in SnPb or Pb-free soldering processes. Features ACOT TM Mode Enables Fast Transient Response.5V to V Input Voltage Range A Output Current 0mΩ Internal Low Site N-MOSFET Adaptive On-Time Control Fast Transient Response Support All Ceramic Capacitors Up to 95% Efficiency 00kHz Switching Frequency Adjustable Output Voltage from 0.5V to V Adjustable Soft-Start Cycle-by-Cycle Current Limit Input Under Voltage Lockout Thermal Shutdown Protection RoHS Compliant and Halogen Free Applications Industrial and Commercial Low Power Systems Computer Peripherals LCD Monitors and TVs Green Electronics/Appliances Point of Load Regulation for High-Performance DSPs, FPGAs, and ASICs Marking Information RT ZSPYMDNN RTZSP : Product Number YMDNN : Date Code Pin Configurations (TOP VIEW) PVCC 9 5 SOP- (Exposed Pad)
Typical Application Circuit Chip Enable V IN C 0µF x C 0.µF C5.9nF 5, 9 (Exposed Pad) RT PVCC C 0.µF C µf L.µH V PVCC C R.5k R.k C µf x.05v/a Table. Suggested Component Values (V) R (k) R (k) C (pf) L (H) C (F).. --. to.05.5. --. to... --. to. 0.. 5 to to.5 9.9. 5 to to... 5 to to 5. 5 to. to 0. 5 to. to Functional Pin Description Pin No. Pin Name Pin Function PVCC Enable Input. A logic-high enables the converter; a logic-low forces the RT into shutdown mode reducing the supply current to less than 0A. Attach this pin to with a 00k pull up resistor for automatic start-up. Feedback Input. It is used to regulate the output of the converter to a set value via an external resistive voltage divider. The feedback reference voltage is 0.5V typically. Internal Regulator Output. Connect a F capacitor to to stabilize output voltage. Soft-Start Control Input. controls the soft-start period. Connect a capacitor from to to set the soft-start period. A.9nF capacitor sets the soft-start period to.5ms. Ground. The Exposed pad should be soldered to a large PCB and connected to 5, 9 (Exposed pad) for maximum thermal dissipation. Switch Node. Connect this pin to an external L-C filter. Bootstrap for High Side Gate Driver. Connect a 0.F or greater ceramic capacitor from to pins. Supply Input. The input voltage range is from.5v to V. Must bypass with a suitable large (0F x ) ceramic capacitor.
Function Block Diagram PVCC Reg UGATE OC Control Driver LGATE Soft-Start On-Time + - Comparator V REF
Absolute Maximum Ratings (Note ) Supply Voltage, ----------------------------------------------------------------------------------------------- 0.V to 0V Switch Voltage, ----------------------------------------------------------------------------------------------- 0.V to (V IN + 0.V) < 0ns----------------------------------------------------------------------------------------------------------------- 5V to 5V to -------------------------------------------------------------------------------------------------------- 0.V to V All Other Pins ------------------------------------------------------------------------------------------------------- 0.V to V Power Dissipation, P D @ T A = 5 C SOP- (Exposed Pad) --------------------------------------------------------------------------------------------.W Package Thermal Resistance (Note ) SOP- (Exposed Pad), θ JA --------------------------------------------------------------------------------------- 5 C/W SOP- (Exposed Pad), θ JC -------------------------------------------------------------------------------------- 5 C/W Junction Temperature Range ------------------------------------------------------------------------------------- 50 C Lead Temperature (Soldering, 0 sec.) ------------------------------------------------------------------------ 0 C Storage Temperature Range ------------------------------------------------------------------------------------- 5 C to 50 C Recommended Operating Conditions (Note ) Supply Voltage, -----------------------------------------------------------------------------------------------.5V to V Junction Temperature Range ------------------------------------------------------------------------------------- 0 C to 5 C Ambient Temperature Range ------------------------------------------------------------------------------------- 0 C to 5 C Electrical Characteristics ( = V, TA = 5 C, unless otherwise specified) Supply Current Parameter Symbol Test Conditions Min Typ Max Unit Shutdown Current I SHDN V = 0V -- 0 A Quiescent Current I Q V = V, V = V -- 0. -- ma Logic Threshold Voltage Logic-High -- 5.5 Logic-Low -- -- 0. V V REF Voltage and Discharge Resistance Feedback Reference Voltage V REF.5V V IN V 0.5 0.5 0. V Feedback Input Current I V = 0.V 0. 0 0. A V PVCC Output V PVCC Output Voltage V PVCC V V IN V, 0 < I PVCC 5mA. 5. 5.5 V Line Regulation V V IN V, I PVCC = 5mA -- -- 0 mv Load Regulation 0 I PVCC 5mA -- -- 0 mv Output Current I PVCC V IN = V, V PVCC = V -- 0 -- ma R DS(ON) Switch On High Side R DS(ON)_H -- 90 -- Resistance Low Side R DS(ON)_L -- 0 -- m Current Limit Current limit I LIM.5. 5. A
Parameter Symbol Test Conditions Min Typ Max Unit Thermal Shutdown Thermal Shutdown Threshold T SD -- 50 -- Thermal Shutdown Hysteresis T SD -- 0 -- On-Time Timer Control On-Time t ON V IN = V, =.05V -- 5 -- ns Minimum On-Time t ON(MIN) -- 0 -- ns Minimum Off-Time t OFF(MIN) -- 0 -- ns Soft-Start Charge Current V = 0V.. A Discharge Current V = 0.5V 0.05 0. -- ma UVLO UVLO Threshold Rising to Wake up V PVCC.55.5.5 Hysteresis -- 0. -- Note. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note. θ JA is measured at T A = 5 C on a high effective thermal conductivity four-layer test board per JEDEC 5-. θjc is measured at the exposed pad of the package. Note. The device is not guaranteed to function outside its operating conditions. C V 5
Typical Operating Characteristics Efficiency vs. Output Current Output Voltage vs. Output Current 00.0 90 Efficiency (%) 0 0 0 50 0 0 0 = 5V =.V =.05V Output Voltage (V).0.05.0 =.5V = V = V 0 0 = V.0 =.05V 0 0.5.5.5 Output Current (A) 0 0.5.5.5 Output Current (A) Output Voltage vs. Input Voltage Frequency vs. Input Voltage.0 900 Output Voltage (V).0.05.0 IOUT = 0A IOUT = A IOUT = A IOUT = A Frequency (khz) 00 00 00 500 =.05V =.05V, ILOAD = 0.A.0 00 0 Input Voltage (V) 0 Input Voltage (V) Reference Voltage vs. Temperature Reference Voltage vs. Input Voltage 0.0 0.0 0.5 0.5 Reference Voltage (V) 0.0 0.5 0.0 0.55 = V = V =.5V Reference Voltage (V) 0.0 0.5 0.0 0.55 No Load, =.05V 0.50-50 -5 0 5 50 5 00 5 Temperature ( C) 0.50 0 Input Voltage (V) No Load, =.05V
Shutdown Current vs. Temperature Quiescent Current vs. Temperature 0 9 V = 0V 0.0 0.5 Shutdown Current (µa) 5 = V = V =.5V Quiescent Current (ma) 0.0 0.5 0.0 0.55 0.50 0.5 0.0 = V = V =.5V 0-50 -5 0 5 50 5 00 5 Temperature ( C) 0.5 0.0 V = V, V = V -50-5 0 5 50 5 00 5 Temperature ( C) Current Limit vs. Input Voltage Current Limit vs. Temperature Current Limit (A) 5 Current Limit (A) 5 = V = V =.5V 0 0 Input Voltage (V) = 0V = 0V 0-50 -5 0 5 50 5 00 5 Temperature ( C) Load Transient Response Output Voltage Ripple (0mV/Div) (0mV/Div) I OUT (A/Div) V (0V/Div) = V, =.05V, IOUT = 0A to A = V, =.05V, IOUT = A Time (00μs/Div) Time (500ns/Div)
Power On from V IN Power Off from V IN V IN (0V/Div) (0V/Div) (V/Div) (V/Div) V (0V/Div) I OUT (5A/Div) V (0V/Div) I OUT (5A/Div) = V, =.05V, IOUT = A Time (5ms/Div) = V, =.05V, IOUT = A Time (0ms/Div) Power On from V Power Off from V V (5V/Div) V (5V/Div) (V/Div) (V/Div) V (0V/Div) I OUT (5A/Div) V (0V/Div) I OUT (5A/Div) = V, =.05V, IOUT = A Time (5ms/Div) = V, =.05V, IOUT = A Time (00μs/Div)
Application Information The RT is a synchronous high voltage buck converter that can support the input voltage range from.5v to V and the output current can be up to A. It operates using adaptive on-time ACOT TM mode control and provides a very fast transient response with few external compensation components. The RT allows low external component count configuration with both low ESR and ceramic output capacitors. Chip Enable Operation The pin is the chip enable input. Pulling the pin low (<0.V) will shutdown the device. During shutdown mode, the RT quiescent current drops to lower than 0μA. Driving the pin high (>V, <5.5V) will turn on the device again. For external timing control, the pin can also be externally pulled high by adding a R * resistor and C * capacitor from the pin (see Figure ). PWM Operation It is suitable for low external component count configuration with appropriate amount of Equivalent Series Resistance (ESR) capacitor(s) at the output. The output ripple valley voltage is monitored at a feedback point voltage. The synchronous high side MOSFET is turned on at the beginning of each cycle. After the internal one shot timer expires, the MOSFET is turned off. The pulse width of this one shot is determined by the converter's input and output voltages to keep the frequency fairly constant over the entire input voltage range. V IN.5V to V Chip Enable * : Optional R * C * C C5 5, 9 (Exposed Pad) RT Figure. External Timing Control PVCC C C L R C R Adaptive On-Time Control The RT has a unique circuit to ensure the switching frequency on 00kHz over full input voltage range and full loading range. This circuit sets the on-time one-shot timer by monitoring the input voltage and signal. The switching frequency will keep constant if the duty ratio is /V IN. Duty Ratio = /V IN = t ON / T For Fixed T, Ton is proportional to /V IN. Soft-Start The RT contains an external soft-start clamp that gradually raises the output voltage. The soft-start timing can be programmed by the external capacitor between pin and. The chip provides a μa charge current for the external capacitor. If a.9nf capacitor is used, the soft-start will be ms (typ.). The available capacitance range is from.nf to 0nF. An external MOSFET can be added to implement digital control on the pin when no system voltage above V is available, as shown in Figure. In this case, a 00kΩ pull-up resistor, R, is connected between V IN and the pin. MOSFET Q will be under logic control to pull down the pin. V IN Chip Enable R 00k Q C C5 5, 9 (Exposed Pad) RT PVCC C L C Figure. Logic Control with Low Voltage R R C t (ms) = C5 (nf).05 I ( A) 9
To prevent enabling circuit when V IN is smaller than the target value, a resistive voltage divider can be placed between the input voltage and ground and connected to the pin to adjust IC lockout threshold, as shown in Figure. For example, if an V output voltage is regulated from a V input voltage, the resistor R can be selected to set input lockout threshold larger than V. V IN V R 00k R C C5 5, 9 (Exposed Pad) RT Figure. The Resistors can be Selected to Set IC Lockout Threshold Output Voltage Setting The resistive divider allows the pin to sense the output voltage as shown in Figure. RT PVCC Figure. Output Voltage Setting The output voltage is set by an external resistive divider according to the following equation. It is recommended to use % tolerance or better divider resistors. R = V ( + ) R Where V is the feedback reference voltage (0.5V typ.). Under Voltage Lockout Protection The RT has Under Voltage Lockout Protection (UVLO) that monitors the voltage of PVCC pin. When the V PVCC voltage is lower than UVLO threshold voltage, the RT will be turned off in this state. This is non-latch protection. Over Temperature Protection The RT equips an Over Temperature Protection (OTP) circuitry to prevent overheating due to excessive power R R C L C R R V C dissipation. The OTP will shut down switching operation when junction temperature exceeds 50 C. Once the junction temperature cools down by approximately 0 C the main converter will resume operation. To maintain continuous operation maximum, the junction temperature should be prevented from rising above 50 C. Inductor Selection The inductor value and operating frequency determine the ripple current according to a specific input and an output voltage. The ripple current ΔI L increases with higher V IN and decreases with higher inductance. V V I = L OUT OUT fl Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. High frequency with small ripple current can achieve highest efficiency operation. However, it requires a large inductor to achieve this goal. For the ripple current selection, the value of ΔI L = 0.(I MAX ) will be a reasonable starting point. The largest ripple current occurs at the highest V IN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : L = f I L(MAX) V IN(MAX) C IN and C OUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the high side MOSFET. To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current should be used. The RMS current is given by : I RMS = IOUT(MAX) This formula has a maximum at V IN =, where I RMS = I OUT /. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For the input capacitor, two 0μF and 0.μF low ESR ceramic capacitors are recommended. 0
The selection of C OUT is determined by the required ESR to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for C OUT selection to ensure that the control loop is stable. The output ripple, Δ, is determined by : IL ESR fc OUT The output ripple will be highest at the maximum input voltage since ΔI L increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, V IN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at V IN large enough to damage the part. External Bootstrap Diode Connect a 0.μF low ESR ceramic capacitor between the and pins. This capacitor provides the gate driver voltage for the high side MOSFET. It is recommended to add an external bootstrap diode between an external 5V and the pin for efficiency improvement when input voltage is lower than 5.5V or duty ratio is higher than 5%. The bootstrap diode can be a low cost one such as N or BAT5. The external 5V can be a 5V fixed input from system or a 5V output of the RT. Note that the external boot voltage must be lower than 5.5V 5V RT 0.µF PVCC Capacitor Selection Decouple with a μf ceramic capacitor. XR or X5R grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. Over Current Protection When the output shorts to ground, the inductor current decays very slowly during a single switching cycle. A over current detector is used to monitor inductor current to prevent current runaway. The over current detector monitors the voltage between and during the low-side MOS turn-on state. This is cycle-by-cycle protection. The over current detector also supports temperature compensated. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : P D(MAX) = (T J(MAX) T A ) / θ JA where T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and θ JA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 5 C. The junction to ambient thermal resistance, θ JA, is layout dependent. For SOP- (Exposed Pad) packages, the thermal resistance, θ JA, is 5 C/W on a standard JEDEC 5- four-layer thermal test board. The maximum power dissipation at T A = 5 C can be calculated by the following formulas : P D(MAX) = (5 C 5 C) / (5 C/W) =.W for SOP- (Exposed Pad) package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θ JA. The derating curves in Figure allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Figure 5. External Bootstrap Diode
Maximum Power Dissipation (W). Four-Layer PCB...0 0. 0. 0. 0. 0.0 0 5 50 5 00 5 Ambient Temperature ( C) Figure. Derating Curve of Maximum Power Dissipation Layout Consideration Follow the PCB layout guidelines for optimal performance of the RT Keep the traces of the main current paths as short and wide as possible. Put the input capacitor as close as possible to the device pins ( and ). node is with high frequency voltage swing and should be kept at small area. Keep sensitive components away from the node to prevent stray capacitive noise pickup. Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the RT. The and Exposed Pad should be connected to a strong ground plane for heat sinking and noise protection. The resistor divider must be connected as close to the device as possible. R R C C5 PVCC 9 5 C C Input capacitor must be placed as close to the IC as possible. C C should be connected to inductor by wide and short trace. Keep sensitive components away from this trace. L Figure. PCB Layout Guide
Outline Dimension A H M EXPOSED THERMAL PAD (Bottom of Package) J Y X B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A.0 5.00 0.9 0.9 B.0.000 0.50 0.5 C..5 0.05 0.09 D 0.0 0.50 0.0 0.00 F.9. 0.0 0.05 H 0.0 0.5 0.00 0.00 I 0.000 0.5 0.000 0.00 J 5.9.00 0. 0. M 0.0.0 0.0 0.050 Option Option X.000.00 0.09 0.09 Y.000.00 0.09 0.09 X.00.500 0.0 0.09 Y.000.500 0. 0. -Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation F, No., Tai Yuen st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: ()559 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.