CMOS Digital Integrated Circuits 74HC595D Silicon Monolithic 74HC595D 1. Functional Description 8-Bihift Register/Latch (3-state) 2. General The 74HC595D is a high speed 8-BIT SHIFT REGISTER/LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The 74HC595D contai an 8-bit static shift register which feeds an 8-bit storage register. Shift operation is accomplished on the positive going traition of the SCK input. The output register is loaded with the contents of the shift register on the positive going traition of the RCK input. Since RCK and SCK signal are independent, parallel outputs can be held stable during the shift operation. And, since the parallel outputs are 3-state, it can be directly connected to 8-bit bus. This register can be used in serial-to-parallel conversion, data receivers, etc. All inputs are equipped with protection circuits agait static discharge or traient excess voltage. 3. Features (1) High speed: f MAX = 55 MHz (typ.) at CC = 5 (2) Low power dissipation: I CC = 4. (max) at T a = 25 (3) Balanced propagation delays: t PLH t PHL (4) Wide operating voltage range: CC(opr) = to 4. Packaging SOIC16 1 Start of commercial production 216-2
5. Pin Assignment 6. Marking 7. IEC Logic 2
8. Truth Table X: Don't care 9. Timing Chart 3
1. System Diagram 11. Absolute Maximum Ratings (Note) Note Rating Supply voltage Input voltage Output voltage Input diode current Output diode current Output current (QH') Output current (QA to QH) CC /ground current Power dissipation Storage temperature CC IN OUT I IK I OK I OUT I CC P D T stg (Note 1) -.5 to 7. -.5 to CC +.5 -.5 to CC +.5 ±2 ±2 ±25 ±35 ±75-65 to 1 Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditio (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ( Handling Precautio / Derating Concept and Methods ) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: P D derates linearly with -8 mw/ above 85 ma ma ma ma mw 4
12. Operating Ranges (Note) Rating Supply voltage Input voltage Output voltage Operating temperature Input rise and fall times Note: CC IN OUT T opr t r,t f to to CC to CC -4 to 125 to The operating ranges must be maintained to eure the normal operation of the device. Unused inputs must be tied to either CC or GND. µs 5
. Electrical.1. DC (Unless otherwise specified, T a = 25 ) CC () Min Typ. Max High-level input voltage IH 1. 3. 4.2 Low-level input voltage IL. 1.35 1.8 OH IN = IH or IL I OH = -2 1.9 4.4 5.9 QH' I OH = -4 ma I OH = -5.2 ma 4.18 5.68 4.31 5.8 QA to QH I OH = -6 ma I OH = -7.8 ma 4.18 5.68 4.31 5.8 OL IN = IH or IL I OL = 2... QH' I OL = 4 ma I OL = 5.2 ma 7 8.26.26 QA to QH I OL = 6 ma I OL = 7.8 ma 7 8.26.26 3-state output OFF-state leakage current I OZ IN = IH or IL OUT = CC or GND ±.5 Input leakage current I IN IN = CC or GND ± Quiescent supply current I CC IN = CC or GND 4. 6
.2. DC (Unless otherwise specified, T a = -4 to 85 ) CC () Min Max High-level input voltage IH 1. 3. 4.2 Low-level input voltage IL. 1.35 1.8 OH IN = IH or IL I OH = -2 1.9 4.4 5.9 QH' I OH = -4 ma I OH = -5.2 ma 4. 5.63 QA to QH I OH = -6 ma I OH = -7.8 ma 4. 5.63 OL IN = IH or IL I OL = 2 QH' I OL = 4 ma I OL = 5.2 ma.33.33 QA to QH I OL = 6 ma I OL = 7.8 ma.33.33 3-state output OFF-state leakage current I OZ IN = IH or IL OUT = CC or GND ±5. Input leakage current I IN IN = CC or GND ±1. Quiescent supply current I CC IN = CC or GND 4. 7
.3. DC (Unless otherwise specified, T a = -4 to 125 ) CC () Min Max High-level input voltage IH 1. 3. 4.2 Low-level input voltage IL. 1.35 1.8 OH IN = IH or IL I OH = -2 1.9 4.4 5.9 QH' I OH = -4 ma I OH = -5.2 ma 3.7 5.2 QA to QH I OH = -6 ma I OH = -7.8 ma 3.7 5.2 OL IN = IH or IL I OL = 2 QH' I OL = 4 ma I OL = 5.2 ma.4.4 QA to QH I OL = 6 ma I OL = 7.8 ma.4.4 3-state output OFF-state leakage current I OZ IN = IH or IL OUT = CC or GND ±1. Input leakage current I IN IN = CC or GND ±1. Quiescent supply current I CC IN = CC or GND 16. 8
.4. Timing Requirements (Unless otherwise specified, T a = 25,, Input: t r = t f = 6 ) CC () Limit Minimum pulse width (SCK, RCK) t w(l),t w(h) 75 Minimum pulse width (SCLR) t w(l) 75 Minimum setup time (SI-SCK) 1 9 Minimum setup time (SCK - RCK) 75 Minimum setup time (SCLR -RCK) 1 2 17 Minimum hold time t h Minimum removal time (SCLR) t rem 1 9 Clock frequency f 6 MHz 35 9
.5. Timing Requirements (Unless otherwise specified, T a = -4 to 85,, Input: t r = t f = 6 ) CC () Limit Minimum pulse width (SCK, RCK) t w(l),t w(h) 95 19 16 Minimum pulse width (SCLR) t w(l) 95 19 16 Minimum setup time (SI-SCK) 65 11 Minimum setup time (SCK - RCK) 95 19 16 Minimum setup time (SCLR -RCK) 125 25 21 Minimum hold time t h Minimum removal time (SCLR) t rem 65 11 Clock frequency f 5 MHz 25 28 1
.6. Timing Requirements (Unless otherwise specified, T a = -4 to 125,, Input: t r = t f = 6 ) CC () Limit Minimum pulse width (SCK, RCK) t w(l),t w(h) 11 22 19 Minimum pulse width (SCLR) t w(l) 11 22 19 Minimum setup time (SI-SCK) 75 Minimum setup time (SCK - RCK) 11 22 19 Minimum setup time (SCLR -RCK) 1 26 Minimum hold time t h Minimum removal time (SCLR) t rem 75 Clock frequency f 4 MHz 2 24.7. AC (Unless otherwise specified, C L = pf, CC = 5, T a = 25,, Input: t r = t f = 6 ) Min Typ. Max Output traition time (QH') t TLH,t THL 4 8 (SCK-QH') t PLH,t PHL 12 21 (SCLR-QH') t PHL Maximum clock frequency f MAX 35 55 MHz 11
.8. AC (Unless otherwise specified, T a = 25,, Input: t r = t f = 6 ) Note C L (pf) CC () Min Typ. Max Output traition time (Qn) Output traition time (QH') (SCK-QH') (SCLR -QH') (RCK-Q n ) Output enable time Output disable time Maximum clock frequency Input capacitance Power dissipation capacitance t TLH,t THL t TLH,t THL t PLH,t PHL t PHL t PLH,t PHL t PZL,t PZH t PLZ,t PHZ f MAX C IN C PD (Note 1) R L = 1 kω R L = 1 kω Note 1: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation. I CC(opr) = C PD CC f IN + I CC 1 1 6 35 25 7 6 8 7 45 6 18 6 2 17 75 25 22 45 6 2 17 14 17 59 3 41 6 12 1 75 125 25 21 175 35 1 26 19 38 32 5 27 23 175 35 1 26 MHz pf pf 12
.9. AC (Unless otherwise specified, T a = -4 to 85,, Input: t r = t f = 6 ) C L (pf) CC () Min Max Output traition time (Qn) t TLH,t THL 75 Output traition time (QH') t TLH,t THL 95 19 16 (SCK-QH') t PLH,t PHL 5 31 26 (SCLR -QH') t PHL 22 44 37 (RCK-Q n ) t PLH,t PHL 19 38 32 1 24 48 41 Output enable time t PZL,t PZH R L = 1 kω 17 34 29 1 22 44 37 Output disable time t PLZ,t PHZ R L = 1 kω 19 38 33 Maximum clock frequency f MAX 5 MHz 25 28
.1. AC (Unless otherwise specified, T a = -4 to 125,, Input: t r = t f = 6 ) C L (pf) CC () Min Max Output traition time (Qn) t TLH,t THL 9 18 Output traition time (QH') t TLH,t THL 1 23 2 (SCK-QH') t PLH,t PHL 24 48 31 (SCLR -QH') t PHL 265 53 45 (RCK-Q n ) t PLH,t PHL 265 53 45 1 285 57 48 Output enable time t PZL,t PZH R L = 1 kω 225 45 38 1 265 53 45 Output disable time t PLZ,t PHZ R L = 1 kω 225 45 38 Maximum clock frequency f MAX 4 MHz 2 24 14
14. AC Waveform t TLH, t THL, t PLH, t PHL t w, t s, t h, t rem
Package Dimeio : mm Weight:. g (typ.) Package Name(s) Nickname: SOIC16 16
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