44 CHAPTER 3 A COMPARION OF MULTILEVEL INVERTER UING IN 3-PHAE INDUCTION MOTOR 3.1 Introduction Now a days the use of multi-level inverters are increasing day to day life and they playing a vital role in case of medium and high power applications due to having less harmonic content compared with classical inverters[77]. Multilevel inverter has level of 3, 5, 7, 9, 11, etc. This chapter has a discussion about even Level Cascaded Inverter and Nine Level Cascaded H-bridge inverter. In Conventional method, Five Level Cascaded H-bridge Multilevel Inverter was discussed [13]. 3.2 ignificance of Cascaded H-Bridge Multilevel Inverter Cascaded H-bridge Five level inverter is shown in Fig. 3.1. The Inverter consists of two series connected H-bridge cells which are fed by independent voltage sources. The outputs of the H-bridge cells are connected in series such that the synthesized voltage waveform is the sum of all of the individual cell outputs [11]. The output voltage is given by.where the output voltage of the first cell is labeled and the output voltage of the second cell is denoted by. There are five level of output voltage i.e. 2V,V,0,-V,-2V.The main advantages of cascaded H-bridge inverter is that it requires least number of components, modularized circuit and soft switching can be employed. But the main disadvantage is that when the voltage level increases, the number of switches increases and also the sources, this in effect increases the cost and weight [15]. The cascaded H-bridge multilevel inverters have been applied where high power[14] and power quality are essential, for example, static synchronous compensators, active filter and reactive power compensation applications, photovoltaic power conversion, uninterruptible power supplies, and
45 magnetic resonance imaging. Furthermore, one of the growing applications for multilevel motor drive is electric and hybrid power trains [12]. Fig. 3.1 Five level cascaded H-bridge multilevel inverter circuit. The new cascaded five level H bridge multilevel inverter [51] and [55]. One switching element and four diodes added in the conventional full-bridge inverter are connected to the centre tap of dc power supply [16]. Proper switching control of the auxiliary switch can generate half level of dc supply voltage. It has five output voltage levels that is V, V/2, 0, -V/2, -V. For getting the output voltage V the switches 14 need to be turned on. imilarly for output voltage V/2 switches 4 5 need to be turned on, for 0 either 3 4 or 1 2 need to be turned on; for V/2 switches 2 5 need to be turned on; for V switches 2 3 need to be turned on [17] and [74]. The switching combinations are shown in Table 3.1.
46 Table 3.1 Five Level switching combinations. 1 2 3 4 5 OUTPUT VOLTAGE ON OFF OFF ON OFF V OFF OFF OFF ON ON V/2 OFF or ON OFF or ON ON or OFF ON or OFF OFF 0 OFF ON OFF OFF ON -V/2 OFF ON ON OFF OFF -V 3.3 Cascaded H-Bridge even Level Inverter A seven -level cascaded H-bridge multilevel inverter has three H-bridges as shown in Fig.3.2 [49]. The DC source for the three H-bridges H1, H2, and H3 is. In this topology the output voltage of the individual H bridges is, 0 or +. Therefore the output voltage of the inverter can have the values 2,, 0, -, - 2, which gives a Five Level output voltage. The switching states of five level output voltage is given in the Table 3.1. The number of voltage levels (m) in the phase voltage of Cascaded H-Bridge Multi Level Inverter (CHMLI) inverter can be found from,[m = (2N + 1)] Where N is the number of H-bridge cells per phase leg the maximum output phase voltage of these N cascaded multilevel inverters [10].
47 Table 3.2 witching Pattern for ymmetric Cascaded even Level Inverter. OUT 11 12 13 14 21 22 23 24 31 32 33 34 PUT 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0
48 Fig. 3.2 Cascaded H-Bridge even Level Inverter Topology. 3.4 Cascaded Nine Level Inverter Circuit configuration of a general cascaded H-bridge Nine Level Inverter is shown in Fig.3.3. Each H-bridge module has an independent DC voltage source of E. Every output terminal of H-bridge cells is connected in series [30]. o the output voltage can be obtained by Eq. (3.1). And the number of output voltage levels is obtained by Eq. (3.2).
49 Fig.3.3 Block diagram of Cascaded Nine Level Inverter. In Eq. (3.1), can be E, 0, or -E therefore, can produce -4E, -3E, -2E, -E, 0, E, 2E, 3E, 4E by mixing of each output voltage. We can notice that this kind of
50 Multi Level Inverter is advantageous in terms of modularity and simplicity. However, it needs 16 switches and 4 independent DC input sources to produce nine output voltage levels [39]. Table 3.3 witching function for generating 9- level output voltage. No of output witching Function Output Voltage of each inverter Output Voltage (V out ) levels F1 F2 V x V y 4 2 2 2E 2E 4E 3 2 1 2E E 3E 1 2 E 2E 2 1 1 E E 2E 0 2 0 2E 2 0 2E 0 1 0 1 0 E E 1 0 E 0 2-1 2E -E -1 2 -E 2E 0 0 0 0 0 0
51 3.5 Cascaded Nine Level inverter fed induction motor Fig.3.4 circuit diagram for cascaded nine level inverter fed Induction motor. Developed Cascaded Nine Level Inverter for three phases shown in Fig.3.4. Three phase Induction motor used as load in our analysis. Compare to other AC drives, induction motors are robust and can operate in any Environmental condition. Induction motors can be operated in polluted and explosive environments as they do not have brushes which can cause sparks. Presented Nine Level Inverter promoted for induction drive application.
52 Applications of Three Phase Induction Motor are 1. Lathes and drilling machines, 2. Agricultural and industrial pumps, 3. Industrial drives and Lifts, 4. Cranes and Conveyors. 3.6 Conventional 4- bit counter based PWM Generator. A number of PWM methods are used to get the high frequency supply as well as reduce the chip size [74]. The Pulse width of PWM pulse changes with the ine wave so as to hold back the lower order harmonics with simple control and great DC utilization. With successively getting better reliability and performance of digital controllers, the digital control techniques have majority over other analog controlled parts. Fig. 3.5 Circuit Diagram of counter based PWM generation unit.
53 The Counter based PWM generator is one of the easiest mechanisms of implementation of PWM. In this research, the evaluation is based upon the FPGA implementation of three types of PWM Generation. Based on the evaluation results, the PWM Generation consumes the least amount of area consumption in FPGA. The system input is an N-bit data word related to the desired PWM duty cycle value, so that it can be simply interfaced to a micro-controller unit I/O port pins. Fig. 3.6 Block diagram of conventional N-bit binary counter.
54 3.6.1 Result and discussions about Counter based PWM generation technique Counter based PWM unit is consisting of Register, Regular 4-bit binary counter, 4-bit Comparator and R latch. A Pipelined technique is applied in the counter based PWM methods. Pipelined techniques means, Register unit is included in the first and last stages of the circuits. Hence the delay of the counter based PWM circuit is reduced and frequency of the circuit is increased. But it consumes more area than the without pipelined techniques. imulation is carried out by Modelim6.3c and ynthesize is carried out Xilinx10.1.imulation and synthesis result of N-bit counter based PWM are shown in figures 3.7, 3.8 & 3.9. Fig.3.7 imulation result of Counter based PWM based on pipelined techniques.
55 imulation process is performed to check the functionality of PWM generation technique. Counter based PWM pulse is generated using Verilog Hardware Description Languages (HDL). Whenever counter values meats the input values that time PWM pulses are generated as shown in Fig.3.6. Fig.3.8 ynthesis result of Counter based PWM architecture for hardware utilization. ynthesis process is performed to analyze the hardware requirement and processing speed of counter based PWM generation scheme. Hardware requirement is analyzed through (Register Transfer Level) RTL view. Area and delay utilization is measured by Xilinx10.1 as shown in Fig.3.9 and 3.10.
56 Area utilization of counter based PWM Delay utilization of counter based PWM Fig.3.9 ynthesis result of Counter based PWM architecture for area, delay and frequency utilization.
57 From the simulation result, PWM pulse are generated whenever the counter reach the overflow condition, (i.e.) 4 bit counter reach 1111, that time Pulse Width modulation pulses are generated using Modelim6.3c. From the synthesis result, the area (lices) of counter based PWM is 12 and the frequency is 355.315 MHz This PWM pulses are implemented using FPGA partan3 xc3s50. Counter based PWM pulses are given as triggering pulses for even Level Inverter and Nine Level Inverter. 3.7 Total Harmonics Distortion (THD) analysis between even Level and Nine Level Inverter This chapter is used to analyze the performance of Cascade Multi Level Inverter. The result shows that the Proposed Nine Level Inverter circuit is having Lesser THD Value than the even Level inverter circuit as shown in the table 3.4. Matlab imulink is used to take the THD analysis of these inverters. In the cascade Nine Level Inverter, switching losses is very low compared to cascade even Level Inverter. Table 3.4 Comparison of seven and nine Level inverter circuits with THD. Parameters even level inverters Nine level inverters Frequency 33.21 t 68.8 t Total Harmonics Distortion (THD) 80.15 (%) 40.20 (%)
58 90 80 70 60 80.15 68.8 50 40 33.21 40.2 THD FREQ 30 20 10 0 7 LEVEL 9 LEVEL Fig. 3.10 Comparison chart of even Level and Nine Level Inverters. In this research, design and simulation of an interconnected H-bridge singlephase inverter is explored. The inverter is simulated and recommendations were made for implementing a hardware prototype. The purpose of work is to draw conclusions on whether the nine levels Inverter produce less low harmonics and high frequency than a seven level inverter. For that reason, two different inverter circuits were simulated, and compared the results. 3.8 Conclusion In this research work, Comparison between even Level and Nine Level inverters is processed to analyze the performance of Multi Level Inverter. Cascade Nine Level Inverter based on Low Total Harmonics Distortion (THD) at High frequency is performed by introducing Counter based PWM as triggering pulse for this Multi Level inverter.