CELL DESIGN METHODOLOGY FOR LOWPOWER HIGHSPEED BALANCED THREEINPUT XOR XNOR IN HYBRIDCMOS LOGIC STYLE. Abstract In this paper, a systematic design methodology based on pass transistor and transmission gate in the category of hybridcmos Logic style is proposed and used for design balanced 3input XOR/XNOR circuits. In this methodology, designer utilize various basic cells, including three independent inputs and two complementary outputs, and different mechanisms,correction and optimization techniques, to build new circuits with desired performance and diverse range of applications. Accordingly, six new fullswing balanced 3input XOR/XNOR circuits are proposed with high driving capability, fullbalanced fullswing outputs and low number of transistors of basic structure, high performance, operating at low voltages and excellent signal integrity. As an especial feature, the critical path of the presented designs consists of only two transistors, which causes low propagation delay. All simulations have been performed with TSMC µm technology, in optimum state of the circuits from viewpoint of transistor sizing, to achieve the minimum powerdelay product (PDP). On an average, these circuits outperform their counterparts showing 10%60% improvement in the powerdelay product. Keywords Design methodology; Arithmetic circuits; balanced 3input XOR/XNOR circuits; hybridcmos logic; energy efficiency. I. INTRODUCTION The exclusiveor (XOR) and exclusivenor (XNOR) gates are the essential parts of several digital systems and are highly used in very large scale integration (VLSI) systems [1] such as parity checkers, comparators, crypto processors [2][3], arithmetic and logic circuits [47], test pattern generators [8], especially in Full adder module as Sum output that is 3input XOR and so forth. In most of these systems, XOR and XNOR gates constitute a part of the critical path of the system, which significantly affects the worstcase delay and the overall performance of the system. An optimized design is desired to avoid any degradation on the output voltage, consume less power, and have less delay in critical path with lowsupply voltage as we scale toward deep submicron technology. Other desired features for the design are to have a small number of transistors to implement the circuit. In particular, for XOR and XNOR circuits, the simultaneous generation of the twononskewed outputs is highly desirable [9]. As known, the switching speed of the balanced XOR and XNOR functions, comparing with those designs that use an inverter to generate the complement signal, is increased by eliminating the inverter from the critical path [911]. In this paper, we present a formal design method for balanced 3input XOR XNOR circuits in the hybridcmos logic style. In our approach, we start with selecting a basic cell including 3input and two outputs. Next and if necessary we apply various correction mechanisms and optimization methods to obtain balanced 3input XOR XNOR circuits. Accordingly and by using four basic cells, we come up with six balanced 3input XOR XNOR circuits. In any type of logic design, the non fullswing outputs play a decisive role in cell drivability. Full swing outputs impact multistage structured arithmetic circuit performance [12][13]. Therefore, designers consider achieving full swing output operations as an important factor in the basic block design of arithmetic circuits. In addition, all of the proposed circuits whose critical path contains only two transistors have low average power consumption and delay. The proposed circuits features balanced outputs, making it easy for large tree structured arithmetic circuits to maximize area efficiency without unduly degrading the VLSI power and delay. The rest of this paper is organized as follows. Section 2 begins with the introduction of the design methodology, and the structure of the elementary basic cell. We use this basic cell and introduce two different alternative basic cells based on pass transistor and transmission gate. In addition, we state optimization and correction mechanisms shortly. In Section 3, we introduce six novel balanced 3input XOR/XNOR circuits using basic cells in conjunction with the mechanisms. In Section 4, we report simulation results. We
analyze the method in Section 5. Finally, we offer concluding remarks in Section 6. II. DESIGN METHODOLOGY OF BALANCED 3INPUT XOR/XNOR CIRCUITS In this section, design methodology for 3input XOR/XNOR circuits introduced. This methodology is based on using different basic cells and optimization mechanisms. To obtain basic cells, 3input XOR/XNOR function is investigated. For choosing the mechanisms, we use the simulation results of [10][11] in which the balanced two inputs XOR/XNOR circuits based on the Cell2 have possessed better results. A. The Elementary Basic Cell In the process of designing balanced 3input XOR XNOR circuits, we face three independent inputs and two complementary outputs. The elementary basic cell which is extracted of minimum sum of product form of 3input XOR XNOR in Eq. 1 has been presented in Fig. 1. This cell has eight elements, deciding two outputs. Each element is a pass transistor or transition gate and has two input controls, i.e., the gate and either the drain or the source..... (1) We present the first version of the elementary basic cell (referred to as BC1) in Fig. 2. In this cell, all six transistors are nmos. Truth table of the BC1 in Fig. 2 shows the output levels of this circuit for each input vector. To convert BC1 to an XOR XNOR circuit that produces full swing output signals, it is necessary to replace high impedance outputs with logic 1 or 0. Moreover, in order to obtain better performance, non fullswing outputs for some input vectors must be converted into full swing signals. B A C XOR3 XNOR3 0 0 0 Hiz Hiz 0 0 1 Hiz 0 0 1 0 Hiz Hiz 0 1 1 0 Hiz 1 0 0 Hiz 0 1 0 1 0 1 1 1 0 0 Hiz 1 1 1 1 0 Figure 2. BC1 circuit and input and output values 2) Basic Cell: Version II We present basic cell 2 (referred as BC2) in Fig. 3. In this cell, nmos transistors for all four external section boxes and transition gate for central section boxes are selected. Fig. 3 shows outputs for each input vector. In order to convert the BC2 into an XOR XNOR circuit, which provides full swing operation, it is necessary that the high impedance states of outputs in Fig. 3 be replaced with 1. We also have to optimize the circuit using various methods to eliminate the non fullswing operation. Figure 1. The elementary basic cell. The input signals (applied to the two input terminals of these transistors) and the selection of pmos, nmos transistors and transition gate decide various output states. As presented in Fig. 1, we refer to the pins of central section (IN1 to IN4 and G1 to G4) as A or C, or their complements respectively. We assume that pins of external section G5 to G8 can also be B or its complement. Another form of the elementary basic cell is obtained by swapping the position of B or its complement that is G5 to G8 and the outputs of central section that are the drains or the sources of external section. This form of the circuit (as the elementary basic cell) is powerless and groundless (P/G).Therefore, the complementary outputs are only affected by input drivability and charged or discharged. B. The Introduction of Basic Cells 1) Basic Cell: Version I B A C XOR3 XNOR3 0 0 0 0 Hiz 0 0 1 Hiz 0 0 1 0 Hiz 0 0 1 1 0 Hiz 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 Figure 3. BC2 circuit and input and output values. C. Correction and optimization mechanisms Correction and optimization mechanisms are pull up/down networks, feedback networks, bootstrap technique, output inverters and combinational mechanism named after applying the two mechnasims simultaneously on basic cell [10][11].
III. INTRODUCTION OF BALANCED 3INPUT XORXNOR CIRCUITS In Section II, two basic cells were introduced. To convert these cells into balanced 3input XORXNOR circuits with acceptable performance, two main steps should be employed. In the first step, the high impedance output states should be eliminated. In the second step, non fullswing output signals should be fixed. Three selected mechanisms such as feedback networks and combinational mechanisms such as pull up/down with feedback networks and pull up/down networks with bootstrap technique are applied and presented the circuits with names XO1 through in Table I. As mentioned, we used simulation results of the best circuits in [10] and [11] to extract these mechanisms. TABLE I. INTRODUCTION OF XOR/XNOR CIRCUITS IN DIFFERENT CLASSES WITH THEIR MECHANISMS Class A B C Name XO1 Basic cell BC1 BC2 BC1 BC2 BC1 BC2 Feedback network Fc Fp Fc Fp Pull up/down network Bootstrap technique n p A. Class A 3input XORXNOR Circuits In this Section, class A circuits are introduced (Table I). This group of circuits uses feedback network mechanisms to convert the basic cells into XORXNOR circuits providing full swing output signals. For each one of the basic cells, we select a proper feedback network [10]. We present Class A circuits with the names XO1 and in Fig. 4. s Figure 5. New 3input XOR/XNOR Circuits and. C. Class C 3input XORXNOR Circuits Class C circuits include XOR XNOR circuits in which bootstrap technique has been used to ensure the full swing operation, and the high impedance states at the outputs have been corrected using pull up and pull down networks. This technique could be used for BC1 and BC2 since they all suffer from the no full voltage swing as well as the high impedance states at the output nodes. Circuits and in class C are optimized versions of BC1 and BC2 respectively. Class C circuits that are introduced in Table I and Fig. 6 employ the combinational mechanisms. Figure 6. New 3input XOR/XNOR Circuits and. Figure 4. New 3input XOR/XNOR Circuits XO1 and. B. Class B 3input XORXNOR Circuits Class B circuits are a group of XORXNOR circuits (Table I) in which pull up and pull down networks and feedback networks are used simultaneously. In this class pull up and pull down networks are used to eliminate critical states and feedback networks are employed to rectify the output levels. Class B circuits, and, are presented in Fig. 5. IV. SIMULATION SETUP In this section, the performance of the proposed methodologies is investigated. For comparison, the four circuits Sum_TFA [1417], Sum_New14T [1417], Sum_NEWHPSC [9], Sum_Hybrid [17], SUM module of full adder circuits with full swing outputs, are selected. For producing XNOR in these selected circuits, we used inverter gate. All the circuits are designed using TSMC um CMOS technology and simulated using the BSIM3v3 model with level 49 technology file in Star HSPICE. The threshold voltage of the pmos and nmos transistor is approximately 0.33V and 0.35V, respectively. Environment temperature has been set to 27 C. We use the simulation set up suggested in [18] to evaluate the proposed circuits.
A. Individual Test Bench To simulate real environment, we use input buffers for both inputs and outputs. The transistor sizes of these buffers are chosen such that there is sufficient signal distortion expected in an actual circuit [9]. Power consumption is measured for the buffers and 3input XOR/XNOR cells. Delay is measured from the moment the inputs are applied to the input buffers with the cell, until the XOR and XNOR signals through the output buffers is produced. B. Transistor Sizing To provide a fair evaluation, the circuits are simulated to achieve minimum PDP using Simple Exact Algorithm of transistor sizing [19] for different voltages (0.8V1.6V VDD). Optimization of the transistor sizing is carried out for the circuits in the test bench. V. SIMULATION RESULTS Performance of the balanced 3input XORXNOR circuits are compared with each other. These proposed circuits have been chosen for comparison, as they exploit some of the best cells and correctionoptimization mechanisms in [10] and [11]. In addition, their critical path contains only two transistors. The operating frequency is set at 100 MHz. The values of delay obtained for considered values of VDD (0.81.6 V) for the circuits are shown in Fig. 8 and Table II. to make the comparison easer, the last column shows the average values of the delays. It is apparent that amongst the existing conventional and proposed circuits has the smallest delays. and have the second and the third position. The circuit TF follows the and circuits. However, the classes C and B are better as the viewpoint of delay. The average power dissipation is evaluated under different supply voltages and summarized in Fig. 8 and Table II. The last column of Table II tabulates the average values of the averages power of the circuits. Among the circuits, NEWHPSC, NEW14T, Hybrid, TF and XO1 have the lowest power dissipation. Among the proposed circuits, class A because of low number of transistors in their design and class C because of using bootstrap technique, which is save voltage in internal node, have low power dissipation. The PDP is a quantitative measure of the efficiency of the tradeoff between power dissipation and speed, and is particularly important when lowpower operation is needed. The value of PDP is evaluated under different supply voltages, summarized Fig. 8 and Table II. Among the circuits, and have the lowest PDP respectively. The PDP of is lesser than that of for lower voltages but the trend reverses for higher voltages. Therefore, from energy point of view, is a better choice. In the and, BC2 integrates with combinational mechanisms such as pull up/down networks with feedback networks or bootstrap techniques. Hybrid and NEWHPSC have the highest PDP amongst the conventional circuits. In this case, the proposed circuits in classes B and C display the better PDP characteristics for varying supply voltages. To make the comparison easier, ascending order of PDP is in Fig. 7, clearly,, TF, are the best circuits respectively. After investigation, it can be realized that from energy point of view the BC1 after the BC2 exhibits better results. TABLE II. DELAY, POWER AND PDP COMPARISION OF THE BALANCED 3INPUT XOR/XNOR CIRCUITS PDP(fJ) 0.8 1 1.2 1.4 1.6 AVERAGE XO1 0.55 0.58 0.67 0.78 0.91 0.70 0.48 0.51 0.59 0.68 0.84 0.62 0.44 0.45 0.55 0.67 0.77 0.57 0.36 0.37 0.45 0.53 0.65 0.47 0.60 0.55 0.58 0.68 0.83 0.65 0.48 0.43 0.44 0.50 0.64 0.50 HTBRID 0.47 0.48 0.60 0.71 0.84 0.62 New14T 0.78 0.51 0.47 0.46 0.66 0.58 NEWHPSC 0.63 0.63 0.70 0.80 1.01 0.76 TF 0.42 0.41 0.48 0.59 0.70 0.52 Td(nS) 0.8 1 1.2 1.4 1.6 AVERAGE XO1 0.53 0.34 0.25 0.21 0.18 0.30 0.46 0.30 0.22 0.17 0.15 0.26 0.40 0.25 0.19 0.16 0.14 0.23 0.34 0.21 0.16 0.11 0.19 0.55 0.31 0.21 0.17 0.16 0.28 0.44 0.24 0.16 0.11 0.22 HTBRID 0.48 0.30 0.27 0.21 0.18 0.29 NEW14T 0.82 0.35 0.21 0.14 0.14 0.33 NEWHPSC 0.70 0.42 0.30 0.24 0.21 0.38 TF 0.42 0.25 0.20 0.16 0.14 0.23 Power(uW) 0.8 1 1.2 1.4 1.6 AVERAGE XO1 1.04 1.70 2.65 3.80 5.13 2.86 1.03 1.72 2.68 3.89 5.57 2.98 1.09 1.78 2.86 4.08 5.45 3.05 1.07 1.79 2.86 4.16 5.98 3.17 1.10 1.77 2.75 3.96 5.28 2.97 1.09 1.78 2.72 3.97 5.77 3.07 HTBRID 0.98 1.62 2.32 3.41 4.73 2.61 NEW 14T 0.96 1.47 2.26 3.31 5.01 2.60 NEWHPSC 0.90 1.49 2.31 3.36 4.73 2.56 TF 0.98 1.69 2.44 3.72 5.12 2.79 Thus, these simulation results confirm that pull up/down networks are better to address high impedance outputs also bootstrap technique and feedback are better to produce full swing output. PDP(fJ) 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 0.4 Ascending order of PDP for the circuits Circuits Figure 7. Ascending order of the circuits at the testbench
Actually, if we use fullswing producing techniques to fix the high impedance problem we have to rely on high drive transistors. Exploiting powerful transistors, however, can interfere with the basic cell work. For example, using powerful feedback transistors in the basic cells increases power and delay at the time of output change. Pull up/down networks have the advantage of not interfering with basic cells. Circuits using bootstrap technique that exploit blocking voltage in the internal nodes for gate voltage shifting in the basic cell transistors are also good candidates for low power modules. In addition, these circuits do not come with short circuit at the time of output switching. As a result, alternative techniques are suggested to remove high impedance and produce fullswing outputs. 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 7 6 5 4 3 2 1 0 0 Powerdelay Product (fj) XO1 HTBRID New14T NEWHPSC TF 0.8 1 1.2 1.4 1.6 Supply Voltage (V) Worst case delay (ns) XO1 HTBRID NEWHPSC 0.8 1 1.2 1.4 1.6 Supply Voltage (V) Average power consumption (uw) XO1 HTBRID NEW 14T NEWHPSC TF Figure 8. Simulation results of circuits. NEW14T TF 0.8 1 1.2 1.4 1.6 Supply Voltage (V) Figure 9. Waveform snapshots of the circuits and in 1.2 V (100 MHz) Without test bench output buffers. Fig. 9 shows the output waveforms of, before the insertion of test bench buffers at 1.2 V. outputs in some transitions have voltage more than supply voltage that is because of ability of bootstrap in saving voltage. For example, XOR3 output in time 250nS and XNOR3 output in time 110nS has voltage 1.33v and 1.35v respectively. As mentioned, by optimizing the transistor sizes of the circuits, it is possible to achieve minimum PDP. So iterative process of SEA algorithm for all the circuits in all ranges (0.81.6v) was carried out, as well as the optimized transistor widths for and at 1.2V are listed in Table III. In all circuits, the buffer sizings are 0.39u and 0.65u for NMOSs, 0.65u, and 1.56u for PMOSs respectively. VI. CONCLUSION Using cell design methodology and correctionoptimization mechanisms rely on hybridcmos design style, it is conceived many new 3input XOR/XNOR circuits. For example, The XO1 to is presented in the paper that targets low PDP. The proposed circuits have high performance, full swing and balanced outputs and they are in optimum size of transistors. They perform well with supply voltage scaling and their critical path contains only two transistors. Simulation results show that the proposed circuits exhibit better performances compared to previously suggested circuits. Finally, we also classify the basic cells and the mechanisms based on performances and applications. REFERENCES [1] M.H. Moaiyeri, R. Faghih Mirzaee, K. Navi, T. Nikoubin and O. kavehei, Novel direct designs for 3input XOR function for lowpower and highspeed applications, International Journal of Electronics, 97: 6, 647662, 18 March 2010. [2] H.W. Kim and S. Lee, Design and Implementation of a Private and Public Key Crypto Processor and its Application to a Security System, IEEE Transactions on Consumer Electronics, 50, 214 224, 2004. [3] P.M. Lee, C.H. Hsu, and Y.H. Hung, Novel 10T Full Adders Realized by GDI Structure, in Proceedings of 2007 International Symposium Integrated Circuits, pp. 115 118, 2007. [4] M.H. Moaiyeri, R. Faghih Mirzaee and K. Navi, Two New Low Power and HighPerformance Full Adders, Journal of Computers, 4, 119 126, 2009. [5] S. Timarchi and K. Navi, Arithmetic Circuits of Redundant SUT RNS, IEEE Transactions on Instrumentation and Measurement, 58, 2959 2968, 2009.
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