Enhancement-mode AlGaN/GaN HEMTs on silicon substrate

phys. stat. sol. (c) 3, No. 6, 368 37 (6) / DOI 1.1/pssc.565119 Enhancement-mode AlGaN/GaN HEMTs on silicon substrate Shuo Jia, Yong Cai, Deliang Wang, Baoshun Zhang, Kei May Lau, and Kevin J. Chen * Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong Received 5 July 5, revised 1 February 6, accepted 4 April 6 Published online 19 May 6 PACS 73.4.Kp, 81.5.Ea, 85.3.Tv High performance enhancement-mode AlGaN/GaN HEMTs (E-HEMTs) were demonstrated with samples grown on low-cost silicon substrate for the first time. The fabrication process is based on fluoride-based plasma treatment of the gate region and post-gate annealing at 45 C. The fabricated E-HEMTs have nearly the same peak transconductance (G m ) and cut-off frequencies as the conventional depletion-mode HEMTs (D-HEMTs) fabricated on the same wafer, suggesting little mobility degradation caused by the plasma treatment. 6 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim 1 Introduction Most of the development in GaN-based HEMT technology has been focused on depletion-mode Al- GaN/GaN HEMTs (D-HEMT) [1 4] that feature negative gate threshold voltage. Enhancement-mode HEMT (E-HEMT) devices, which exhibit a positive threshold voltage, provide extra benefits in many applications. For RF/microwave applications, the E-HEMTs enable the elimination of the negative polarity supply voltage, leading to reduced circuit complexity, size and cost. For digital applications, E- HEMTs integrated with D-HEMTs can be used in direct coupled FET logic (DCFL) circuits that have much simpler circuit configurations compared to those implemented by D-HEMT based technologies. However, the fabrication of E-HEMTs in III-nitride materials is difficult due to the large amount of polarization charges in AlGaN/GaN hetero-structures. To date, most E-HEMTs have been fabricated by reducing the gate-to-channel distance via thinner barrier layer growth [5] or recess etch [6, 7]. The approach using thinner barrier features large access resistance that degrades the transconductance. The recessed-gate approach requires additional pre-gate annealing and additional gate-level photolithography, which implies that the gate recess and gate metallization are not self-aligned. A novel approach is proposed by our group recently on samples grown on sapphire substrate. The technique employs selfaligned fluoride-based plasma treatment of the gate region and post-gate annealing [8], maintaining low access resistance. Confirmed by second ion mass spectroscopy (SIMS) measurement, the plasma treatment can effectively incorporate immobile negatively charged fluorine ions into AlGaN barrier, raise the conduction band, and shift the threshold voltage to a positive value. For high volume applications, such as digital integrated circuits, it is necessary to demonstrate E-HEMT on silicon substrate that offers benefits of large-size and low-cost. In this paper, we demonstrate the first AlGaN/GaN E-HEMTs on silicon substrates. Crack-free Al- GaN/GaN HEMT structures were grown on silicon substrates. Using fluoride-based plasma treatment, D-HEMTs with a threshold voltage of -3.3 V are converted to E-HEMTs with a.5 V threshold voltage, allowing monolithic integration of E-HEMT and D-HEMT for digital applications. * Corresponding author: e-mail: eekjchen@ust.hk, Phone: +85-358-8969, Fax: +85-358-1485 6 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

phys. stat. sol. (c) 3, No. 6 (6) 369 Material growth and device fabrication The heterostructure layers employed in this study were epitaxially grown by metalorganic chemical vapor deposition (MOCVD) on a -inch (111) silicon substrate. It consists of a 3 nm high temperature AlN nucleation layer grown at 115 C, followed by a 1 µm thick GaN buffer, which has a 1 nm thick low-temperature AlN interlayer grown at 76 C inserted in the middle. Then the Al.3 Ga.7 N barrier is grown, which consists of a 3-nm undoped spacer, a 15-nm doped (Si doped, 5x1 18 cm 3 ) carrier supply layer, and a -nm undoped cap layer. Owing to the optimized interlayer, the grown sample is crack free. For device processing, both and HEMTs are implemented on the same wafer. Device mesa was formed using Cl /He plasma dry etching in an STS ICP-RIE system followed by the source/drain ohmic contact formation with Ti/Al/Ni/Au annealed at 85 C for 3 seconds. The ohmic contact resistance was typically measured to be.7 Ω-mm by TLM method. Ni/Au e-beam evaporation and lift-off were carried out subsequently to form the gate electrodes. E-HEMTs underwent identical processing as D-HMETs, except for an additional fluoride-based treatment before the gate metal deposition. This treatment employs CF 4 plasma in a RIE system at a power 17 W for 1 seconds after gate regions were open by photolithography. D-HEMTs are protected by photoresist during treatment and not affected. After the gate metal deposition, the sample was annealed at 45 C in N ambient for 1 minutes to recover the plasma induced damage. Experiment results show that the pinch-off voltage shift will increase with both the plasma power and treatment time. However, higher energy treatment will cause un-recoverable damage and degradation of mobility. This RTA temperature was chosen to be 45 C out of consideration of maintaining good gate Schottky contact and source/drain ohmic contacts. All the D/E mode devices stated in this article have 1 µm gate length and 1 µm gate width with a source-gate spacing of L SG = 1 µm and a gate-drain spacing of L GD = µm. 3 Device characteristics and discussion The transfer characteristics of both and HEMTs fabricated on the same wafer are plotted in Fig. 1(a). Defining the threshold voltage (V th ) as the gate bias intercept of the linear extrapolation of drain current at the point of peak transconductance (g m ), the V th of D-HEMTs is -3.3 V, while for E- HEMTs it is.5 V. The peak G m was 18 ms/mm for device and 167 ms/mm for device. The small difference may come from device variation or un-recovered damages. The shift of V th is attributed to the incorporation of negative charged fluorine ions into the AlGaN barrier during the plasma treatment. These immobile charges effectively deplete the channel electrons and convert the HEMT into. Owing to the self-aligned nature of the plasma treatment, the access region between the source and gate remains to be and low on-resistance (R on ) can be maintained, a key feature for achieving high-performance E-HEMT. Figure 1(b) shows the output characteristics of devices (before and after annealing). Comparison of source-drain current-voltage curves of device before and I DS (ma/mm) 1 1 8 6 15 1 4 5 V V th =-3.3 V DS =1V V th =.5 V -7-6 -5-4 -3 - -1 1 3 4 V GS G m (ms/mm) I DS (ma/mm) 35 3 5 15 1 5 E-HEMT V GS : From to.4 V, step by.3 V Before RTA After RTA 4 6 8 1 V DS Fig. 1 DC characteristics. (a) Transfer curves measured on the D/E mode device. (b) Output curves of device before and after RTA at 45 C. www.pss-c.com 6 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

37 Shuo Jia et al.: Enhancement-mode AlGaN/GaN HEMTs on silicon substrate after annealing suggests that that annealing at 45 C for 1 minutes is essential to recovering the damage induced during the plasma treatment. No shift of threshold voltage was observed after the annealing. Among 35 HEMTs tested across a 1 cm by 1 cm area, the standard deviation of the threshold voltage is about.1 V. It should be pointed out that the device can be biased to higher gate voltage up to.5 V, which in turn provides a larger gate voltage swing and thereby improves the dynamic range for the input. To study this phenomenon we compare the gate current of D/E HEMTs with both source and drain grounded. As can be seen in Fig., the device showed a reduction of both forward and reverse gate currents, especially at V GS larger than 1 V. Corresponding to the same gate leakage current in D-HEMT at V GS = 1.5 V, the E-HEMT can be biased at.5 V. We believe the mechanism for gate current is a combination of thermal emission and tunneling through the AlGaN barrier. The incorporation of negative charge in the AlGaN barrier can effectively raise the conduction band energy of the barrier, resulting in higher potential barrier for both thermal emission and tunneling. Consequently, the gate current is suppressed. I g (A/mm) 1 1-1 1-1 -3 1-4 1-5 1-6 1 1 Fig. Gate Schottky diode characteristics of the D-HEMTs and E-HEMTs with both source and drain grounded. 1-7 -16-14 -1-1 -8-6 -4-4 V g The on-wafer small-signal characterization was carried out by S-parameter measurements with an Agilent 87ES Network Analyzer and a microwave probe station. The devices were measured at the bias condition exhibiting the peak G m as shown in Fig. 3. A current gain cutoff frequency (f T ) of 7.5 GHz and a maximum stable gain/maximum available gain (MSG/MAG) cutoff frequency (f max ) of 16.9 GHz were obtained from E-HEMTs, which are close to the D-HEMTs, whose f T and f max were 7.9 GHz and 18.7 GHz, respectively. These results suggest that a large shift in the threshold voltage can be achieved without degradation of transconductance and RF performance through the treatment and post-gate annealing technique. Gain (db) 4 3 Current gain of HEMT MAG/MSG of HEMT Current gain of HEMT MAG/MSG of HEMT Fig. 3 Short-circuit current gain (H1) and maximum stable gain/maximum available gain (MSG/MAG) of the typical 1 µm x 1 µm D/E-HEMTs measured at gate bias displaying maximum transconductance and VDS = 1 V. 1 1E8 1E9 1E1 Frequency (GHz) 4 Simulations and discussion In order to investigate the mechanisms of the threshold voltage shift by CF 4 plasma treatment, second ion mass spectrum (SIMS) measurements were carried out on accompanying samples. Confirmed by SIMS 6 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim www.pss-c.com

phys. stat. sol. (c) 3, No. 6 (6) 371 measurement [8], the plasma treatment can effectively incorporate negatively charged fluorine ions into AlGaN barrier, raise the potential in conduction band, and shift the threshold voltage to a positive value. To confirm this explanation, we calculate the conduction band profile by applying Poisson s equation and Fermi-Dirac statistics. Parameters used for this calculation are the same as those listed in [9]. Based on SIMS result, we assume a Gaussian distribution of the negative charged fluorine ions as follows: x N( x) = NP *exp(- ) (1) N P is the peak concentration at AlGaN surface and equals to x1 19 cm 3, and a standard deviation of 7 nm is assumed. N(x) is the negative charge concentration as the function of vertical depth. This profile is in good agreement with the measured result. We adopted an effective polarization charge density of 8x1 1 cm and a Schottky barrier height of φ B =.6 V in this simulation to match experimentally observed valued of pinch-off voltage. Figure 4 shows the conduction band structure along a vertical cross section under the gate. The solid line and dashed line represent the conduction band of (without fluorine ions) and (with fluorine ions) device respectively, and the dotted line shows the position of the Fermi level. As shown in Fig. 4 (a), the negative charges are incorporated into the AlGaN layer after plasma treatment, and the DEG in the channel of device are depleted to maintain charge neutrality. In modeling the band diagram, the conduction band at the surface is pinned by the schottky barrier, and the incorporated negative charges can effectively raise the conduction band, to the extent that the Fermi level is below the conduction minimum at AlGaN/GaN interface. Figure 4 (b) shows the band diagram with positive gate bias. It is generally believed that the mechanism for gate current is a combination of thermal emission and tunneling through the AlGaN barrier [1, 11]. After treatment, the conduction band of AlGaN is raised, resulting in effectively higher and thicker barrier for channel electrons to tunnel through the AlGaN layer, and the forward gate current is suppressed. Figure 4 (c) shows the band profile with -5 V gate bias. Similarly, the probability for electrons tunneling through the barrier layer is reduced, and consequently the reverse leakage current is decreased. This simulation result is in agreement with the measured gate currents, as shown in Fig... 1.5 1..5. Gate bias: V -.5 4 6 8 1.6.4.. -. -.4 -.6 -.8 Gate bias: +1 V -1. 4 6 8 1 8 6 4 Gate bias: -5 V 5 1 15 5 3 Fig. 4 Simulated conduction band edge profiles with (a) zero gate bias, (b) gate bias of +1 V, and (c) gate bias of - 5 V of AlGaN/GaN heterostructures. Solid lines represent device and dashed lines represent device with plasma treatment. 5 Conclusions We demonstrate, for the first time, both depletion-mode and enhancement-mode AlGaN/GaN HEMTs fabricated on the same sample grown on silicon substrate. This technique is based on a combination of self-aligned plasma treatment of the gate region and a post-gate annealing process. The fabricated E- HEMTs device exhibits a threshold voltage above zero with nearly no degradation of transcondcutance and RF performance. Meanwhile the gate leakage current in the HEMT is suppressed, allowing larger input voltage swing. These results are attractive for various applications requiring low-cost D/Emode HEMTs integration. www.pss-c.com 6 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

37 Shuo Jia et al.: Enhancement-mode AlGaN/GaN HEMTs on silicon substrate Acknowledgements This work is partially supported by the Research Grant Council of Hong Kong Government under CERG grant HKUST6317/4E, HKUST615/3E and 61185. References [1] V. Kumar, W. Lu, R. Schwindt, A. Kuliev, G. Simin, J. Yang, M. A. Khan, and I. Adesida, IEEE Electron Device Lett. 3, 455 (). [] W. Saito, Y. Takada, M. Kuraguchi, K. Tsuda, I. Omura, T. Ogura, and H. Ohashi, IEEE Trans. Electron Devices 5, 58 (3). [3] Y. F. Wu, A. Saxler, M. Moore, R. P. Smith, S. Sheppard, P. M. Chavarkar, T. Wisleder, U. K. Mishra, and P. Parikh, IEEE Electron Device Lett. 5, 117 (4). [4] J. W. Johnson, E. L. Piner, A. Vescan, R. Therrien, P. Rajagopal, J. C. Roberts, J. D. Brown, S. Singhal, and K. J. Linthicum, IEEE Electron Device Lett. 5, 459 (4). [5] M. A. Khan, Q. Chen, C. J. Sun, J. W. Yang, M. Blasingame, M. S. Shur, and H. Park, Appl. Phys. Lett. 68, 514 (1996). [6] J. S. Moon, D. Wang, T. Hussain, M. Mocovic, P. Deelman, M. Hu, M. Antcliffe, C. Ngo, P. Hashimoto, and L. McCray, Dig. 6th Device Research Conf., Santa Barbara, CA, USA,, pp. 3 5. [7] V. Kumar, A. Kuliev, T. Tanaka, Y. Otoki, and I. Adesida, Electron. Lett. 39, 1758 (3). [8] Y. Cai, Y. G. Zhou, K. J. Chen, and K. M. Lau, IEEE Electron Device Lett. 6, 435 (5). [9] R. M. Chu, Y. D. Zheng, Y. G. Zhou, S. L. Gu, B. Shen, P. Han, R. Zhang, R. L. Jiang, and Y. Shi, Appl. Phys. A 77, 669 (3). [1] L. S. Yu, Q. Z. Liu, Q. J. Qiao, S. S. Lau, and J. Redwing, J. Appl. Phys. 78, 99 (1998). [11] J. C. Carrano, T. Li, P. A. Grudowski, C. J. Eiting, R. D. Dupuis, and J. C. Campbell, Appl. Phys. Lett. 7, 544, (1998). 6 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim www.pss-c.com