Aalborg Universitet. Published in: I E E E Journal of Emerging and Selected Topics in Power Electronics. Publication date: 2018

Aalborg Universie High Volage Gain Quasi-SEPIC DC-DC Converer Siwakoi, Yam Prasad; Mosaan, Ali; Abdelhakim, Ahmed; Davari, Pooya; Khan, Noman Habib; Li, Li; Blaabjerg, Frede Published in: I E E E Journal of Emerging and Seleced Topics in Power Elecronics Publicaion dae: 2018 Documen Version Acceped auhor manuscrip, peer reviewed version Link o publicaion from Aalborg Universiy Ciaion for published version (APA): Siwakoi, Y. P., Mosaan, A., Abdelhakim, A., Davari, P., Khan, N. H., Li, L., & Blaabjerg, F. (Acceped/In press). High Volage Gain Quasi-SEPIC DC-DC Converer. I E E E Journal of Emerging and Seleced Topics in Power Elecronics. General righs Copyrigh and moral righs for he publicaions made accessible in he public poral are reained by he auhors and/or oher copyrigh owners and i is a condiion of accessing publicaions ha users recognise and abide by he legal requiremens associaed wih hese righs.? Users may download and prin one copy of any publicaion from he public poral for he purpose of privae sudy or research.? You may no furher disribue he maerial or use i for any profi-making aciviy or commercial gain? You may freely disribue he URL idenifying he publicaion in he public poral? Take down policy If you believe ha his documen breaches copyrigh please conac us a vbn@aub.aau.dk providing deails, and we will remove access o he work immediaely and invesigae your claim. Downloaded from vbn.aau.dk on: okober 01, 2018

High Volage Gain Quasi-SEPIC DC-DC Converer Y. P. Siwakoi, Member, IEEE, A. Mosaan, A. Abdelhakim, Suden Member, IEEE, P. Davari, Member IEEE, M. Solani, Senior Member, IEEE, Md N. H. Khan, Suden Member, IEEE, L. Li, Senior Member, IEEE, F. Blaabjerg, Fellow, IEEE Auhors Conac Informaion 1) Dr. Yam P. SIWAKOTI (Corresponding Auhor) Mailing Address: Faculy of Engineering and Informaion Technology, Universiy of Technology Sydney, AUSTRALIA. E-mail: yam.siwakoi@us.edu.au 2) Mr. Ali Mosaan, Iranian Cenral Oil Field Company (I.C.O.F.C), Tehran, IRAN. E-mail: ali_8457@yahoo.com 3) Mr. Ahmed Abdelhakim, Universiy of Padova, Vicenza, ITALY. E-mail: ahmed.a.abdelrazek@ieee.org 4) Dr. Pooya Davari, Aalborg Universiy, Aalborg, DENMARK. E-mail: pda@e.aau.dk 5) Dr. Mohsen Solani, Aalborg Universiy, Esbjerg, DENMARK. E-mail: sms@e.aau.dk 6) Mr. Md Noman Habib Khan, Universiy of Technology Sydney, AUSTRALIA. E-mail: MdNomanHabib.Khan@suden.us.edu.au 7) Dr. Li Li, Universiy of Technology Sydney, AUSTRALIA. E-mail: li.li@us.edu.au 8) Dr. Frede BLAABJERG, Aalborg Universiy, Aalborg, DENMARK. E-mail: fbl@e.aau.dk Absrac This paper proposes a modified coupled-inducor SEPIC dc-dc converer for high volage gain (2 < G < 10) applicaions. I uilizes he same componens as he convenional SEPIC converer wih an addiional diode. The volage sress on he swich is minimal, which helps he designer o selec a low volage and low RDS-on MOSFET, resuling in a reducion of cos, conducion and urn ON losses of he swich. Compared o equivalen opologies wih similar volage gain expression, he proposed opology uses lower componen-coun o achieve he same or even higher volage gain. This helps o design a very compac and lighweigh converer wih higher power densiy and reliabiliy. Operaing performance, seady-sae analysis and mahemaical derivaions of he proposed dc-dc converer have been demonsraed in he paper. Moreover, exension of he circui for higher gain (G > 10) applicaion is also inroduced and discussed. Finally, he main feaures of he proposed converer have been verified hrough simulaion and experimenal resuls of a 400 W laboraory prooype. The efficiency is almos fla over a wide range of load wih he highes measured efficiency of 96.2%, and he full-load efficiency is 95.2% a a volage gain of 10. Index Terms Boos converer, coupled-inducor, dc-dc converer, flyback ransformer, SEPIC converer, Swiched- Mode Power Supply (SMPS)

I. INTRODUCTION High conversion gain dc-dc power converers have recenly seen an increased demand in variey of power elecronics applicaions. In fac, he main reasons behind his increased aenion have hree folds. Firsly, fas deploymen of Renewable Energy (RE) based power sysems has inensified he need for high conversion gain power converers. This is due o he low volage generaion inheren in mos RE sources such as Phoovolaic (PV) modules and fuelcells, where sepping up he low inpu volage (e.g., 20 V - 40 V) o higher volage levels (e.g., 200 V - 400 V) is required in order o have a properly funcion grid-forming or grid-feeding converer [1], [2]. Secondly, prevalence of applicaions demanding higher volage levels for beer performance, from few hundreds of Vols such as for Ligh Emiing Diode (LED) in lighning [3] up o few kilovols in pulsed power applicaions [4]. Lasly, one of he mos relevan is he possibiliy of disribuing elecrical energy more efficienly a higher dc volage levels (e.g., 380 V- 400 V or even higher). This is he case in applicaions such as elecommunicaion and dc power sysems where elecrical energy can be ransferred wih higher efficiency, reliabiliy and power qualiy [5], [6]. Convenionally, he boos and buck-boos opologies can be employed in order o sep-up he oupu volage. However, pracically achieving conversion gains of beyond six due o presence of parasiic elemens is no feasible [2]. Moreover, operaing a high duy cycles compromise he boos converer efficiency as small urn-off imes which may incline Elecromagneic Inerference (EMI) and ripple curren levels, indicaing a requiremen for larger magneic componens [2], [7]. Anoher derivaion of a buck-boos opology suiable for high volage applicaions is he flyback converer [4], [8], [9]. Alhough his opology is well employed for high volage applicaions wih low pars coun, i is only suiable for very low power levels (i.e., < 300 W). This is due o he high dc magneizaion curren requiremen of is flyback ransformer, which increases he size of he ransformer and consequenly he losses for higher power levels under coninuous conducion mode operaion [8]. From his sandpoin, many research effors have been devoed owards developing high volage gain power converers wihou imposing exreme duy raio. In general, he demanded performance can be obained hrough uilizing coupled-inducor, swiched inducors and swiched capacior cells [7], [10]-[16] and/or employing muli-cell configuraions [4], [17]-[21]. All hese aemps are made in order o overcome he exising echnological limis (i.e., power swich breakdown volage and limied power raings) and o reach he required oupu volage level wih minimum duy raio (i.e., obaining beer efficiency). However, in many pracical siuaions, in order o obain he required volage gain and reduce volage sress across he power swich many swiched-cells are ypically required. Furhermore, using an impedance nework is also considered as anoher opological varian. The impedance nework based power converers. known as Z-source, is iniially proposed for dc-ac inverer operaion [22], bu i can be modified o operae as a high volage gain dc-dc converer [23]. Recenly, wih he aim of reducing sar-up inrush

curren and improving he volage gain of convenional Z-source converer, a variey of modified impedance neworks have been inroduced. These modificaions can be summarized as swiched inducor, exended boos, swiched inducor quasi Z-source and enhanced boos [24]-[29].While using he aforemenioned opologies a high volage gain wih small duy cycle (D) is achievable, bu he demeris of he aforemenioned opologies are high pars couns (i.e., diodes, inducors and capaciors) and paricularly he conducion of mos diodes in (1-D) of he swiching period, which lead o high power loss and low efficiency. In spie of opological improvemens, connecing wo or more power converers in o muli-cell configuraions is an alernaive way o achieve a high conversion raio. This can be obained by series/parallel connecion of power converer unis [4], [9], cascaded cells [18]-[20] or mulilevel approach [21]. Wih no doub, muli-cell connecion of power converers is an effecive way o mach he required power raing, volage gain and reduce volage sresses across he power swiches, bu high componen coun and lower efficiency may limi heir performance. Thereby, i is preferable o firs maximize he converer performance a he opology level before applying muli-cell connecion. I is worh noing ha obaining high volage gain, high efficiency and high power densiy a he same ime are conradicing arges and a compromise is required o mach specific applicaion requiremens. As a resul designing a power converer wih minimum number of componens is always desirable. Low pars coun can be a good design facor as i may lead o a cos-effecive, simple, compac and efficien power converer. Among aforemenioned echniques, using coupled inducor is an effecive echnique o increase he volage gain while avoiding high pars coun [30], [31]. The main concep in his approach is o obain he desirable volage gain by increasing he coupled inducors urns raio wihou including more componens o he power converer. Therefore, he power loss may be lowered and consequenly he efficiency can be improved. The coupled inducor echnique associaed wih he SEPIC opology is inroduced in [32]-[34]. Oher varians of his converer wih higher volage gain raio are presened in [35]-[39]. Generally, wo main drawbacks can be idenified in he inroduced mehods. Firsly, using wo magneic elemens [32]-[37] and necessiy of including exra diodes and capaciors cells o furher exend he volage raio significanly impair he power densiy. Secondly, in order o miigae he adverse effec of coupled-inducor leakage inducance, a snubber circui is mandaory [40]. The presence of snubber circui impose addiional losses on he power converer. However, wih suiable coupled-inducor design i is possible o minimize he leakage inducance and consequenly he snubber circui, which in reurn improves he sysem efficiency. In [41]- [42], high gain DC-DC converers, using aped inducor echnique are inroduced where heir operaions are very similar o converers using coupled inducor echnique. However, wihou minimizing he leakage inducance effecs and wihou using he low power loss snubber circui, he volage spike across he power swich is high and he efficiency is degraded. Sep-up curren-fed converers [43]-[45] wih low inpu curren ripple are appropriae soluions

in renewable energy applicaions, paricularly in fuel cell sysems. High efficiency is achieved in hese converers using sof swiching echniques. However, heir complicaed srucures and using more han one acive power swich make heir conroller sysem more complicaed. From he above discussions, he presen work focuses on coupled-inducor mehod as a suiable candidae o obain high volage wih low power losses in low o medium power applicaions. The proposed mehod is based on he SEPIC dc-dc converer opology. Here using a coupled-inducor, less number of componens are employed comparing wih prior-ar mehods. The volage sress across he acive power swich is minimized, which highlighs he possibiliy of uilizing low volage power swiches (i.e., low swiching losses) wih low urn-on resisance (i.e., low conducion losses), which lead o an efficien and cos-effecive design. Moreover, by improving he magneic coupling he leakage inducance effec is minimized. The principle of operaion, heoreical analysis of he proposed converer are invesigaed in comparison wih is similar counerpars. The repored analysis is validaed by key experimenal resuls of a 400 W prooype. This paper is improved version of he conference paper [46]. In [46], his converer was inroduced for very low power (5 W) applicaions as a fron end DC-DC converer for piezoelecric sysems and here are he following improvemens for he curren work: a) This converer is inroduced as a high sep-up and high efficiency converer in renewable energy applicaion wih nominal inpu volage 40 V and oupu volage 400 V as well as having considerable higher power (400 W). b) In addiion o CCM mode, he converer is analyzed in he boundary conducion mode (BCM) and disconinuous conducion mode (DCM). Moreover, a design guideline in order o selec he appropriae componens value is added o his paper. c) A derivaive converer wih higher volage gain (secion IV) based on he proposed converer is also presened. d) In order o minimize he leakage inducance effecs and preven he volage spike across he power swich, an improved magneic coupling is designed and a RCD snubber circui wih low power loss is added in he experimenal prooype as well as an efficiency measuremen and loss disribuion. A peak efficiency of 96.2% confirms he effeciveness of his converer in renewable energy applicaions. This paper is srucured as follows: Secion II describes he proposed opology operaion principle and design guidelines under seady sae condiions. Analyzing he prior-ar mehods in comparison wih he proposed opology hrough highlighing key aspecs of heir performance are addressed in Secion III. Secion IV is dedicaed o furher

exend he proposed opology for higher volage gain raios. In Secion V, experimenal resuls are presened o subsaniae he effecive performance of he proposed mehod. Finally, conclusions are drawn in Secion VI. II. OPERATING PRINCIPLE AND STEADY STATE ANALYSIS OF THE QUASI-SEPIC DC-DC CONVERTER This secion sars firs by illusraing he operaing principle of he proposed converer in coninuous conducion mode (CCM). Then, is operaion in he disconinuous conducion mode (DCM) is inroduced, considering he criical case beween he CCM and he DCM, which is called he boundary conducion mode (BCM). Finally, i shows he design seps or guidelines of a 400 W converer. A. CCM Operaion Compared o he basic coupled-inducor SEPIC converer, as shown in Fig. 1(a), he proposed converer, which is shown in Fig. 1(b), uilizes he same number of componens wih an addiional diode. I is worh noing ha his srucure does no require an isolaed gae drive circuiry for he employed MOSFET, resuling in lower cos and volume. Furhermore, a capacior is conneced in series wih he ransformer secondary winding, prevening he flow of he dc curren in he ransformer and, hence, avoiding sauraion due o dc curren. 1:n 1:n C in C in N 1 N 2 D 1 N1 N 2 V ou C dc D 1 V ou PWM Q C ac C ou PWM Q D 2 C ou Fig. 1. Circui schemaic showing (a) radiional coupled-inducor SEPIC dc-dc converer and (b) proposed coupled-inducor quasi-sepic dcdc converer. 1:n 1:n C in C in Lm N 1 N 2 C dc D 1 V ou Lm N 1 N 2 C dc D 1 V ou PWM Q D 2 C ou PWM Q D 2 C ou (a) (b) Fig. 2. Equivalen circuis of he proposed converer in one swiching cycle (a) Mode 1 (Q ON), and (b) Mode 2 (Q OFF). In order o do furher analysis on he converer operaion, several assumpions are aken ino accoun as follows: 1) The MOSFET and he diodes are ideal, i.e. he ON resisances of he MOSFET and volage drop across he diodes are negleced;

2) All he employed capaciors are large enough, i.e. he volage ripples across hem are negligible; and 3) The leakage inducance of wo coupled inducors are negligible and hey are modeled as an ideal ransformer wih a urns raio of N 1:N 2 and a magneizing inducance of L m, parallel conneced o he primary winding. According o he prior ar assumpions, each swiching cycle is divided ino wo modes of operaion as shown in Fig. 2(a) and Fig. 2(b). The key waveforms in one swiching cycle in CCM are shown in Fig. 3. In Mode 1, as shown in Fig. 2(a), he power swich is urned ON, and he volage across L m is equal o he inpu volage. Moreover, D 1 is ON and D 2 is OFF during his mode, where C dc is delivering energy o he load, conneced across C ou. Hence, from Fig. 2(a) V Lm(mode1) = (1) Then, applying he KVL in secondary winding, he following equaion can be obained as: V O = V Cdc + nv dc Where n = n 2 n 1 (2) Mode 2 sars when he power swich is urned OFF, in which D 2 is ON and providing a curren pah for he magneizing Vgs VQ iq VD1 id1 VD2 id2 ilm inducance curren. During his mode, D 1 is OFF and he oupu capacior delivers he required energy o he load. Thus, applying KVL again, he volage across L m is given by V Lm(mode2) = V dc 1+n (3) VO DT ()T Fig. 3. Key waveforms of he proposed converer in coninuous conducion mode. Due o he volage-second balance of L m, he following expression can be obained: Therefore, he volage across C dc is obained as D + ()( V Cdc ) 1+n Subsiuing (5) ino (2), he oupu volage is given by = 0 (4) V Cdc = (1+nD) (5)

Using (6), he volage gain of he proposed converer is V O = 1+n (6) G = 1+n (7) Hence, i is obvious ha he oupu volage is a funcion of he ransformer urns raio (n) or he duy cycle (D). The volage sress across he power swich is obained by applying KVL in Fig. 2(b) as follows: V S = V Lm(mode2) (8) Using (3) and (5), we have V S = ( V C1 ) 1+n = (9) Comparing (6) and (9), i is clear ha volage sress on he power swich is always lower han oupu volage for any urns raio. The swiching loss can be obained as P S = C S f s V S 2 = C S f s ( )2 (10) Where, Cs is MOSFET drain-source inrinsic capacior, f s is he swiching frequency and V s is he volage sress across he power swich. From (10), i is obvious ha he power loss can be decreased n 2 imes compared o he convenional coupled inducor SEPIC converer. Moreover, he low volage power MOSFET has lower urn-on resisance ha can lead o lower conducion losses and consequenly gives a beer efficiency. Similarly, he R DS,on of he device increases wih he blocking volage capabiliy of he device. Hence, lower volage device as implemened in he circui has lower R DS,on, which consequenly have lower conducion loss. Hence, wih he reducion of he volage sress boh swiching and conducion losses are reuced. Similarly, he volage sress across D 1 and D 2 can be obained by V D1 = n (11) V D2 = V O = 1+n (12) The curren sress of he differen componens can be deermined using he charge balance of he capaciors. According o Fig. 2(b), he oupu capacior curren is equal o he oupu curren in Mode 2. Therefore, I Cou (Mode 2) = I O (13) Similarly, due o he charge balance in C ou, he following equaion can be obained: I Cou (Mode 1) = ()I O D (14) The average value of he curren in D 1 (<I D1>) is equal o oupu curren, i.e. Thus, he maximum curren in D 1 can be deermined by < I D1 >= I O (15)

I D1 = I o D (16) Using Fig. 2, he average values of he ransformer primary and secondary curren are equal o zero. Therefore, he average curren in D 2 (<I D2>) is given by The maximum curren in D 2 is given by < I D2 >= I O (17) I D2 = Moreover, from Fig. 2(a), he average value of he MOSFET curren (<I Q>) is given by I o. (18) < I Q >= < I Lm > n < I D1 > (19) The average value of he magneizing inducor curren is equal o he average inpu curren. Since he average value of he ransformer primary curren is zero, he following equaion can be obained: which resuls in Therefore, he maximum curren in he MOSFET can be calculaed by using < I Q >= < I in > n I o, (20) < I Q >= 1+Dn I o. (21) I S = 1+Dn D() I o. (22) B. BCM and DCM operaions The proposed converer goes o boundary conducion mode (BCM) when he magneizing inducor curren drops o zero exacly in he nex swiching cycle. The magneizing inducance curren and volage in his mode are shown in Fig. 4. This phenomenon occurs when he magneic inducance or swiching frequency values are small or he converer works under ligh load condiions. If he inducor curren goes o zero before he nex swiching cycle, he converer works in disconinuous conducion mode (DCM). In he following conex, he condiion under which he converer goes o he BCM is derived, and hen he volage gain of he converer under DCM is obained. From Fig. 4, he curren ripple across he magneic inducance is given by Also, he average value of he magneizing curren (<i Lm>) is i Lm = DT s L m. (23) < i Lm > = i Lm 2 = DT s 2L m. (24) The average curren value of he ransformer primary and secondary winding is equal o zero due o he series capacior (C dc) wih secondary winding. Thus, applying KCL resuls in < i Lm > =< i in >, (25)

V gs v Lm V dc 1 + n i Lm DT s L m DT s V dc ( DT L m (1 + n)l s ) m DT s 1-DT s Fig. 4. Magneizing inducance volage and curren in BCM. where,< i in > is he average value of he inpu curren. If all parasiic effecs are negleced he inpu power is equal o oupu power, i.e. Or in anoher way P o = P in. (26) v in i in = v o i o (27) The volage gain of he converer in he BCM can be obained using (6). Therefore, subsiuing (6) and (25) ino (27) can lead o where f s is he swiching frequency and i OB is he oupu curren under BCM. Therefore, he boundary oupu curren can be obained from D = (1+n) i 2L m f s OB, (28) Using he above equaion, he normalized boundary oupu curren is given by i OB = D()2 V O 2L m f s (1+n) 2. (29) i OB V O = D()2 2L mf s (1+n) 2, (30) Using (28), he minimum value of he magneizing inducor ha is required in order o operae he converer in CCM can be obained by L m D()2 V O 2f s i OB (1+n) 2 (31)

The converer goes o DCM if he magneizing inducance value is lower han (31) for a cerain load. The boundary load resisance and is normalized value can also be obained as in (32) and (33) respecively, where R OB = 2L mf(1+n) 2 D() 2, (32) R OB 2Lm f = (1+n)2 s D() 2. (33) The normalized oupu curren and he normalized oupu resisance are ploed in Fig. 5(a) and Fig. 5(b) respecively for n=1 and n=2. I is clear ha he CCM region can be exended wih increasing he coupled inducors urn raio. The maximum value of he boundary oupu curren can be obained from he derivaive of (29), ha occurs under D=1/3 and gives he maximum value of he boundary oupu curren as Normalized Boundry Oupu Curren 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 DCM for n=1 CCM for n=2 CCM n=1 n=2 i O(max) = V o 54L m f s (1+n) 2. (34) 50 DCM n=1 DCM CCM n=2 CCM 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Duy cycle (D) Duy cycle (D) (a) (b) Fig. 5. Normalized (a) load curren and (b) load resisance under n = 1, and n = 2. 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalized Boundry Load Resisance 300 250 200 150 100 DCM n=1 n=2 There are hree regions in DCM. Modes 1 and 2 are similar o Fig. 2(a) and Fig. 2(b) respecively, while Mode 3 is shown in Fig. 6. 1:n C in Lm N 1 N 2 C dc D 1 V ou PWM Q D 2 C ou Fig. 6. Mode 3 in Disconinuous Conducion Mode (DCM).

V gs v Lm V dc 1 + n i Lm DT s L m DT s V dc ( DT L m (1 + n)l s ) m DT s D 2 T s Fig. 7. Magneizing inducance volage and curren in DCM. In his mode, he swich and he wo diodes are urned OFF and he magneizing inducor curren fall o zero before he nex swiching cycle. The magneizing curren under DCM is shown in Fig. 7. Hence, he following equaions can be derived by using Fig. 7. i PK = DTs L m, (35) < i Lm > = i PK(D+D 2 ) 2 = D(D+D 2 ) 2L m f s, (36) As shown in Fig. 7, D 2T s is he ime aken by he inducor curren i Lm o fall o zero from is peak value (i.e. a he end of V gs ON). As discussed before, he average value of he magneizing inducor curren is equal o inpu curren, i.e. < i Lm > =< i in >. (37) Also, he oupu power is equal o he inpu power if all parasiic effecs are negleced i.e. P in = P O 2 D(D+D 2 ) 2L m f s = V 2 O. (38) R Due o he volage-second balance of he magneizing inducance, he following relaion can be obained: Subsiuing (2) ino (39) leads o D + D 2( V Cdc ) 1+n D 2 = = 0. (39) D(n+1) V O (n+1). (40) The relaionship beween D and he volage gain of he converer during he DCM can evenually be derived by subsiuing (40) ino (38) as follows: D = 2τM DCM (M DCM (n + 1)), (41)

Fig. 8. Volage gain versus duy raio a DCM operaion under various τ L values and n = 4. where he normalized inpu ime consan τ L is given by τ L = L RT s = Lf s R, (42) Where f s is he swiching frequency and R is he equivalen load resisance. Curves illusraing (41) are shown in Fig. 8 for differen τ L values during he DCM operaion. From (41), i is quie obvious ha he volage gain is load dependen during he DCM. Finally, he DCM is no recommended in general. C. Design guidelines The componen values in he proposed converer can be deermined considering he following specificaions: 1) inpu volage varies beween 30 V and 50 V and is nominal value is 40 V; 2) oupu volage is fixed o 400 V; 3) swiching frequency is se o be 100 KHz; 4) nominal oupu power equals 400 W, corresponding o I O=1 A; 5) converer works in CCM; 6) volage sress on power swich should be lower han 150 V, which is he raed value of he seleced MOSFET; and 7) Volage ripple across he capaciors should be lower han 1% of heir nominal values. Using (11), he volage sress across he swich can be deermined as V S = V 0 1+n (43) Using (43), in order o resric he volage sress across he swich o 80 V, n should be equal o or higher han 4.Therefore, in he experimenal prooype n=4 is seleced The minimum and maximum value of he duy cycle is deermined using (7) D min = 1 (1+n)max = 1 5 50 = 0.375 (44) V O 400

Also, he nominal value of he duy cycle is deermined as D=0.5 D max = 1 (1+n) min = 1 5 30 = 0.625 (45) V O 400 Using (31), in order o mainain he converer operaes in CCM in half load (I O=0.5 A) and maximum inpu volage, he minimum value of he magneizing inducance can be deermined as L m (min) 0.375 (1 0.375)2 400 2 100 10 3 25 0.5 = 23.43 μh (46) Finally, a coupled inducor wih n=4 and L m = 39 μh is uilized in he experimenal prooype. Moreover, he maximum value of he volage across D 1, obained from (11) is V D1 = n(max) The volage sress on D 2 is equal o he oupu volage ha is 400 V. = 4 40 = 320 V. (47) 1 0.5 The oupu capacior curren is equal o he oupu curren in Mode 2. Therefore, he volage ripple across his capacior can be deermined as ΔV Cou = ()I O C ou f (48) Therefore, C ou(min) = ( max)i O fδv Cou = (1 0.55) 1 = 1.125 μf (49) 100 10 3 4 As a resul, a 1 μf ceramic capacior is seleced in he experimenal prooype. A nominal inpu volage, he oupu volage ripple is slighly higher han 1% of he oupu volage value. However, he oupu volage ripple can be lower wih increasing he size of oupu capacior. C dc curren is equal o he D 1 curren during Mode 1. This capacior is discharged in Mode 1 and is volage is decreased. Therefore, he volage ripple is ΔV Cdc = DI D1 C dc f (50) Subsiuing (16) ino (50) gives ΔV Cou = I O C dc f (51) Tha deermines he minimum value of C dc as C dc (min) I O 1 = fδv Cdc(min) 100 10 3 2.4 A 4.4 μf, 400 V ceramic capacior is used in he experimenal prooype. Using (16) and (18) he maximum curren sress on D 1 and D 2 can be obained by I D1max = I D2max = = 4.17 μf (52) I o = 1 = 2.66 A (53) D min 0.375 I o min = 1 1 0.6255 = 2.66 A. (54) As a resul, power diode C3D03060 wih a DC blocking volage 600 V and coninuous forward curren a11 A a

T C=25 0 C is seleced for D 1 and D 2. The maximum curren sress on he power swich can be obained using (21) I Qmax = (1+nD max)i o = (1+4 0.625) 1 = 14.93 A. (55) D max ( max ) 0.625 (1 0.6255) Therefore, a power MOSFET IRFB4321PBF wih V DS =150 V and I D = 85 A is seleced. III. COMPARISON WITH CONVENTIONAL TOPOLOGIES A. Comparison wih convenional SEPIC converer In his secion, he proposed converer is compared wih convenional coupled inducor SEPIC converer. The volage gain in he proposed converer is higher for any duy cycle by adding only one diode. Wih higher volage gain, he swich volage sress in he proposed converer is lower han he convenional SEPIC converer when n>1. In order o achieve a high volage gain, usually n is more han one, which helps o choose a low volage and low R DS, ON MOSFETs. This can lead o lower conducion and swiching loss and hereby he efficiency can be improved. Anoher feaure of he proposed converer is ha he curren on he primary and secondary winding, power swich, inermediae capacior (C dc in compare wih C ac) is always lower han he convenional SEPIC converer when n 1. Table I compares he proposed Quasi-SEPIC converer wih is convenional counerpar. TABLE I. COMPARISON OF THE PROPOSED CONVERTER FEATURES WITH CONVENTIONAL ISOLATED SEPIC CONVERTER Parameers SEPIC (Fig. 1(a)) Proposed quasi-sepic (Fig. 1(b)) Volage gain expression [ V O ] nd 1 + n 6 7 Toal no. of componens (including C in and C ou ) No. of swich 1 1 No. of diode 1 2 No. of capacior 3 3 No. of coupled inducor 1 1 Volage sress on swich Q Curren sress on swichq Volage Sress on diode Volage sress on capacior Curren sress on winding Curren sress on capacior Curren sress on diode n ndi O D() n (n + D)I O D() D n 1 D 2 1 + n NA C ac n NA C dc NA 1 + nd i N1 i N2 C ac C dc D 1 D 2 Mode 1: n(n+1)i O D Mode 2: (n+1)i O Mode 1: (n+1)i O D Mode 2: (n+1)i O n() Mode 1: (n+1)i O D Mode 2: (n+1)i O NA I O NA Noe: NA is no applicable. Mode 1: ni O D Mode 2: ni O Mode 1: I O D Mode 2: I O NA Mode 1: I O D Mode 2: I O I O D I O

B. Comparison wih oher converer wih similar volage gain Higher boos converer opologies are also available in he lieraure using muli-sage and/or volage muliplier cells or using muliple winding coupled inducors. However, for a fair comparison, only opologies wih one wo-winding coupled inducor ype converer wih one acive swiching device and similar volage sress are considered for comparison. Hence quadraic boos ype and opologies wih wo or more han wo swiches are excluded from he comparison along wih hree winding coupled inducor opologies. Table II compares he proposed converer wih oher wo winding coupled inducor converers. Topologies presened in [32]-[34] produce he same volage gain as of he proposed opology; however he number of capaciors and diodes are higher han he proposed opology. Wih wo magneic elemens in [35]-[37], hese converers require more space whils heir volage gains are significanly lower. Similarly, he volage gain for he opology presened in [38] and [39] are higher han he proposed converer; however, he number of componens is higher han he proposed opology. These wo opologies are considered o be compared fair wih he exended circui of he proposed opology and hence will be discussed in Secion IV. Fig. 9 compares he volage gain of he proposed converer and he presened converers in [32]-[39]. TABLE II COMPARISON OF THE PROPOSED CONVERTER WITH DIFFERENT TWO WINDING COUPLED INDUCTOR BASED SINGLE SWITCH HIGH VOLTAGE DC-DC CONVERTERS. Ref. Proposed Converer Converer in [32] Volage Gain (G v = V O V dc ) 1 + n 1 + n Volage Sress on No. of componens Swich Coupledinducor L D C* S/W () 1 0 2 3 1 V dc V dc () 1 1 2 4 1 Converer in [33] 1 + n V dc () 1 1 4 5 1 Converer in [34] Converer in [35] and [36] Converer in [37] Converer in [38], And[39] 1 + n V dc () 1 0 3 4 1 D(1 + n) V dc () 1 1 2 2 1 1 + nd V dc () 1 1 2 3 1 1 + n + nd V dc () 1 0 4 5 1 *Including inpu and oupu capacior Fig. 9. Comparison of volage gain of he proposed converer wih differen wo-winding inducor based high boos single swich-swich dc-dc converer in CCM (n = 2).

IV. DERIVATIVE CONVERTER WITH HIGHER VOLTAGE GAIN The volage gain of he proposed converer can be raised furher by adding one diode and one capacior o is srucure as shown in Fig. 10. The oupu capacior C o is spli ino wo capaciors (C o1 & C o2) and D 3 is insered beween he negaive erminal of he load and he secondary winding of he ransformer. In CCM as shown in Fig. 11, here are wo modes in one swiching cycle. When he power swich is urned ON, he diode D 1 becomes forward biased while diodes D 2 and D 3 become reverse biased. When he power swich is urned OFF, he diode D 1 is urned OFF while D 2 and D 3 are ON. Similar analysis can be made for his exended gain converer as well. 1:n C in N 1 N 2 C dc D 1 C o1 + PWM Q D 3 D 2 C o2 R L _ V ou Fig. 10. Derivaive circui of quasi-sepic for higher volage gain. Exension of he proposed coupled-inducor quasi-sepic Appling he volage-second balance principle on he magneizing inducance leads o Tha resuls in D + () V Cdc 1+n = 0 (56) V Cdc = 1+nD (57) Using KVL in Mode 1 Also, he volage across V Co2 can be obained using KVL in Mode 2 V Co1 = V Cdc + n = 1+n (58) V Co2 = Dn (59) Therefore, he oupu volage can be obained using (58) - (59) V o = V Co1 + V Co2 = 1+n+nD (60) The volage sress across he power swich and diodes can be expressed as given in he following equaions V D1 = n V D2 = (1+n) V D3 = n (61) (62) (63) V s =. (64)

Comparing (61) (64) wih he oupu volage, i is clear ha he volage sress on all semiconducor devices is lower han he oupu volage. Paricularly, alhough he volage gain can be raised compared wih he elemenary converer proposed in Fig. 1, he volage sress on he swich remains unchanged. Therefore, he power swich wih low ON resisance (R DS,ON) can be uilized ha can lead o lower conducion loss and higher efficiency. From he volage gain view-poin, he derivaive of he proposed converer has equal volage gain wih converers ha have been presened in [38]-[39]. However, here are fewer componens in he proposed converer in Fig.10. Refer o Table II, here are five capaciors and four diodes in he presened converers in [38]-[39], while here are four capaciors and hree diodes in he proposed exension of he converer shown in Fig. 11. 1:n C in N 1 N 2 _ V Cdc + D 1 C dc + V Co1 _ C o1 + PWM Q D 3 D 2 V + Co2 _ C o2 R L _ V ou 1:n (a) C in N 1 N 2 _ V Cdc + D 1 C dc + V Co1 _ C o1 + PWM Q D 3 D 2 + V Co2 _ C o2 R L _ V ou (b) Fig. 11. Equivalen circuis during one swiching cycle (a) Mode 1 (Q ON), and (b) Mode 2 (Q OFF). V. SIMULATION AND EXPERIMENTAL RESULTS Simulaions were carried ou in Malab-Simulink wih PLECS oolboxes included o verify he performance of he proposed converer. The converer was simulaed wih N = 4, (N 1 : N 2 = 1: 4), D = 0.5 and f s = 100 khz. Wih hese condiions, he oupu volage is boosed o V O = 398 V using a V dc = 40 V, which is consisen wih (6) as shown in he sish race of Fig. 12 (a). The drain source volage of he swich are around 80 V as shown in he firs race of Fig. 12 (b), which helps o selec a low volage and a low R DS-on swich. Oher simulaed waveforms are also noed o be in agreemen wih he heoreical values derived in Secion-II. The performances expeced from he converer are hus verified in simulaions. In order o verify he funcionaliy and validae he repored analysis, a 400 W prooype of he proposed quasi-sepic converer (Fig. 1(b)) is implemened as shown in Fig. 13. This prooype is designed o achieve a volage gain of 10

from a dc inpu volage ( ) of 40 V, i.e. he oupu volage (V ou ) is se o be 400 V. Hence, for he seleced value of n = 4, he duy cycle (D) is se o be 50 %. The parameers of his prooype are as lised in Table III, where hese parameers are designed as explained before. Inpu dc volage ( ) Volage across he swich (v s) Inpu curren (i in) & curren hrough he primary winding (i N1) Curren hrough he swich (i s ) Volage across he primary winding (v N1 ) Volage across he Diode D 1 (v D1) Volage across he secondary winding (v N2 ) Curren hrough he Diode D 1 (i D1) Curren hrough he secondary winding (i N2) Volage across he Diode D 2 (v D2 ) Oupu volage (V O) Curren hrough he Diode D 2 (v D2) 0.1 µs/div 0.1 µs/div (a) (b) Fig. 12. Simulaed waveforms of he proposed converer a N = 4, D = 0.5, = 40 V and f s = 100 khz a full load: (a) inpu-oupu volage and coupled inducor winding volage/curren waveforms, and (b) semiconducor volage and curren waveforms. The seady-sae open-loop experimenal resuls of his prooype are shown in Fig. 14, in which Fig. 14(a) shows he oupu volage (v ou ), he volage across C dc (v Cdc ), and he volage across he swich (v s ), while Fig. 14(b) shows he inpu curren (i in ) and he swich curren (i Q ) wih v s. Then, Fig. 14(c) shows he coupled inducors primary and secondary side volages (v pr and v sr respecively) wih v s. Noe ha an oupu volage of 385 V has been achieved a full-load under open-loop condiion due o he volage drop in he parasiic resisances and he non-ideal coupled inducors. I is worh o noe ha his prooype uilizes an RCD snubber across he primary side in order o miigae he effec of he leakage inducance of he coupled inducors and preven he swich from any volage spikes. In order o emphasize he imporance of his snubber, Fig. 15 shows he volage across he swich (v s ) wihou and wih he RCD snubber a full-load. Fig. 15(a) shows v s wihou he RCD snubber and he peak volage of he spike is lower han he raed volage of he swich, i.e. smaller ha 150 V. Meanwhile, Fig. 15(b) shows v s wih he RCD snubber and he volage is effecively clamped. Noe ha he coupled inducors have been implemened wih an inerleaved design in order o minimize he leakage inducance, minimize he snubber circui requiremens, and improve he efficiency as a consequence. Finally, he efficiency of he proposed converer has been measured using KineiQ PPA5530 power analyzer, and he obained resuls are as shown in Fig. 16(a). This figure shows ha a maximum efficiency of 96.2 % has been obained.

As shown in Fig. 16(b), he I 2 R losses in he swich and he snubber accouns he major losses in he converer. This is as expeced from he converer, as he curren in he primary winding and hence he curren in he swich is proporional o he volage gain of he converer (55). However, he reducion of volage sress on he swich helps o selec a lower volage and lower R DS,on swich wih lower conducion loss. These differen resuls verify he prior inroduced analysis and discussions, and confirm he funcionaliy of he proposed converer. TABLE III PARAMETERS OF THE 400 W QUASI-SEPIC CONVERTER PROTOTYPE 40 V V ou 400 V n 4 D 50 % C dc 4.4 μf C ou 1 μf f s 100 khz L m 39 μh Fig. 13. A 400 W quasi-sepic converer prooype. Noe ha he converer diodes (D 1 and D 2 ) are on he boom of he PCB. (a) (b) (c) Fig. 14. Obained seady-sae experimenal resuls of he 400 W quasi-sepic converer a full-load. (a) Oupu volage (v ou ), volage across C dc (v Cdc ), and volage across he swich (v s ); (b) inpu curren (i in ), swich curren (i s ), and volage across he swich (v s ); and (c) coupled inducors primary side volage (v pr ), coupled inducors secondary side volage (v sr ), and volage across he swich (v s ).

(a) (b) Fig. 15. Experimenal resuls of he 400 W quasi-sepic converer swich volage (v s ) a full-load, where (a) shows v s wihou he RCD snubber, while (b) shows v s wih he RCD snubber. (a) (b) Fig. 16. (a) Measured efficiency of he 400 W quasi-sepic converer a a volage gain of 10 ( = 40 V), and (b) major power loss disribuion a full load. VI. CONCLUSION An efficien and high volage gain modified coupled-inducor SEPIC dc-dc converer has been inroduced in his paper wih deailed heoreical explanaions. Addiionally, seady-sae analysis and mahemaical derivaions of he proposed converer has been shown sequenially. Compared o equivalen opologies wih similar volage gain expression, he proposed opology uses lower componen-couns o achieve he same or even higher volage gain. This helps o design a very compac and ligh-weigh converer wih higher power densiy and reliabiliy. The volage sress on he swich is minimal, which helps he designer o use a low volage and R DS-on MOSFET, resuling in a reducion in cos, conducion losses and urn ON losses of he swich. Simulaion and experimenal resuls have verified hese feaures in addiion o pracicaliy of he proposed converer for various power applicaions. The measured efficiency of he converer over a wide range of load is above 95% wih a peak efficiency of 96% a a volage gain of 10, which is comparaively higher han he convenional converer having similar volage gains and power levels. These demonsraed performances clearly show he proposed opology as a compeiive alernaive for a pracical applicaion where a high volage gain is demanded, such as for a fuel cells, PV and high volage Ligh Emiing Diode (LED) lamps.

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