TVS Diodes Transient Voltage Suppressor Diodes ESD102-U2-099EL 2-Line Ultra-low Capacitance ESD / Transient Protection Diodes ESD102-U2-099EL Data Sheet Revision 1.1, 2013-05-15 Final Power Management & Multimarket
Edition 2013-05-15 Published by Infineon Technologies AG 81726 Munich, Germany 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Revision History: Revision 1.0, 2013-03-21 Page or Item Subjects (major changes since previous revision) Revision 1.1, 2013-05-15 Trademarks of Infineon Technologies AG AURIX, BlueMoon, COMNEON, C166, CROSSAVE, CanPAK, CIPOS, CoolMOS, CoolSET, CORECONTROL, DAVE, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPACK, EconoPIM, EiceDRIVER, EUPEC, FCOS, HITFET, HybridPACK, ISOFACE, I²RF, IsoPACK, MIPAQ, ModSTACK, my-d, NovalithIC, OmniTune, OptiMOS, ORIGA, PROFET, PRO-SIL, PRIMARION, PrimePACK, RASIC, ReverSave, SatRIC, SIEGET, SINDRION, SMARTi, SmartLEWIS, TEMPFET, thinq!, TriCore, TRENCHSTOP, X-GOLD, XMM, X-PMU, XPOSYS. Other Trademarks Advance Design System (ADS) of Agilent Technologies, AMBA, ARM, MULTI-ICE, PRIMECELL, REALVIEW, THUMB of ARM Limited, UK. AUTOSAR is licensed by AUTOSAR development partnership. Bluetooth of Bluetooth SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirstGPS of Trimble Navigation Ltd. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsoft Corporation. FlexRay is licensed by FlexRay Consortium. HYPERTERMINAL of Hilgraeve Incorporated. IEC of Commission Electrotechnique Internationale. IrDA of Infrared Data Association Corporation. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MathWorks, Inc. MAXIM of Maxim Integrated Products, Inc. MICROTEC, NUCLEUS of Mentor Graphics Corporation. Mifare of NXP. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. murata of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Systems Inc. RED HAT Red Hat, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Sattelite Radio Inc. SOLARIS of Sun Microsystems, Inc. SPANSION of Spansion LLC Ltd. Symbian of Symbian Software Limited. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tektronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limited. VERILOG, PALLADIUM of Cadence Design Systems, Inc. VLYNQ of Texas Instruments Incorporated. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zetex Limited. Last Trademarks Update 2010-06-09 Final Data Sheet 3 Revision 1.1, 2013-05-15
2-Line Ultra-low Capacitance ESD / Transient Protection Diodes 1 2-Line Ultra-low Capacitance ESD / Transient Protection Diodes 1.1 Features ESD / transient protection of high speed data lines exceeding: IEC61000-4-2 (ESD): ±20 kv (air / contact) IEC61000-4-4 (EFT): ±2.5 kv / 50 A (5/50ns) IEC61000-4-5 (Surge): ±3 A (8/20μs) Maximum working voltage: V RWM = 3.3 V Ultra low capacitance C L = 0.4 pf (typ.) I/O to GND, 0.2 pf (typ.) I/O to I/O Very low clamping voltage: V CL = 8 V (typ.) at I PP = 16 A Very low dynamic resistance: R DYN = 0.19 Ω (typ.) TSLP-4-10 package with pad pitch 0.4 mm, smallest 2 line package Pb-free and halogen free package (RoHS compliant) 1.2 Application Examples USB 3.0, 10/100/1000 Ethernet, Firewire DVI, HDMI, S-ATA, DisplayPort Mobile HDMI Link, MDDI, MIPI, etc. 1.3 Product Description Pin 1 TSLP-4-x ESD102-U2-099EL Pin 1 Pin 4 A1 A2 A1 A2 B1 B2 a) Pin configuration B1 B2 Pin 2 Pin 3 b) Schematic diagram PG-TSLP-4-x_Dual_Diode_PinConf_and_SchematicDiag.vsd Figure 1 Pin Configuration and Schematic Diagram Table 1 Ordering Information Type Package Configuration Marking code ESD102-U2-099EL TSLP-4-10 2 Lines anti-parallel, uni-directional B Final Data Sheet 4 Revision 1.1, 2013-05-15
Characteristics 2 Characteristics Table 2 Maximum Rating at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Min. Typ. Max. ESD air / contact discharge 1) V ESD -20 20 kv Peak pulse current (t p = 8/20 μs) 2) I PP -3 3 A Operating temperature T OP -40 125 C Storage temperature T stg -65 150 C 1) V ESD according to IEC61000-4-2 2) I PP according to IEC61000-4-5 2.1 Electrical Characteristics at T A = 25 C, unless otherwise specified V F Forward voltage I F R DYN Dynamic resistance I F Forward current V Trig Triggering reverse voltage V R Reverse voltage I PP V CL Clamping voltage I R Reverse current R DYN V Hold Holding reverse voltage V RWM Reverse working voltage maximum V Trig V Hold V RWM V FC Forward clamping voltage V R V CL I RWM V FC V F I Trig Triggering reverse current I Trig I Hold I Hold I PP Holding reverse current Peak pulse current R DYN I RWM Reverse working current maximum -I PP Figure 2 Definitions of electrical characteristics[1] I R Diode_Characteristic_Curve_with _snapback_uni-directional.vsd Table 3 DC Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Reverse working voltage V RWM 3.3 V I/O to GND Reverse current I R 1 50 na V R = 3.3 V, I/O to GND Final Data Sheet 5 Revision 1.1, 2013-05-15
Characteristics Table 4 RF Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Line capacitance 1) C L 0.4 0.65 pf V R = 0 V, f = 1 MHz, I/O to GND 0.2 0.35 pf V R = 0 V, f = 1 MHz, I/O to I/O Channel capacitance matching between I/O to GND Channel capacitance matching between I/O to I/O 1) Total capacitance line to ground C i/o-gnd 0.01 pf V R = 0 V, f = 1 MHz, I/O to GND C i/o-i/o 0.005 pf V R = 0 V, f = 1 MHz, I/O to I/O Table 5 ESD Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Clamping voltage 1) [2] V CL 8 V I TLP = 16 A, from I/O to GND 11 V I TLP = 30 A, from I/O to GND Forward clamping voltage 1) [2] V FC 6 V I TLP = 16 A, from GND to I/O 9 V I TLP = 30 A, from GND to I/O Dynamic resistance 1) [2] R DYN 0.19 Ω I/O to GND 0.23 Ω GND to I/O 1) Please refer to Application Note AN210. TLP parameter: Z 0 = 50 Ω, t p = 100ns, t r = 300ps, averaging window: t 1 = 30 ns to t 2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristic between I TLP1 = 10 A and I TLP2 = 40 A. Final Data Sheet 6 Revision 1.1, 2013-05-15
Typical Characteristics at T A = 25 C, unless otherwise specified 3 Typical Characteristics at T A = 25 C, unless otherwise specified 10-7 10-8 I R [A] 10-9 10-10 10-11 10-12 0 1 2 3 4 V R [V] Figure 3 Reverse current, I R = (V R ) 10-6 10-7 I R [A] 10-8 10-9 25 50 75 100 125 150 T A [ C] Figure 4 Reverse current: I R = f(t A ), V R = 3.3 V Final Data Sheet 7 Revision 1.1, 2013-05-15
Typical Characteristics at T A = 25 C, unless otherwise specified 0.8 0.7 0.6 C L [pf] 0.5 0.4 0.3 0.2 0 0.5 1 1.5 2 2.5 3 3.5 V R [V] Figure 5 Line capacitance: C L = f(v R ), f = 1MHz, from I/O to GND Final Data Sheet 8 Revision 1.1, 2013-05-15
Typical Characteristics at T A = 25 C, unless otherwise specified 50 40 ESD102-U2-099EL R DYN 25 20 30 15 R DYN = 0.19 Ω 20 10 I TLP [A] 10 0-10 5 0-5 Equivalent V IEC [kv] -20-10 R DYN = 0.23 Ω -30-15 -40-20 -50-25 -25-20 -15-10 -5 0 5 10 15 20 25 V TLP [V] Figure 6 Clamping voltage V TLP = f(i TLP )[2] Note: TLP parameter: Z 0 = 50 Ω, t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristic between I TLP1 = 10 A and I TLP2 = 40 A. The equivalent stress level V IEC according IEC 61000-4-2 (R = 330 Ω, C = 150 pf) is calculated at the broad peak of the IEC waveform at t = 30 ns with 2 A / kv Final Data Sheet 9 Revision 1.1, 2013-05-15
Typical Characteristics at T A = 25 C, unless otherwise specified 5 ESD102-U2-099EL R DYN 4 3 R DYN = 0.70 Ω 2 1 I PP [A] 0-1 -2 R DYN = 0.44 Ω -3-4 -5-10 -8-6 -4-2 0 2 4 6 8 10 V CL [V] Figure 7 Pulse current (IEC61000-4-5) versus clamping voltage: I PP = f(v CL ) Final Data Sheet 10 Revision 1.1, 2013-05-15
Typical Characteristics at T A = 25 C, unless otherwise specified 80 Scope: 6 GHz, 20 GS/s V CL [V] 60 40 20 V CL-max-peak = 81 [V] V CL-30ns-peak = 7 [V] 0-20 -100 0 100 200 300 400 500 600 700 800 900 t p [ns] Figure 8 IEC61000-4-2 V CL = f(t), 8 kv positive pulse from pin 1 to pin 2 20 0 Scope: 6 GHz, 20 GS/s V CL [V] -20-40 -60 V CL-max-peak = -72 [V] V CL-30ns-peak = -3 [V] -80-100 0 100 200 300 400 500 600 700 800 900 t p [ns] Figure 9 IEC61000-4-2 V CL = f(t), 8 kv negative pulse from pin 1 to pin 2 Final Data Sheet 11 Revision 1.1, 2013-05-15
Typical Characteristics at T A = 25 C, unless otherwise specified 100 Scope: 6 GHz, 20 GS/s 80 V CL [V] 60 40 V CL-max-peak = 104 [V] V CL-30ns-peak = 9 [V] 20 0-20 -100 0 100 200 300 400 500 600 700 800 900 t p [ns] Figure 10 IEC61000-4-2 V CL = f(t), 15 kv positive pulse from pin 1 to pin 2 20 0 Scope: 6 GHz, 20 GS/s -20 V CL [V] -40-60 V CL-max-peak = -98 [V] V CL-30ns-peak = -7 [V] -80-100 -100 0 100 200 300 400 500 600 700 800 900 t p [ns] Figure 11 IEC61000-4-2 V CL = f(t), 15 kv negative pulse from pin 1 to pin 2 Final Data Sheet 12 Revision 1.1, 2013-05-15
Package Information 4 Package Information 4.1 TSLP-4-10 (mm) Top view Pin 1 marking 0.05 MAX. +0.1 0.31-0.2 0.25 Bottom view 0.75 ±0.035 1) ±0.035 0.4 2 3 1 4 0.4 1) ±0.035 0.25 0.75 ±0.035 Figure 12 1) Dimension applies to plated terminals TSLP-4-10: Package outline (dimension in mm) TSLP-4-10-PO V01 0.4 0.4 0.25 Figure 13 TSLP-4-10: Footprint (dimension in mm) TSLP-4-10-FP V01 0.4 Pin 1 marking 0.92 8 2 0.92 TSLP-4-10-TP V01 Figure 14 TSLP-4-10: Packing dimension in mm) Pin 1 marking 1 Type code TSLP-4-10-MK V01 Figure 15 TSLP-4-10: Marking (example) Final Data Sheet 13 Revision 1.1, 2013-05-15
References References [1] On-chip ESD protection for integrated circuits, Albert Z. H. Wang, ISBN:0-7923-7647-1 [2] Infineon Technologie AG - Application Note AN210: Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology [3] Infineon Technologie AG - Application Note AN240: Effective ESD Protection for USB3.0, combined with perfect Signal Intergrity. Final Data Sheet 14 Revision 1.1, 2013-05-15
www.infineon.com Published by Infineon Technologies AG