18-bit bus-interface D-type flip-flop with reset and enable; 3-state Rev. 5 22 January 2018 Product data sheet 1 General description 2 Features and benefits The 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The has two 9-bit wide buffered registers with clock enable (pin nce) and master reset (pin nmr) which are ideal for parity bus interfacing in high microprogrammed systems. The registers are fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition is transferred to the corresponding output of the flip-flop. It is designed for V CC operation from 2.5 V to 3.0 V with I/O compatibility to 5 V. Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops 5 /O compatible Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up 3-state Power-up reset No bus current loading when output is tied to 5 V bus Output capability: +64 ma to -32 ma Latch-up protection: JESD78: exceeds 500 ma ESD protection: MIL STD 883, method 3 015: exceeds 2000 V MM: exceeds 200 V
3 Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version DL -40 C to +85 C SSOP56 plastic shrink small outline package; 56 leads; body width 7.5 mm DGG -40 C to +85 C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm 4 Functional diagram SOT371-1 SOT364-1 1OE 1MR 1CE 1CP 2OE 2MR 2CE 2CP 2 1 55 56 27 28 30 29 EN1 R2 G3 3C4 EN5 R6 G7 7C8 1D0 54 4D 1,2 3 10 1D1 52 5 11 1D2 51 6 12 1D3 49 8 13 1D4 48 9 14 1D5 47 10 15 1D6 45 12 16 1D7 44 13 17 1D8 43 14 18 2D0 42 8D 5,6 15 20 2D1 41 16 21 2D2 40 17 22 2D3 38 19 23 2D4 37 20 24 2D5 36 21 25 2D6 34 23 26 2D7 33 24 27 2D8 31 26 28 Figure 1. IEC logic symbol 001aad242 V CC data input to internal circuit 001aad245 Figure 2. Bushold circuit (one data input) All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 2 / 18
nce nd0 nd1 nd2 nd3 nd4 nd5 nd6 nd7 nd8 ncp CP CP CP CP CP CP CP CP CP nd nd nd nd nd nd nd nd nd R R R R R R R R R nmr noe n0 n1 n2 n3 n4 n5 n6 n7 n8 001aad243 Figure 3. Logic diagram All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 3 / 18
5 Pinning information 5.1 Pinning 1MR 1 56 1CP 1OE 2 55 1CE 10 3 54 1D0 4 53 11 5 52 1D1 12 6 51 1D2 V CC 7 50 V CC 13 8 49 1D3 14 9 48 1D4 15 10 47 1D5 11 46 16 12 45 1D6 17 13 44 1D7 18 20 14 15 43 42 1D8 2D0 21 16 41 2D1 22 17 40 2D2 18 39 23 19 38 2D3 24 20 37 2D4 25 21 36 2D5 V CC 22 35 V CC 26 23 34 2D6 27 24 33 2D7 25 32 28 26 31 2D8 2OE 27 30 2CE 2MR 28 29 2CP 001aad403 Figure 4. Pin configuration All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 4 / 18
Table 2. Pin description 5.2 Pin description Symbol Pin Description 1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7, 1D8 10, 11, 12, 13, 14, 15, 16, 17, 18 2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7, 2D8 20, 21, 22, 23, 24, 25, 26, 27, 28 54, 52, 51, 49, 48, 47, 45, 44, 43 3, 5, 6, 8, 9, 10, 12, 13, 14 42, 41, 40, 38, 37, 36, 34, 33, 31 15, 16, 17, 19, 20, 21, 23, 24, 26 data inputs data outputs data inputs data outputs 1MR, 2MR 1, 28 master reset input (active-low) 1OE, 2OE 2, 27 output enable inputs (active LOW) 1CP, 2CP 56, 29 clock pulse inputs (active rising edge) 1CE, 2CE 55, 30 clock enable input (active-low) 4, 11, 18, 25, 32, 39, 46, 53 ground (0 V) V CC 7, 22, 35, 50 supply voltage 6 Functional description Table 3. Function table [1] Operating mode Input Output noe nmr nce ncp ndn nn clear L L X X X L load and read data L H L h H l L hold L H H X NC high-impedance H X X X X Z [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; NC = no change; X = don t care; Z = high-impedance OFF-state; = LOW-to-HIGH clock transition; = not a LOW-to-HIGH clock transition. All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 5 / 18
7 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage -0.5 +4.6 V input voltage V O output voltage output in OFF-state or HIGH-state [1] [1] -0.5 +7.0 V -0.5 +7.0 V I IK input clamping current < 0 V - -50 ma I OK output clamping current V O < 0 V - -50 ma I O output current output in LOW-state - 128 ma output in HIGH-state -64 - ma T stg storage temperature -65 +150 C T j junction temperature [2] - 150 C [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 8 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V CC = 2.5 V V CC supply voltage 2.3-2.7 V input voltage 0-5.5 V I OH HIGH-level output current - - -8 ma I OL LOW-level output current none - - 8 ma current duty cycle 50 %; f 1 khz - - 24 ma Δt/Δv input transition rise or fall rate outputs enabled - - 10 ns/v T amb ambient temperature in free air -40 - +85 C V CC = 3.3 V V CC supply voltage 3.0-3.6 V input voltage 0-5.5 V I OH HIGH-level output current - - -32 ma I OL LOW-level output current none - - 32 ma current duty cycle 50 %; f 1 khz - - 64 ma Δt/Δv input transition rise or fall rate outputs enabled - - 10 ns/v T amb ambient temperature in free air -40 - +85 C All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 6 / 18
9 Static characteristics Table 6. Static characteristics At recommended operating conditions; T amb = 40 C to +85 C; voltages are referenced to (ground = 0 V). Symbol Parameter Conditions Min Typ [1] Max Unit V CC = 2.5 V ± 0.2 V K input clamping voltage V CC = 2.3 V; I IK = -18 ma - -0.85-1.2 V H HIGH-level input voltage 1.7 - - V L LOW-level input voltage - - 0.7 V V OH V OL V OL(pu) I I HIGH-level output voltage LOW-level output voltage power-up LOW-level output voltage input leakage current V CC = 2.3 V to 2.7 V; I O = -100 μa V CC - 0.2 V CC - V V CC = 2.3 V; I O = -8 ma 1.8 2.5 - V V CC = 2.3 V; I O = 100 μa - 0.07 0.2 V V CC = 2.3 V; I O = 24 ma - 0.3 0.5 V V CC = 2.3 V; I O = 8 ma - - 0.4 V V CC = 2.7 V; I O = 1 ma; = V CC or control pins [2] - - 0.55 V V CC = 2.7 V; = V CC or - 0.1 ±1 μa V CC = 0 V to 2.7 V; = 5.5 V - 0.1 10 μa I/O data pins V CC = 2.7 V; = V CC - 0.1 1 μa V CC = 2.7 V; = 0 V - +0.1-5 μa I OFF power-off leakage current V CC = 0 V; or V O = 0 V to 4.5 V - +0.1 ±100 μa I BHL bus hold LOW current data inputs; V CC = 2.3 V; = 0.7 V I BHH bus hold HIGH current data inputs; V CC = 2.3 V; = 1.7 V I EX external current output HIGH-state when V O > V CC ; V O = 5.5 V; V CC = 2.3 V I O(pu\pd) I OZ I CC power-up/power-down output current OFF-state output current supply current V CC 1.2 V; V O = 0.5 V to V CC ; = or V CC V CC = 2.7 V; = L or H [3] [4] [4] [5] - 100 - μa - -70 - μa - 10 125 μa - 1 ±100 μa output HIGH state; V O = 2.3 V - 0.5 5 μa output LOW-state; V O = 0.5 V - +0.5-5 μa V CC = 2.7 V; = or V CC ; I O = 0 A outputs HIGH-state - 0.04 0.1 ma outputs LOW-state - 2.7 4.5 ma outputs disabled ΔI CC additional supply current per input pin; V CC = 2.3 V to 2.7 V; one input at V CC - 0.6 V, other inputs at V CC or [6] [7] - 0.04 0.1 ma - 0.04 0.4 ma C I input capacitance = 0 V or V CC - 3 - pf C O output capacitance /O = 0 V or 3.0 V - 9 - pf All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 7 / 18
Symbol Parameter Conditions Min Typ [1] Max Unit V CC = 3.3 V ± 0.3 V K input clamping voltage V CC = 3.0 V; I IK = -18 ma - -0.85-1.2 V H HIGH-level input voltage 2.0 - - V L LOW-level input voltage - - 0.8 V V OH V OL V OL(pu) I I HIGH-level output voltage LOW-level output voltage power-up LOW-level output voltage input leakage current V CC = 3.0 V to 3.6 V; I O = -100 μa V CC - 0.2 V CC - V V CC = 3.0 V; I O = -32 ma 2.0 2.3 - V V CC = 3.0 V; I O = 100 μa - 0.07 0.2 V V CC = 3.0 V; I O = 16 ma - 0.25 0.4 V V CC = 3.0 V; I O = 32 ma - 0.3 0.5 V V CC = 3.0 V; I O = 64 ma - 0.4 0.55 V V CC = 3.6 V; I O = 1 ma; = V CC or control pins [2] - - 0.55 V V CC = 3.6 V; = V CC or - 0.1 ±1 μa V CC = 0 V or 3.6 V; = 5.5 V - 0.1 10 μa I/O data pins V CC = 3.6 V; = V CC - 0.5 1 μa V CC = 3.6 V; = 0 V - +0.1-5 μa I OFF power-off leakage current V CC = 0 V; or V O = 0 V to 4.5 V - 0.1 ±100 μa I BHL bus hold LOW current data inputs; V CC = 3 V; = 0.8 V 75 130 - μa I BHH bus hold HIGH current data inputs; V CC = 3 V; = 2.0 V -75-140 - μa I BHLO I BHHO bus hold LOW overdrive current bus hold HIGH overdrive current data inputs; V CC = 3.6 V; = 0 V to 3.6 V data inputs; V CC = 3.6 V; = 0 V to 3.6 V I EX external current output HIGH-state when V O > V CC ; V O = 5.5 V; V CC = 3.0 V I O(pu\pd) I OZ I CC power-up/power-down output current OFF-state output current supply current V CC 1.2 V; V O = 0.5 V to V CC ; = or V CC V CC = 3.6 V; = L or H [3] [8] [8] [9] 500 - - μa 500 - - μa - 10 125 μa - 1 ±100 μa output HIGH state; V O = 3.0 V - 0.5 5 μa output LOW-state; V O = 0.5 V - +0.5-5 μa V CC = 3.6 V; = or V CC ; I O = 0 A outputs HIGH-state - 0.06 0.1 ma outputs LOW-state - 3.9 5.5 ma outputs disabled ΔI CC additional supply current per input pin; V CC = 3 V to 3.6 V; one input at V CC - 0.6 V, other inputs at V CC or [6] [7] - 0.06 0.1 ma - 0.04 0.4 ma All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 8 / 18
Symbol Parameter Conditions Min Typ [1] Max Unit C I input capacitance = 0 V or V CC - 3 - pf C O output capacitance /O = 0 V or 3.0 V - 9 - pf [1] All typical values for V CC = 2.5 V ± 0.2 V are measured at V CC = 2.5 V and T amb = 25 C. All typical values for V CC = 3.3 V ± 0.3 V are measured at V CC = 3.3 V and T amb = 25 C. [2] For valid test results, data must not be loaded into the flip-flops after applying power. [3] Unused pins at V CC or. [4] Not guaranteed. [5] This parameter is valid for any V CC between 0 V and 1.2 V with a transition time of up to 10 ms. From V CC = 1.2 V to V CC = 2.5 V ± 0.2 V a transition time of 100 μs is permitted. This parameter is valid for T amb = 25 C only. [6] I CC is measured with outputs pulled up to V CC or pulled down to ground. [7] This is the increase in supply current for each input at the specified voltage level other than V CC or. [8] This is the bus hold overdrive current required to force the input to the opposite logic state. [9] This parameter is valid for any V CC between 0 V and 1.2 V with a transition time of up to 10 ms. From V CC = 1.2 V to V CC = 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for T amb = 25 C only. 10 Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to (ground = 0 V); T amb = 40 C to +85 C; for test circuit see Figure 9. Symbol Parameter Conditions Min Typ [1] Max Unit V CC = 2.5 V ± 0.2 V t PLH LOW to HIGH propagation delay ncp to nn; see Figure 5 1.5 2.9 4.5 ns t PHL HIGH-to-LOW propagation delay ncp to nn; see Figure 5 1.4 2.7 4.2 ns nmr to nn; see Figure 7 1.5 2.7 4.2 ns t PZH OFF-state to HIGH propagation delay noe to nn; see Figure 8 2.1 3.4 5.0 ns t PZL OFF-state to LOW propagation delay noe to nn; see Figure 8 1.8 3.0 4.7 ns t PHZ HIGH to OFF-state propagation delay noe to nn; see Figure 8 1.7 3.0 4.3 ns t PLZ LOW to OFF-state propagation delay noe to nn; see Figure 8 1.4 2.3 3.3 ns t su(h) t su(l) t h(h) t h(l) set-up time HIGH set-up time LOW hold time HIGH hold time LOW ndn to ncp; see Figure 6 1.0 0.5 - ns nce to ncp; see Figure 6 1.0 0.2 - ns ndn to ncp; see Figure 6 1.8 1.3 - ns nce to ncp; see Figure 6 0.5-0.1 - ns ndn to ncp; see Figure 6 0.1-1.4 - ns nce to ncp; see Figure 6 1.0 0.2 - ns ndn to ncp; see Figure 6 0.1-0.5 - ns nce to ncp; see Figure 6 1.0-0.1 - ns t WH pulse width HIGH ncp; see Figure 5 2.0 0.8 - ns t WL pulse width LOW ncp 3.0 2.1 - ns nmr; see Figure 7 2.0 0.8 - ns t rec recovery time nmr to ncp; see Figure 7 2.0 1.3 - ns f max maximum frequency CP; see Figure 5 150 - - MHz All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 9 / 18
Symbol Parameter Conditions Min Typ [1] Max Unit V CC = 3.3 V ± 0.3 V t PLH LOW to HIGH propagation delay ncp to nn; see Figure 5 1.0 2.3 3.1 ns t PHL HIGH-to-LOW propagation delay ncp to nn; see Figure 5 1.0 2.1 2.9 ns nmr to nn; see Figure 7 1.0 2.3 2.9 ns t PZH OFF-state to HIGH propagation delay noe to nn; see Figure 8 1.7 2.7 4.0 ns t PZL OFF-state to LOW propagation delay noe to nn; see Figure 8 1.4 2.3 3.5 ns t PHZ HIGH to OFF-state propagation delay noe to nn; see Figure 8 2.2 3.1 4.0 ns t PLZ LOW to OFF-state propagation delay noe to nn; see Figure 8 1.8 2.6 3.5 ns t su(h) t su(l) t h(h) t h(l) set-up time HIGH ndn to ncp; see Figure 6 1.0 0.5 - ns nce to ncp; see Figure 6 1.0 0.1 - ns set-up time LOW ndn to ncp; see Figure 6 1.6 1.1 - ns nce to ncp; see Figure 6 0.5-0.5 - ns hold time HIGH ndn to ncp; see Figure 6 0.1-0.7 - ns nce to ncp; see Figure 6 1.0 0.5 - ns hold time LOW ndn to ncp; see Figure 6 0.1-0.5 - ns nce to ncp; see Figure 6 1.0-0.1 - ns t WH pulse width HIGH ncp; see Figure 5 1.5 0.7 - ns t WL pulse width LOW ncp 2.5 1.4 - ns nmr; see Figure 7 2.0 1.5 - ns t rec recovery time nmr to ncp; see Figure 7 2.0 1.1 - ns f max maximum frequency CP; see Figure 5 250 - - MHz [1] All typical values for V CC = 2.5 V ± 0.2 V are measured at V CC = 2.5 V and T amb = 25 C. All typical values for V CC = 3.3 V ± 0.3 V are measured at V CC = 3.3 V and T amb = 25 C. 10.1 Waveforms and test circuit 1/f max ncp input t W t PHL t PLH V OH nn output V OL 001aaa256 Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Figure 5. Propagation delay clock input (ncp) to output (nn), clock pulse (ncp) width HIGH and maximum clock frequency All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 10 / 18
input ndn, nce t su(h) t h(h) t su(l) t h(l) input ncp 001aad401 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 6. Data set-up and hold times input nmr t WL t rec input ncp t PHL V OH output nn V OL 001aad400 Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Figure 7. Master reset pulse width, master reset to output delay and master reset to clock recovery time noe input t PLZ t PZL nn output LOW-to-OFF OFF-to-LOW V CC V OL V X t PHZ t PZH V OH nn output HIGH-to-OFF OFF-to-HIGH Measurement points are given in Table 8. outputs enabled V Y outputs disabled V OL and V OH are typical voltage output levels that occur with the output load. outputs enabled 001aal795 Figure 8. OFF-state to HIGH and LOW propagation delays and LOW and HIGH to OFF-state propagation delays All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 11 / 18
Table 8. Measurement points V CC Input Output VM VM VX VY 2.7 V 0.5 x V CC 0.5 x V CC V OL + 0.15 V V OH - 0.15 V 3.0 V 1.5 V 1.5 V V OL + 0.3 V V OH - 0.3 V t W negative pulse 0 V 90 % 10 % t f t r t r t f positive pulse 0 V 10 % 90 % t W V EXT V CC G DUT V O RL RT CL RL 001aae331 Test data is given in Table 9. Definitions test circuit: R L = Load resistance. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to output impedance Z o of the pulse generator. V EXT = Test voltage for switching times. Figure 9. Test circuit for measuring switching times Table 9. Test data Input Load V EXT f i t W t r, t f C L R L t PHZ, t PZH t PLZ, t PZL t PLH, t PHL 3.0 V or V CC whichever is less 10 MHz 500 ns 2.5 ns 50 pf 500 Ω 6 V or V CC x 2 open All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 12 / 18
11 Package outline SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 D E A X c y H E v M A Z 56 29 A 2 A 1 (A ) 3 A pin 1 index θ L p 1 28 L e b p w M detail X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) A UNIT A 1 A 2 A 3 b p c D (1) E (1) e H E L L p v w y Z (1) max. mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 18.55 18.30 7.6 7.4 0.635 10.4 10.1 1.0 1.2 1.4 0.25 0.18 0.1 0.6 1.0 0.85 0.40 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT371-1 REFERENCES IEC JEDEC JEITA MO-118 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Figure 10. Package outline SOT371-1 (SSOP56) All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 13 / 18
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 D E A X c y H E v M A Z 56 29 A 2 A 1 (A ) 3 A pin 1 index 1 28 L detail X L p θ e bp w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions). A UNIT A 1 A 2 A 3 b p c D (1) E (2) e H E L L p v w y Z max. mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 8.3 0.5 1 7.9 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Figure 11. Package outline SOT364-1 (TSSOP56) All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 14 / 18
12 Abbreviations Table 10. Abbreviations Acronym DUT ESD MIL MM MOS Description Device Under Test ElectroStatic Discharge Military Machine Model Metal-Oxide Semiconductor 13 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes v.5 20180122 Product data sheet - v.4 Modifications: The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. v.4 20050802 Product data sheet - v.3 Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. Section 2: modified Jedec Std 17 into JESD78 Section 10: changed propagation delays. v.3 19980612 Product specification - v.2 v.2 19980612 Product specification - v.1 v.1 19980303 Product specification - - All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 15 / 18
14 Legal information 14.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet ualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 14.2 Definitions Draft The document is a draft version only. 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Non-automotive qualified products Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations A non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. 17 / 18
Contents 1 General description... 1 2 Features and benefits...1 3 Ordering information... 2 4 Functional diagram...2 5 Pinning information... 4 5.1 Pinning...4 5.2 Pin description... 5 6 Functional description...5 7 Limiting values...6 8 Recommended operating conditions... 6 9 Static characteristics...7 10 Dynamic characteristics...9 10.1 Waveforms and test circuit... 10 11 Package outline...13 12 Abbreviations... 15 13 Revision history... 15 14 Legal information...16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. Nexperia B.V. 2018. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 22 January 2018 Document identifier: